Three-phase / six-phase lo generator with mixers

Abstract

Circuits for implementation in RF transmitters and receivers are described. In one implementation, the circuits can include a clock signal generator, a logic gate control signal generator, a baseband signal processor, a mixer coupled to the baseband signal processor and a plurality of logic gates, and a controller communicatively coupled to the clock signal generator and the mixer. The controller is configured to switch between a first mode and a second mode, wherein in the first mode the controller is configured to control the clock signal generator to set a clock frequency to a value cl, and in the second mode the controller is configured to control the clock signal generator to set a clock frequency to a value c2, wherein c2 is different than cl.

Description

[0001] Cross-references

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 084,464, filed on September 28, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of cellular communication technology, and in particular to a communication method and related equipment. Background Art

[0004] In wireless / wired terminals, such as cellular phones or Wi-Fi devices, multi-phase local oscillators (LOs) are generated for radio frequency (RF) transmission and reception.

[0005] In the transmit signal path of a terminal supporting the Long-Term Evolution (LTE) standard, third-order counter-intermodulation (CIM3) products can be a significant contributor to spurious emissions in protected bands, particularly when the transmit power is concentrated in a single resource block at the edge of the allocated bandwidth. This can be addressed by a harmonic rejection architecture for the upconversion mixer in the transceiver. In some implementations, the upconversion mixer retains the four-phase baseband inputs of a traditional quadrature mixer, employs various techniques in the local oscillator (LO) path (including overlapping LO waveforms and sometimes scaling factors in the signal path), and requires the digitally controlled oscillator (DCO) to operate at twice or more the LO frequency. Summary of the Invention

[0006] The present invention relates to radio frequency (RF) transmitters and receivers and methods of transmitting and receiving RF.

[0007] A first aspect of the subject matter described herein can be embodied in a radio frequency (RF) receiver. The RF receiver includes: a clock signal generator configured to generate a clock signal having a clock frequency; a logic gate control signal generator configured to generate a plurality of control signals; a plurality of logic gates configured to generate a local oscillator signal based on the clock signal and one of the plurality of control signals; a mixer coupled to a baseband signal processor and the plurality of logic gates, configured to generate an outgoing radio frequency (RF) signal, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with a plurality of baseband signals generated by the baseband generator to generate the outgoing RF signal; and a controller communicatively coupled to the clock signal generator and the mixer, wherein the controller is configured to control the clock signal generator and the mixer to switch between a first mode and a second mode. In the first mode, the controller is configured to control the clock signal generator to set the clock frequency to a value c1 and to control the mixer to mix the plurality of local oscillator signals with a first baseband signal from the plurality of baseband signals. In the second mode, the controller is used to control (1) the clock signal generator to set the clock frequency to a value c2, and control (2) the mixer to mix the multiple local oscillator signals with a second baseband signal among the multiple baseband signals, respectively, wherein c2 is different from c1, and the second baseband signal among the multiple baseband signals is different from the first baseband signal among the multiple baseband signals.

[0008] In some implementations, c1 is equal to 2c2.

[0009] In some implementations, the multiple control signals are out of phase with each other.

[0010] In some examples, the clock signal generator is disconnected from the plurality of logic gates, and inputs of the plurality of logic gates are pulled to a power supply or ground.

[0011] In some implementations, the plurality of logic gates includes one or more AND gates, one or more NAND gates, or a combination of one or more AND gates and one or more NAND gates.

[0012] In some implementations, the logic gate control signal generator includes a plurality of flip-flops, and the plurality of flip-flops and the one or more NAND gates form a three-way frequency division circuit.

[0013] In some examples, the multiple control signals are non-overlapping.

[0014] In some implementations, the LO signal is generated by a single LO circuit in both the first mode and the second mode; in the first mode, an input clock frequency is 3 times an output frequency of the mixer; and in the second mode, the input clock frequency is 1.5 times the output frequency of the mixer.

[0015] A second aspect of the subject matter described herein can be embodied in a radio frequency (RF) receiver. The RF receiver includes: a clock signal generator for generating a clock signal having a clock frequency; a logic gate control signal generator for generating a plurality of control signals; a plurality of logic gates for generating a local oscillator signal based on the clock signal and one of the plurality of control signals; a mixer coupled to a baseband signal processor and the plurality of logic gates, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with a received RF signal to generate a plurality of down-converted baseband signals; the baseband signal processor is configured to generate one or more output signals based on the plurality of down-converted baseband signals, wherein the plurality of down-converted baseband signals are received from the mixer and are out of phase with each other; and a controller communicatively coupled to the clock signal generator and the mixer, wherein the controller is configured to control the clock signal generator and the mixer to switch between a first mode and a second mode. In the first mode, the controller is configured to control the clock signal generator to set the clock frequency to a value c1, and to control the mixer to mix the multiple local oscillator signals with the received signal, respectively. In the second mode, the controller is configured to control the clock signal generator to set the clock frequency to a value c2, and to control the mixer to mix the multiple local oscillator signals with the received signal, respectively, where c2 is different from c1.

[0016] In some implementations, c1 is equal to 2c2.

[0017] In some examples, the multiple control signals are out of phase with each other.

[0018] In some implementations, in the second mode, the clock signal generator is disconnected from the plurality of logic gates, and inputs of the plurality of logic gates are pulled to a power supply or ground.

[0019] In some implementations, the plurality of logic gates includes one or more AND gates, one or more NAND gates, or a combination of one or more AND gates and one or more NAND gates.

[0020] In some implementations, the logic gate control signal generator includes a plurality of flip-flops, and the plurality of flip-flops and the one or more NAND gates form a three-way frequency division circuit.

[0021] A third aspect of the subject matter described herein can be embodied in a method for generating an RF signal. The method includes: a baseband signal processor generating a plurality of baseband signals out of phase with one another; a clock signal generator generating a clock signal having a clock frequency; a logic gate control signal generator generating a plurality of control signals; a plurality of logic gates each generating a local oscillator signal based on the clock signal and one of the control signals; a mixer coupled to the baseband signal processor and the plurality of logic gates generating an outgoing radio frequency (RF) signal, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with the plurality of baseband signals generated by the baseband generator to generate the outgoing RF signal; and a controller communicatively coupled to the clock signal generator and the mixer to control the clock signal generator and the mixer to switch between a first mode and a second mode. In the first mode, the controller is configured to control the clock signal generator to set the clock frequency to a value c1 and to control the mixer to mix the plurality of local oscillator signals with a first baseband signal of the plurality of baseband signals. In the second mode, the controller is used to control the clock signal generator to set the clock frequency to a value c2, and to control the mixer to mix the multiple local oscillator signals with a second baseband signal among the multiple baseband signals, respectively, wherein c2 is different from c1, and the second baseband signal among the multiple baseband signals is different from the first baseband signal among the multiple baseband signals.

[0022] In some implementations, c1 is equal to 2c2.

[0023] In some examples, the multiple control signals are out of phase with each other.

[0024] In some implementations, the multiple control signals are non-overlapping.

[0025] In some implementations, an input clock frequency is three times the output frequency of the mixer, and in the second mode, the input clock frequency is 1.5 times the output frequency of the mixer.

[0026] A fourth aspect of the subject matter described herein can be embodied in a method for generating an output signal based on a received RF signal. The method includes: a clock signal generator generating a clock signal having a clock frequency; a logic gate control signal generator generating a plurality of control signals; each of a plurality of logic gates generating a local oscillator signal based on the clock signal and one of the plurality of control signals; a mixer coupled to a baseband signal processor and the plurality of logic gates generating a plurality of down-converted baseband signals, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with a received RF signal; and a controller communicatively coupled to the clock signal generator and the mixer to control the clock signal generator and the mixer to switch between a first mode and a second mode. In the first mode, the controller is configured to control the clock signal generator to set the clock frequency to a value c1 and control the mixer to mix the multiple local oscillator signals with the received signal; in the second mode, the controller is configured to control the clock signal generator to set the clock frequency to a value c2 and control the mixer to mix the multiple local oscillator signals with the received signal, wherein c2 is different from c1. The method may further include: generating, by the baseband signal processor, one or more output signals based on the multiple down-converted baseband signals, wherein the multiple down-converted baseband signals are received from the mixer.

[0027] Implementations of the subject matter described herein can provide several advantages. For example, in some implementations, the present application includes a harmonic rejection architecture with six baseband phases and six non-overlapping LO phases. This architecture eliminates the need for a scaling factor, and for higher frequency bands, the DCO can operate at only 1.5 times the LO frequency. This architecture inherently offers greater uncalibrated image rejection than architectures with quadrature baseband inputs, which is advantageous for any wireless communication standard supporting high-order quadrature amplitude modulation (QAM) schemes. The subject matter described herein involves generating three-phase and six-phase signals in a manner that allows for easy switching between these two signals. The described architecture offers lower power and reduced phase noise compared to standard quadrature baseband inputs, while using smaller flip-flops, thereby saving chip area and reducing current consumption. By switching the baseband (BB) signal connected to the mixer in each mode (i.e., generating a three-phase signal or a six-phase signal), LO phase noise can be optimized. Because the LO frequency is half the frequency required for the six-phase mode, the three-phase mode operates at particularly low power without compromising phase noise performance. The three-phase mode LO frequency is doubled in the mixer to obtain the appropriate transmit frequency.

[0028] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram of an exemplary wireless communication system.

[0030] Figure 2 is a block diagram of exemplary details of a wireless device that may implement the methods and guidance provided herein.

[0031] Figure 3A and Figure 3B is an exemplary circuit diagram of six-phase LO generation and three-phase LO generation.

[0032] Figure 4A and Figure 4B yes Figure 3A and Figure 3B An exemplary timing diagram for the shown circuit.

[0033] Figure 5 is Figure 3A and Figure 3B A circuit diagram of an exemplary mixer driven by an LO signal generated by the circuit is shown.

[0034] Figure 6 FIG. 4 is a diagram of an exemplary LO generation circuit provided by an embodiment.

[0035] Figure 7 FIG. 4 is a diagram of an exemplary LO generation circuit provided by an embodiment.

[0036] Figure 8 yes Figure 6 and Figure 7 An exemplary timing diagram of the LO generation circuit is shown.

[0037] Figure 9 is Figure 6 and Figure 7 An exemplary diagram of a mixer driven by an LO signal generated by the circuit is shown.

[0038] Figure 10 is a flow chart of an exemplary method of generating an RF signal. DETAILED DESCRIPTION

[0039] Figure 1is a block diagram of an exemplary wireless communication system 100 including a wireless device 110 capable of communicating with one or more wireless communication networks. The one or more wireless communication networks with which the wireless device 110 is capable of communicating may include, but are not limited to, one or more cellular or wireless wide area networks (WWANs), one or more wireless local area networks (WLANs), one or more wireless personal area networks (WPANs), or a combination thereof.

[0040] exist Figure 1 In the example of FIG, a wireless device 110 communicates with at least one WWAN via at least one base station 120, communicates with at least one WLAN via at least one access point 130, and communicates with at least one personal area network (PAN) via at least one PAN device 140. At least one base station 120 is capable of bidirectional communication with wireless devices located within a corresponding coverage area 122 of the base station. Similarly, at least one access point 130 is capable of bidirectional communication with wireless devices located within a corresponding coverage area 132 of the access point. Figure 1 Any communication device in a communication system may include various embodiments of the present invention.

[0041] In some implementations, the at least one WWAN associated with the at least one base station 120 may be a fifth generation (5G) network, as well as networks of other generations and types. In these implementations, the at least one base station 120 may be a 5G base station that communicates with a wireless device (e.g., the wireless device 110) using orthogonal frequency division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) of less than 1 ms (e.g., 100 microseconds or 200 microseconds). For example, at least one base station 120 may be one of several devices, such as a base transceiver station (BTS), a 3G base station (NodeB), an evolved NodeB (eNB), a next generation (fifth generation, 5G) base station (gNB), a home base station (Home NodeB / Home eNodeB), a site controller, an access point or a wireless router, or a server, router, switch or other processing entity with a wired network or a wireless network. In addition, as Figure 1 As shown, the wireless device 110 is used to communicate with one or more personal area network (PAN) devices / systems 140 (e.g., or radio frequency identification (RFID) systems and devices) to communicate.

[0042] System 100 can utilize multi-channel access functionality, including at least one base station 120 and wireless device 110 for implementing the Long Term Evolution (LTE) wireless communication standard, LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS) schemes, among others. In other implementations, at least one base station 120 and wireless device 110 are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may also be used. In some examples, one or more such access schemes and wireless protocols may correspond to standards that impose RF power amplifier linearity requirements.

[0043] To communicate with at least one base station 120 and / or access point 130, wireless device 110 may include one or more transmitter and receiver components (similar or equivalent to those described below with reference to FIG. Figure 2 One or more transmitter and receiver components further described), thereby enabling multiple communications with different types of access points, base stations and other wireless communication devices.

[0044] Although Figure 1 An example of a communication system is shown, but Figure 1 For example, communication system 100 may include any number of wireless devices, base stations, access points, networks, or other components in any suitable configuration.

[0045] References below Figures 2 to 9 Examples of transceiver components and RF components that may be used in wireless device 110 and other similar devices are further detailed.

[0046] Figure 2 1 is a block diagram of exemplary details of a wireless device 110 that may implement the methods and guidance provided herein. The wireless device 110 may be, for example, a mobile phone, but in other examples may be other devices, such as a desktop computer, a laptop computer, a tablet computer, a handheld computing device, an automotive computing device, and / or other computing devices. As shown, the wireless device 110 includes at least one transmitter 210, at least one receiver 220, a memory 230, at least one processor 240, and at least one input / output device 260. In some implementations, a separate block of a transceiver is shown, rather than Figure 2 2. In other words, although the at least one transmitter 210 and the at least one receiver 220 are shown as separate blocks or components, they may be combined into a transceiver.

[0047] Furthermore, only one transmitter and one receiver are shown here, but in many embodiments, multiple transmitters and receivers (or multiple transceivers) are included to support multiple communications of different types simultaneously. Each transmitter / transceiver can employ the innovations of the present invention.

[0048] The processor 240 may implement various processing operations for the wireless device 110. For example, the processor 240 may perform signal coding, data processing, power control, input / output processing, or enable the wireless device 110 to operate in the system 100 ( Figure 1) and any other functions that perform operations in the processor 240. The processor 240 may include any suitable processing device or computing device for performing one or more operations. For example, the processor 240 may include a microprocessor, a microcontroller, a digital signal processor, a field programmable gate array or an application-specific integrated circuit, or a combination of these devices.

[0049] The transmitter 210 may be configured to modulate data or other content, filter and amplify an outgoing radio frequency (RF) signal for transmission via at least one antenna 250A. The transmitter 210 may also be configured to amplify and filter a baseband frequency signal or an intermediate frequency signal, up-convert the baseband frequency signal or the intermediate frequency signal to a radio frequency (RF) signal, and then provide the RF signal to the antenna 250A for transmission. The transmitter 210 may include any suitable structure for generating an RF signal for wireless transmission. Figure 2 Components 212 through 218 are shown to further detail other aspects of transmitter 210 .

[0050] Receiver 220 can be configured to demodulate data or other content received in an incoming RF signal via at least one antenna 250B. Receiver 220 can also be configured to amplify and filter the RF signal received via antenna 250B, downconvert the RF signal to an intermediate frequency or baseband frequency, and then convert it to digital form for processing. Receiver 220 can include any suitable structure for processing wireless received signals.

[0051] Antennas 250A and 250B may each include any suitable structure for transmitting and / or receiving wireless RF signals. In some implementations, antennas 250A and 250B may be implemented as a single antenna that can be used to transmit and receive RF signals. In an alternative implementation, separate antennas may be used for both transmission and reception.

[0052] It should be understood that one or more transmitters 210 may be used in the wireless device 110, one or more receivers 220 may be used in the wireless device 110, and one or more antennas 250 may be used in the wireless device 110. For example, in one embodiment, the device 110 includes at least three transmitters 210 and receivers 220 (or at least three transceivers) to communicate via a personal area network (e.g., ), Wi-Fi networks (e.g., networks based on IEEE 802.11), and cellular networks. These protocol transceivers (transmitter 210 and receiver 220) can all employ the concepts of the present invention.

[0053] The wireless device 110 also includes one or more input / output devices 260. The input / output devices 260 facilitate interaction with a user. Each input / output device 260 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, a microphone, a keypad, a keyboard, a display, or a touch screen.

[0054] In addition, the wireless device 110 includes at least one memory 230. The memory 230 stores instructions and data used, generated, or collected by the wireless device 110. For example, the memory 230 may store software or firmware instructions executed by one or more processors 240, as well as data used to reduce or eliminate interference in incoming signals. Each memory 230 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory may be used, such as random access memory (RAM), read-only memory (ROM), a hard disk, an optical disk, a subscriber identity module (SIM) card, a memory stick, a secure digital (SD) card, etc.

[0055] In some implementations, transmitter 210 may include signal processing circuitry 212, modulation circuitry 214, an RF front end 217, a power amplifier 216, and at least one filter 218. Signal processing circuitry 212 may include one or more circuits for processing a signal received as input (e.g., from processor 240). For example, signal processing circuitry 212 may include a digital-to-analog converter (D / A) that converts a digital input (e.g., from processor 240) into an analog signal, which is then provided to a low-pass filter. The low-pass filter filters the analog signal and provides the filtered analog signal to modulation circuitry 214. In addition to receiving the filtered analog signal from signal processing circuitry 212, modulation circuitry 214 also receives a signal from local oscillator 213 and modulates or adjusts the frequency of the signal, e.g., from a first frequency to a second frequency greater than the first frequency. For example, the modulation circuit 214 may include a mixer 219 that up-converts the filtered analog signal from a relatively low frequency (e.g., baseband frequency, or an intermediate frequency (IF) offset from the baseband frequency) to a relatively high frequency RF signal. Thus, the signal from the local oscillator 213 is used as a carrier signal in the transmitter 210. In addition, as Figure 2As shown, transmitter 210 includes an RF front end 217 that includes amplification and filtering circuits that filter and amplify the RF signal and then provide the RF signal to a VGA amplifier 215 and a power amplifier 216.

[0056] At this time, the RF signal from the RF front end 217 is amplified by the power amplifier 216 and filtered by at least one filter 218, and then provided as the output of the transmitter 210 to at least one antenna 250A for wireless transmission. Figure 2 The filter 218 is shown downstream of the power amplifier 216. In some implementations, the filter 218 can be upstream of the power amplifier 216. In this case, the RF signal from the RF front end 217 is first filtered by the at least one filter 218, then amplified by the power amplifier 216, and then provided as the output of the transmitter 210 to the at least one antenna 250A for wireless transmission.

[0057] When a cellular terminal transmits an LTE signal, third-order counter-intermodulation (CIM3) can be a significant contributor to unwanted spectral content in the antenna's output signal. The transmitter / transceiver's transmit signal path typically includes an up-conversion mixer, a variable-gain amplifier (VGA), and a power amplifier (PA) (see Figure 2 ). The baseband signal U may include a frequency of f BB The LO signal V may include a single tone signal with a fundamental frequency of f LO and the third harmonic of the RF carrier frequency is 3f LO At the mixer output X side, f BB With f LO and 3f LO Mixing produces f LO +f BB (useful signal) and 3f LO –f BB Spectral content under (modulated third harmonic, HD3).

[0058] In addition to the above mechanisms, there are three other factors that can affect the generation of CIM3. First, there is third-order nonlinearity in the analog baseband signal path. This generates 3f BB The third harmonic component under this condition is converted to f on the modulator output side. LO –3f BB, and can increase the CIM3 level depending on the phase relative to other components. Second, the mixer itself has third-order nonlinearities, which produce CIM3 products at the mixer output. This effect is more severe for passive mixers than for active mixers, but passive mixers have lower power consumption and are therefore generally preferred. Third, if the LO includes fifth harmonic content that is not suppressed by the mixer, the mixer output includes 5f LO +f BB (HD5) and this component is related to f LO +f BB The fifth-order intermodulation (IM5) between the useful signals under the LO –3f BB The harmonic suppression technology is described in more detail below with reference to the accompanying drawings.

[0059] Figure 3A and Figure 3B FIG2 is a schematic diagram of an exemplary circuit for six-phase LO generation 300 and three-phase LO generation 302. A flip-flop 304 and a negative AND (NAND) logic gate 306 form a three-way frequency divider circuit. The Qb outputs of the flip-flops (e.g., Q1b, Q2b, Q3b, Q4b, Q5b, Q6b) are 33.3% duty cycle signals that are 1 / 3 of the input clock frequency period, and these signals are interleaved at a nominal 60 degrees. Figure 4A and Figure 4B The timing diagram shown further illustrates this. Input clock 308 enters a three-way divider circuit and a set of switches 310. Switches 310 connect the flip-flop's Sw_Clk and Sw_Clkb nodes to Clk and Clkb, respectively, in six-phase mode. In three-phase mode, the switches are open, and the Sw_Clk node is pulled to the supply voltage, while the Sw_Clkb node is pulled to ground.

[0060] In six-phase mode (such as Figure 3A As shown in FIG, the output of flip-flop 304 is combined with the input clock (or "ANDed" with the input clock) as input through switch 310 and then enters AND logic gate (AND) 312 to generate a 16.67% duty cycle signal at 1 / 3 the input clock frequency. These signals are staggered at a nominal 60 degrees. The output of AND 312 includes six non-overlapping phase signals (LO_0, LO_60, LO_120, LO_180, LO_240, LO_300, LO_360), which drive the subsequent mixer switches (e.g., as shown in FIG. Figure 5As shown in Figure 3 ). The phase noise associated with the LO signal is highly dependent on the signal edges. Since AND gate 312 uses the low-frequency signal from flip-flop 304 to gate the input clock signal, the noise of the flip-flop does not appear in the output signal. This allows for the use of smaller flip-flops, saving chip area, reducing current consumption, and reducing LO phase noise. This can be seen by observing Figure 4A Note that there is a small amount of propagation delay in the Qb output, so the falling edge of the clock is the strobe signal and the noise is set for the falling edge.

[0061] exist Figure 3B In the illustrated three-phase mode 302, the output of flip-flop 304 is ANDed with either a logic high or a logic low. When ANDed with a logic high, the output of AND gate 312 is the same as the flip-flop output. ANDing with a logic low causes the output of AND gate 312 to be low, regardless of the flip-flop output. Consequently, signals LO_0, LO_120, and LO_240 are 33.3% duty cycle signals at one-third the input clock frequency, interleaved at a nominal 120 degrees. Signals LO_60, LO_180, and LO_300 remain low, disconnecting the mixer switches to which they are connected. Note that in three-phase mode, since input clock 308 is not ANDed with the output of flip-flop 304, the resulting phase noise is determined by flip-flop 304 and gate 312. Consequently, flip-flop 304 must be large enough to meet the required phase noise requirements, resulting in increased chip area and current consumption compared to a six-phase system.

[0062] Figure 4A and Figure 4B yes Figure 3A and Figure 3B An exemplary timing diagram for the shown circuit. Figure 4A The timing diagram 400 shown corresponds to Figure 4A The six-phase mode circuit shown shows that the frequency of the six phase signals (402, 404, 406, 408, 410, 412) in the six-phase mode is 1 / 3 of the input clock and the nominal duty cycle is 16.67%. These signals are 6 non-overlapping signals, interleaved with each other at a nominal 60 degrees.

[0063] Figure 4B The timing diagram 414 in FIG. 1 shows the six phase signals (402 to 412) in three-phase mode. Signals LO_0 402, LO_120 406, and LO_240 410 have a frequency of 1 / 3 the input clock and a nominal duty cycle of 33.3%. These signals are three non-overlapping signals, staggered by a nominal 120 degrees. Signals LO_60 404, LO_180 408, and LO_360 412 are always low.

[0064] Figure 5 is Figure 3A and Figure 3B Schematic diagram of an exemplary mixer 500 driven by a six-phase LO signal or a three-phase LO signal generated by the circuit shown in FIG. LO signal drives the mixer. The mixer configuration is the same in three-phase mode or six-phase mode. In three-phase mode (e.g., based on Figure 3B In the six-phase mode, all switches including LO_0 502, LO_120 506, and LO_240 512 are closed.

[0065] Figure 6 is a schematic diagram of an exemplary LO generation circuit 600 .

[0066] exist Figure 6 In the embodiment shown, the flip-flops 602, 604, 606, 608, 610 and 612 can together form a logic gate control signal generator, which can be used to generate multiple control signals. The flip-flops and the NAND gate 614 form a three-way frequency division circuit. Figure 6 NAND gates are used in the examples described in

[15] , but any suitable logic gates (e.g., AND gates) can be used. The Qb (Q1b, Q2b, Q3b, Q4b, Q5b, Q6b) outputs of the flip-flops are 33.3% duty cycle signals that are 1 / 3 the period of the input clock frequency, and these signals are staggered at a nominal 60 degrees relative to each other. Figure 8 The timing diagram shown further illustrates this. The output of the flip-flop is combined through a plurality of logic gates, each of which is used to generate a local oscillator signal based on the clock signal and one of a plurality of control signals. For example, the output of the flip-flop can be ANDed with the input clock 628 through a plurality of AND gates 616, 618, 620, 622, 624 and 626 to produce a 16.67% duty cycle control signal at 1 / 3 the input clock frequency, which are staggered with each other at a nominal 60 degrees. The output of the AND is six non-overlapping LO phase signals 630, 632, 634, 636, 638 and 640, which drive the subsequent mixer switches (e.g., Figure 9 As shown in Figure 2.2.1, the phase noise associated with the LO signal is highly dependent on the signal edges. Since the AND gate uses a low-frequency signal from the flip-flop to gate the input clock signal, the noise of the flip-flop does not appear in the output signal. This has the advantage that a smaller flip-flop can be used (compared to the Figure 3A and Figure 3B), thus saving chip area, reducing current consumption, and reducing LO phase noise. This can be seen by observing Figure 8 This can be seen in the timing diagram shown (and described further below). Note that there is a small amount of propagation delay in the Qb output, so the falling edge of the clock is the strobe signal and also sets the noise for the falling edge.

[0067] exist Figure 6 In the LO generation in the three-phase mode and the six-phase mode, the only difference is that in the six-phase mode, the frequency of the input clock 626 is three times the transmitter output frequency, while in the three-phase mode, the frequency of the input clock is 1.5 times the transmitter output frequency. In other words, for a given transmitter output frequency, the input clock 626 in the three-phase mode is half that in the six-phase mode. In the three-phase mode, this has the advantage of reducing the cost of this circuit and the circuit that provides the input clock (compared to the Figure 3A and Figure 3B This is also superior to other methods (e.g., compared to the circuit shown in Figures 3 to 4). Figure 5 One or more associated methods): Phase noise in three-phase mode is reclocked by the input clock and therefore does not increase relative to six-phase mode.

[0068] Figure 7 is a schematic diagram of an exemplary LO generation circuit 700, showing an AND gate (in Figure 7 Marked as 702, 704, 706, in Figure 6 One implementation is shown in Figure 6 (labeled 616, 618, and 620). Because the signals from the flip-flops are not critical to signal edge switching, the transistors controlled by these signals and connected to the power supply can be made very small, saving chip area and reducing current consumption. Because the same clock signal is used to clock each group of three AND gates, a single n-channel transistor can be shared between all three AND gates. For clarity, the inverters between Out1b, Out2b, and Out3b, and between Out1, Out2, and Out3, are not shown.

[0069] Figure 8 yes Figure 6 and Figure 7 An example timing diagram 800 of the LO generation circuit is shown. The waveforms in three-phase and six-phase modes are identical, except that the input clock frequency in three-phase mode is half that of six-phase mode, when the mixer output frequency is the same. This effectively doubles the frequency in the mixer. In three-phase mode, power is conserved in this circuit and in the clock source circuits that drive it. In some embodiments, in the first mode, the input clock frequency is three times the mixer output frequency; in the second mode, the input clock frequency is 1.5 times the mixer output frequency.

[0070] Figure 9 is Figure 6 and Figure 7 The circuit shown is an exemplary diagram of a mixer 900 driven by a three-phase LO signal or a six-phase LO signal generated by the circuit.

[0071] In one implementation, in mixer 900, each switching transistor 902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, and 924 connects one of the baseband inputs (t) 926, 928, 930, 932, 934, and 936 to the output during the high phase of the LO inputs 938, 940, 942, 944, 946, and 948 that control the switches. This is equivalent to multiplying the baseband waveform un(t) by the effective LO waveform vn(t).

[0072] The baseband waveform can be expressed as:

[0073]

[0074] The effective LO waveform can be expressed as a Fourier series:

[0075]

[0076] Where D is the LO duty cycle, V k It can be expressed as:

[0077]

[0078] For non-overlapping LO waveforms, V k It can be expressed as:

[0079]

[0080] The output waveform of the mixer is given by:

[0081]

[0082] Among them, x k+1 (t) and x k-1 (t) is the time domain representation of the upper and lower sidebands at the kth LO harmonic in the frequency domain.

[0083] In some implementations, second to fifth order sidebands at the first LO harmonic may generate spurious emissions at the antenna. There are three possible mechanisms for generating these sidebands. In one example, assuming a frequency of f BB First, if there is p-order nonlinearity in the baseband signal path, pf will be generated. BB The mixer then directly upconverts the harmonics to f LO ±pf BBSecond, if the mixer generates pf LO –f BB The product under f LO +f BB The p-order intermodulation between the useful signals under the LO –pf BB CIM p Third, if the mixer generates (p+2)f LO +f BB The product under the (p+2) order intermodulation between this product and the useful signal will generate f LO –pf BB The amount of food you eat.

[0084] In some implementations, three-phase and six-phase mixers reject the third harmonic but not the higher-order odd harmonics. The baseband signal is actually present in differential form, meaning N is an even number. In these cases, second-order nonlinearity is not significant, and the primary priority is to suppress the odd harmonics.

[0085] In some implementations, mixer 900 is a six-phase mixer. A six-phase mixer is a minimum even-numbered phase that suppresses the third-order LO and baseband harmonics. With six baseband phases, six LO phases, and a differential output, a "quasi-three-phase" operating mode can also be used, where the output signal is given by the following equation (instead of equation (5)):

[0086]

[0087] This is equivalent to a three-phase mixer running at twice the LO frequency, where each baseband waveform is the difference between the two inverted baseband inputs and each LO waveform is the sum of the two inverted LO inputs, resulting in each LO having two pulses separated by half a cycle.

[0088] The following table summarizes the connections to each mixer transistor, depending on whether operating in three-phase or six-phase mode.

[0089] Table 1

[0090]

[0091] Because each baseband phase has two LO phases in three-phase mode, the two LO phases are effectively combined at the mixer output. As can be seen in the rows labeled LO_0 or LO_180, LO_60 or LO_240, and LO_120 or LO_300, the frequency of the signal is twice the frequency of the original LO signal. This is why the LO signal frequency in three-phase mode can be half the transmit frequency, saving current in the LO generation circuit.

[0092] For three-phase and six-phase modes, LO noise is solely a function of the input clock signal and the output AND gate (not the flip-flop). By using the clock to gate the latch outputs (rather than each other) to generate the LO output, the latch's contribution to LO phase noise is eliminated. This allows the use of smaller transistors in the latch, reducing power consumption. Consequently, the flip-flop can be made much smaller than would otherwise be necessary, reducing the load on the circuit driving the clock signal source. This, in turn, reduces current consumption for a given LO phase noise performance.

[0093] Sharing a single device for the output AND gate also reduces the loading on the input clock line, saving additional current.

[0094] In three-phase mode, the input clock to the LO divider is 1.5 times the mixer output frequency, which reduces current consumption in the input clock source circuitry as well as in all LO generation circuitry.

[0095] In some examples, a typical style of standalone AND gates is used instead of the dedicated set of three AND gates used in one or more of the above-described systems and techniques. In these examples, design complexity can be reduced to some extent, but the load on the input clock line and the latch output can increase, which can result in increased current consumption by the circuitry driving the clock signal into the circuit. In addition, in some such examples, additional chip area can be required.

[0096] Advantageously, in one or more of the systems and techniques described herein, in both three-phase and six-phase modes, the LO phase noise depends only on the input clock noise and the noise of the output AND gate, and not on the latch. In other approaches, the latch noise contributes to the LO phase noise in three-phase mode and, in some implementations, also contributes to the LO phase noise in six-phase mode.

[0097] Furthermore, in one or more of the systems and techniques described herein, by changing which phases of the baseband signal are connected to the mixer switches in a three-phase mode, the LO frequency can be half the mixer output frequency, thereby reducing current consumption in the LO generation circuit. In this case, the mixer doubles the LO frequency, so the mixer output frequency is correct.

[0098] One or more of the systems and techniques described herein can be used in any transmitter that uses three-phase and six-phase modes for 3rd order counter-intermodulation (CIM3) improvement. In addition, the techniques described herein can be applied to other N / 2N phases, such as four-phase / eight-phase.

[0099] Figure 10 As mentioned above Figures 6 to 9Flowchart of an exemplary method 1000 of generating an RF signal in the context of .

[0100] The method may include: performing third-order anti-intermodulation (3-OIM) in, for example, a three-phase mode and a six-phase mode. rd On the transmitter side of the improved CIM3 (order Counter-Intermodulation), a baseband signal generator generates 1002 a plurality of baseband signals that are out of phase with each other.

[0101] The method may further include: a clock signal generator generating 1004 a clock signal having a clock frequency; and a logic gate control signal generator generating 1006 a plurality of control signals. In one embodiment, the plurality of control signals may be out of phase with each other. In another embodiment, the plurality of control signals may be non-overlapping.

[0102] Furthermore, the method may include: each logic gate of the plurality of logic gates generating 1008 a local oscillator signal based on the clock signal and one of the plurality of control signals. The plurality of local oscillator signals generated by the plurality of logic gates may be mixed 1010 with the plurality of baseband signals generated by the baseband generator to generate an output signal. In one embodiment, the plurality of logic gates may include one or more AND gates, one or more NAND gates, or a combination of one or more AND gates or one or more AND gates.

[0103] The method may include controlling 1012 a controller communicatively coupled to the clock signal generator and the mixer to switch the clock signal generator and the mixer between a first mode and a second mode. The controller may include a plurality of flip-flops. In one embodiment, the plurality of flip-flops and the one or more NAND gates form a three-way frequency division circuit. In one embodiment, in the first mode, the controller controls the clock signal generator to set the clock frequency to a value c1 and controls the mixer to mix the plurality of local oscillator signals with a first signal from the plurality of baseband signals. In one embodiment, in the second mode, the controller controls the clock signal generator to set the clock frequency to a value c2 and controls the mixer to mix the plurality of local oscillator signals with a second signal from the plurality of baseband signals. In some embodiments, c2 may be different from c1, and the second signal from the plurality of baseband signals may be different from the first signal from the plurality of baseband signals. In one embodiment, c1 is equal to 2c2. In one embodiment, in the second mode, the clock signal generator is disconnected from the plurality of logic gates, and the inputs of the plurality of logic gates are pulled to a power supply or ground.

[0104] Embodiments of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium (or media) for execution by a data processing apparatus or for controlling the operation of the data processing apparatus. Alternatively or in addition, the program instructions can be encoded on an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiver device for execution by the data processing apparatus. A computer storage medium can be or be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more thereof. Furthermore, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium can also be or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).

[0105] The operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0106] The term "data processing apparatus" includes various devices, equipment, and machines for processing data, including, for example, a programmable processor, a computer, a system on a chip, or a plurality or combination thereof. The apparatus may include dedicated logic circuits, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of these. The apparatus and execution environment may implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0107] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may (but need not) correspond to a file in a file system. A program may be stored in a portion of a file that contains other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program may be deployed for execution on a single computer or on multiple computers located at a single site or distributed across multiple sites and interconnected by a communications network.

[0108] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. These processes and logic flows can also be performed by special-purpose logic circuits (e.g., field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)), and the apparatus can also be implemented as the special-purpose logic circuits shown.

[0109] Processors suitable for executing computer programs include, for example, general-purpose and special-purpose microprocessors. Typically, a processor receives instructions and data from a read-only memory or a random access memory, or both. The essential elements of a computer are a processor for performing actions according to instructions and one or more storage devices for storing instructions and data. Typically, a computer also includes one or more mass storage devices for storing data (e.g., magnetic disks, magneto-optical disks, or optical disks), or is operatively coupled to one or more mass storage devices for storing data to receive data from the mass storage devices and / or send data to the mass storage devices. However, a computer need not include such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name a few examples. Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks. The processor and memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0110] To provide for interaction with a user, embodiments of the subject matter described in this specification may be implemented on a computer having a display device for displaying information to the user, such as a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, and a keyboard and pointing device, such as a mouse or trackball, through which the user can provide input to the computer. Other types of devices may also be used for interaction with the user. For example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and the user's input may be received in any form, including sound, voice, or tactile input. In addition, the computer may interact with the user by sending documents to and receiving documents from a device used by the user; for example, sending a web page to a web browser on a user's client device in response to a request received from the web browser.

[0111] Embodiments of the subject matter described in this specification may be implemented in systems that include a back-end component (e.g., as a data server), or include a middleware component (e.g., an application server), or include a front-end component (e.g., a client computer with a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components). The components of the above-described systems may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks (LANs) and wide area networks (WANs), cross-networks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0112] A computing system may include a client and a server. The client and server are typically remote from each other and typically interact via a communication network. The relationship between the client and the server is generated by computer programs running on their respective computers and having a client-server relationship with each other. In some embodiments, the server transmits data (e.g., an HTML page) to a client device (e.g., to display data to a user interacting with the client device and to receive user input from the user interacting with the client device). Data generated on the client device (e.g., the results of the user interaction) can be received from the client device on the server.

[0113] Although this specification includes many specific implementation details, these details should not be interpreted as limiting the scope of any invention or the scope of what is claimed, but rather as descriptions of features that may be unique to a particular embodiment of a particular invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable subcombination. In addition, although features may be described above as acting in certain combinations, or even initially claimed, in some cases, one or more features in the claimed combination may be removed from that combination, and the claimed combination may be directed to a subcombination or a variant of the subcombination.

[0114] Similarly, although the drawings depict operations in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown, or in sequence, or that all of the operations shown be performed in order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be construed as requiring such separation in all embodiments. It should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0115] In addition, without departing from the scope of the present invention, the techniques, systems, subsystems, and methods described and illustrated as discrete or separate in the various embodiments may be combined or integrated with other systems, modules, techniques, or methods. Other items shown or described as coupled, directly coupled, or communicating with each other may be indirectly coupled or communicating electrically, mechanically, or otherwise through some interface, device, or intermediate component. Other examples of variations, substitutions, and modifications may be determined by those skilled in the art and may be exemplified without departing from the spirit and scope disclosed herein.

[0116] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., through one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element can be directly connected to the other element or indirectly connected to the other element through intermediate elements. When an element is referred to as being directly connected to another element, there are no intermediate elements between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected so that they can transmit electronic signals between them.

[0117] Specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. For example, the operations recited in the claims can be performed in a different order and still achieve desirable results. For example, the processes depicted in the accompanying figures do not necessarily require that they be performed in the particular order shown or in sequential order to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A radio frequency (RF) transmitter, characterized in that: The RF transmitter includes: a baseband signal processor for generating a plurality of baseband signals that are out of phase with each other; A clock signal generator, configured to generate a clock signal having a clock frequency; A logic gate control signal generator for generating a plurality of control signals; a plurality of logic gates, each configured to generate a local oscillator signal according to the clock signal and one of the plurality of control signals; a mixer coupled to the baseband signal processor and the plurality of logic gates, for generating an outgoing radio frequency (RF) signal, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with the plurality of baseband signals respectively to generate the outgoing RF signal; a controller communicatively coupled to the clock signal generator and the mixer, wherein the controller is configured to control the clock signal generator and the mixer to switch between a first mode and a second mode, wherein: In the first mode, the controller is used to control (1) the clock signal generator to set the clock frequency to a value c 1 , and controlling (2) the mixer to mix the plurality of local oscillator signals with the first baseband signal among the plurality of baseband signals respectively; In the second mode, the controller is used to control (1) the clock signal generator to set the clock frequency to a value c 2 , and controlling (2) the mixer to mix the plurality of local oscillator signals with the second baseband signal among the plurality of baseband signals respectively, wherein, c 2 and c 1 Different, the second baseband signal among the multiple baseband signals is different from the first baseband signal among the multiple baseband signals.

2. The RF transmitter according to claim 1, wherein c 1 Equal to 2 c 2 .

3. The RF transmitter according to claim 1 or 2, characterized in that The plurality of control signals are out of phase with each other.

4. The RF transmitter according to claim 1 or 2, characterized in that In the second mode, the clock signal generator is disconnected from the plurality of logic gates, and inputs of the plurality of logic gates are pulled to a power supply or ground.

5. The RF transmitter according to claim 1 or 2, characterized in that The plurality of logic gates include: One or more AND gates; One or more NAND gates; or A combination of one or more AND gates and one or more NAND gates.

6. The RF transmitter according to claim 5, wherein: The logic gate control signal generator includes a plurality of triggers; The multiple flip-flops and the one or more NAND gates constitute a three-way frequency division circuit.

7. The RF transmitter according to claim 1 or 2, characterized in that The plurality of control signals are non-overlapping.

8. The RF transmitter according to claim 1 or 2, characterized in that The local oscillator signal is generated by a single local oscillation (LO) circuit in both the first mode and the second mode; In the first mode, the input clock frequency is three times the output frequency of the mixer; In the second mode, the input clock frequency is 1.5 times the output frequency of the mixer.

9. An RF receiver, characterized in that: The RF receiver comprises: A clock signal generator, configured to generate a clock signal having a clock frequency; A logic gate control signal generator for generating a plurality of control signals; a plurality of logic gates, each configured to generate a local oscillator signal according to the clock signal and one of the plurality of control signals; a mixer coupled to the baseband signal processor and the plurality of logic gates, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with a received RF signal to generate a plurality of down-converted baseband signals; the baseband signal processor configured to generate one or more output signals based on the down-converted baseband signals, wherein the down-converted baseband signals are received from the mixer and are out of phase with each other; a controller communicatively coupled to the clock signal generator and the mixer, wherein the controller is configured to control the clock signal generator and the mixer to switch between a first mode and a second mode, wherein: In the first mode, the controller is configured to control (1) the clock signal generator to set the clock frequency to a value c1, and control (2) the mixer to mix the plurality of local oscillator signals with the received signal respectively; In the second mode, the controller is configured to control (1) the clock signal generator to set the clock frequency to a value c2, and control (2) the mixer to mix the plurality of local oscillator signals with the received signal, respectively, wherein c2 is different from c1.

10. The RF receiver according to claim 9, wherein: c1 equals 2c2.

11. The RF receiver according to claim 9 or 10, characterized in that: The plurality of control signals are out of phase with each other.

12. The RF receiver according to claim 9 or 10, characterized in that In the second mode, the clock signal generator is disconnected from the plurality of logic gates, and inputs of the plurality of logic gates are pulled to a power supply or ground.

13. The RF receiver according to claim 9 or 10, characterized in that The plurality of logic gates include: One or more AND gates; One or more NAND gates; or A combination of one or more AND gates and one or more NAND gates.

14. The RF receiver according to claim 9 or 10, characterized in that The logic gate control signal generator includes a plurality of triggers; The multiple flip-flops and the one or more NAND gates constitute a three-way frequency division circuit.

15. A method for generating an RF signal, characterized in that: The method comprises: The baseband signal processor generates a plurality of baseband signals that are out of phase with each other; The clock signal generator generates a clock signal having a clock frequency; The logic gate control signal generator generates a plurality of control signals; Each logic gate of the plurality of logic gates generates a local oscillator signal based on the clock signal and one of the plurality of control signals; a mixer coupled to the baseband signal processor and the plurality of logic gates to generate an outgoing radio frequency (RF) signal, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with the plurality of baseband signals respectively to generate the outgoing RF signal; A controller communicatively coupled to the clock signal generator and the mixer controls the clock signal generator and the mixer to switch between a first mode and a second mode, wherein: In the first mode, the controller is configured to control (1) the clock signal generator to set the clock frequency to a value c1, and control (2) the mixer to mix the plurality of local oscillator signals with a first baseband signal among the plurality of baseband signals respectively; In the second mode, the controller is used to control (1) the clock signal generator to set the clock frequency to a value c2, and control (2) the mixer to mix the plurality of local oscillator signals with a second baseband signal among the plurality of baseband signals, respectively, wherein c2 is different from c1, and the second baseband signal among the plurality of baseband signals is different from the first baseband signal among the plurality of baseband signals.

16. The method according to claim 15, characterized in that c 1 Equal to 2 c 2 .

17. The method according to claim 15 or 16, characterized in that The plurality of control signals are out of phase with each other.

18. The method according to claim 15 or 16, characterized in that The plurality of control signals are non-overlapping.

19. The method according to claim 15 or 16, characterized in that In the first mode, the input clock frequency is three times the output frequency of the mixer; In the second mode, the input clock frequency is 1.5 times the output frequency of the mixer.

20. A method for generating an output signal based on a received RF signal, characterized in that: The method comprises: The clock signal generator generates a clock signal having a clock frequency; The logic gate control signal generator generates a plurality of control signals; Each logic gate of the plurality of logic gates generates a local oscillator signal based on the clock signal and one of the plurality of control signals; a mixer coupled to the baseband signal processor and the plurality of logic gates to generate a plurality of down-converted baseband signals, wherein the mixer is configured to mix the plurality of local oscillator signals generated by the plurality of logic gates with a received RF signal; A controller communicatively coupled to the clock signal generator and the mixer controls the clock signal generator and the mixer to switch between a first mode and a second mode, wherein: In the first mode, the controller is configured to control (1) the clock signal generator to set the clock frequency to a value c1, and control (2) the mixer to mix the plurality of local oscillator signals with the received signal respectively; In the second mode, the controller is configured to control (1) the clock signal generator to set the clock frequency to a value c2, and control (2) the mixer to mix the plurality of local oscillator signals with the received signal, respectively, wherein c2 is different from c1; The baseband signal processor generates one or more output signals based on the plurality of down-converted baseband signals received from the mixer.

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