Instruction execution method and apparatus, electronic device, and storage medium

Abstract

An instruction execution method, an instruction execution device, an electronic device and a non-transitory computer-readable storage medium. The instruction execution method comprises: reading an instruction, wherein the instruction comprises at least one source operand; decoding the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; based on the operand bit width and the physical register port bit width, performing a register renaming operation to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and based on the register mapping table, executing the instruction to obtain an instruction execution result.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to an instruction execution method, an instruction execution apparatus, an electronic device, and a non-transitory computer-readable storage medium. BACKGROUND

[0002] When defining an instruction, an instruction set specifies the bit width of an operand corresponding to the instruction. When a processor executes the instruction, the bit width of a physical register read-write port can represent the bit width of a data path. Generally, the bit width of the physical register read-write port is the same as the bit width corresponding to an instruction execution unit. When the bit width of the operand corresponding to the instruction is greater than the bit width of the physical register read-write port, the instruction needs to be split into more micro-operations for execution when the instruction is decoded, which reduces the execution efficiency of the instruction and lengthens the clock cycle of the instruction. SUMMARY

[0003] At least one embodiment of the present disclosure provides an instruction execution method, including: reading an instruction, wherein the instruction includes at least one source operand; decoding the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; performing a register renaming operation based on the operand bit width and the physical register port bit width to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction and a plurality of physical registers in a physical register file corresponding to the instruction are associated; and executing the instruction based on the register mapping table to obtain an instruction execution result.

[0004] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the number of the plurality of physical registers associated with the logical register corresponding to each source operand is related to the ratio between the operand bit width and the physical register port bit width.

[0005] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, executing the instruction based on the register mapping table to obtain an instruction execution result includes: determining all physical registers associated with at least one logical register corresponding to at least one source operand based on the register mapping table; and processing all data in all physical registers associated with the at least one logical register to obtain the instruction execution result.

[0006] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the data in all the physical registers associated with the at least one logical register mapping is processed to obtain the instruction execution result, including: reading all the data in all the physical registers associated with the at least one logical register mapping; processing all the data in all the physical registers associated with the at least one logical register mapping to obtain the instruction execution result.

[0007] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the plurality of data in the plurality of physical registers associated with each logical register mapping is read through a plurality of continuous clock cycles respectively.

[0008] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the instruction further includes a destination operand, and in the register mapping table, the logical register corresponding to the destination operand is associated with a plurality of physical registers in the physical register file; the instruction execution method further includes: performing a broadcast wake-up operation on the plurality of physical registers associated with the logical register corresponding to the destination operand to update the state of the plurality of physical registers associated with the logical register corresponding to the destination operand.

[0009] For example, the instruction execution method provided by at least one embodiment of the present disclosure further includes: writing the instruction execution result back to the plurality of physical registers associated with the logical register corresponding to the destination operand.

[0010] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the instruction execution result includes a plurality of sub-results, and writing the instruction execution result back to the plurality of physical registers associated with the logical register corresponding to the destination operand includes: writing the plurality of sub-results into the plurality of physical registers associated with the logical register corresponding to the destination operand one by one through a plurality of clock cycles.

[0011] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the broadcast wake-up operation is executed after reading all the data in all the physical registers associated with the at least one logical register mapping and before processing all the data in all the physical registers associated with the at least one logical register mapping.

[0012] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, before the instruction is executed, the instruction execution method further includes: determining the state of all physical registers in the physical register file; and in response to the state of all physical registers associated with the at least one logical register mapping corresponding to the at least one source operand being the matching state, determining that the state of the instruction is the launchable state.

[0013] For example, the instruction execution method provided by at least one embodiment of the present disclosure further includes: in response to the state of the instruction being the launchable state and the instruction being selected, performing a port conflict judgment on the instruction, and in response to the instruction not having a port conflict, launching the instruction to execute the instruction.

[0014] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the execution of the instruction includes: executing the instruction by using one execution unit corresponding to the instruction through a plurality of clock cycles to obtain the instruction execution result, wherein in each clock cycle, the one execution unit processes data in at least one physical register corresponding to the at least one source operand one by one to obtain a sub-result.

[0015] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the at least one physical register used to store data processed by the one execution unit in the a-th clock cycle of the plurality of clock cycles is different from the at least one physical register used to store data processed by the one execution unit in any clock cycle of the plurality of clock cycles except the a-th clock cycle, where a is a positive integer.

[0016] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the execution of the instruction includes: executing the instruction by using a plurality of execution units corresponding to the instruction through at least one clock cycle to obtain the instruction execution result, wherein in each clock cycle, each execution unit processes data in at least one physical register corresponding to the at least one source operand one by one to obtain a sub-result.

[0017] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the at least one physical register used to store data processed by the b-th execution unit of the plurality of execution units is different from the at least one physical register used to store data processed by any execution unit of the plurality of execution units except the b-th execution unit, where b is a positive integer.

[0018] For example, in the instruction execution method provided by at least one embodiment of the present disclosure, the operand bit width is greater than the physical register port bit width.

[0019] The instruction execution apparatus provided in at least one embodiment of the present disclosure includes: an instruction fetching unit configured to read an instruction, wherein the instruction includes at least one source operand; a decoding unit configured to perform decoding processing on the instruction to determine an operand bit width corresponding to the instruction and determine a physical register port bit width corresponding to the instruction; a renaming unit configured to perform a register renaming operation based on the operand bit width and the physical register port bit width to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and an instruction execution unit configured to execute the instruction based on the register mapping table to obtain an instruction execution result.

[0020] The electronic device provided in at least one embodiment of the present disclosure includes: a memory, which is non-transitory and stores computer executable instructions; and a processor, which is configured to run the computer executable instructions, wherein the computer executable instructions, when run by the processor, implement the instruction execution method according to any embodiment of the present disclosure.

[0021] The non-transitory computer readable storage medium provided in at least one embodiment of the present disclosure stores computer executable instructions, and the computer executable instructions, when executed by a processor, implement the instruction execution method according to any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are merely related to some embodiments of the present disclosure, and not a limitation of the present disclosure.

[0023] Figure 1 The schematic flowchart of the instruction execution method provided in at least one embodiment of the present disclosure is shown in FIG. 1;

[0024] Figure 2 The schematic diagram of the physical register file provided in at least one embodiment of the present disclosure is shown in FIG. 2;

[0025] Figure 3 The overall flowchart of the instruction execution method provided in at least one embodiment of the present disclosure is shown in FIG. 3;

[0026] Figure 4 The schematic block diagram of the instruction execution apparatus provided in at least one embodiment of the present disclosure is shown in FIG. 4;

[0027] Figure 5 The schematic diagram of the electronic device provided in at least one embodiment of the present disclosure is shown in FIG. 5;

[0028] Figure 6 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0030] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0031] In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components.

[0032] The X86 architecture is a computer language instruction set executed by a microprocessor. The X86 instruction set is a CSIC (complex-instruction-set-computer) instruction set. For the X86 instruction set, when the bit width of an operand corresponding to an instruction is greater than the bit width of a physical register port in a computer, the instruction is split into multiple micro-operations (micro-commands) using multiple Microcode instructions, and then the multiple micro-operations are executed respectively. The above-mentioned manner reduces the IPC (instruction per cycle) index, reduces the utilization rate of the scheduling queue (the queue includes multiple instructions processed by decoding), and requires more physical registers due to the splitting of the instruction into multiple micro-operations, resulting in resource waste and low efficiency.

[0033] The instruction execution method comprises the following steps: reading an instruction, wherein the instruction comprises at least one source operand; performing a decoding process on the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; performing a register renaming operation based on the operand bit width and the physical register port bit width to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and performing the instruction based on the register mapping table to obtain an instruction execution result.

[0034] In the instruction execution method provided by the embodiments of the present disclosure, in the case where the operand bit width corresponding to the instruction is greater than the physical register port bit width, the execution of the instruction is realized without splitting the instruction by associating one logical register with a plurality of physical registers and reading data in the plurality of physical registers for processing in a plurality of clock cycles, thereby improving the execution efficiency of the instruction, saving the flow of instruction execution, saving power consumption, improving the IPC index and the utilization rate of the scheduling queue, reducing the use of microcode to realize the instruction, and simultaneously saving the number of physical registers used when executing one instruction.

[0035] The embodiments of the present disclosure also provide an instruction execution device, an electronic device and a non-transitory computer-readable storage medium applied to the above instruction execution method.

[0036] It should be noted that the logical register in the embodiments of the present disclosure can be a register defined by an instruction set architecture (ISA, Instruction Set Architecture), for example, in the X86 instruction set, the logical register can be a 256-bit logical register (i.e., the bit width of the logical register is 256 bits) or a 128-bit logical register (i.e., the bit width of the logical register is 128 bits), and the bit width of the logical register (for example, the above 256 bits or 128 bits, etc., which can also be 32 bits, 64 bits, etc.) can be determined according to actual conditions, and the present disclosure does not limit this. In addition, in the embodiments of the present disclosure, the physical register is a component of the processor, and the physical register can be a register allocated by the processor internally for the logical register.

[0037] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0038] Figure 1 The present disclosure provides an instruction execution method.

[0039] For example, as Figure 1As shown, the instruction execution method provided in this embodiment includes steps S110 to S150.

[0040] The instruction execution method provided by the embodiments of this disclosure can improve and optimize the execution of instructions that need to be split into multiple micro-operations when the operand width is greater than the physical register port width, thereby improving the efficiency of instruction execution and solving the problem of low efficiency when the operand width is greater than the physical register port width.

[0041] like Figure 1 As shown, in step S110, the instruction is read.

[0042] For example, an instruction includes at least one source operand. For example, an instruction can be an instruction from the x86 instruction set.

[0043] For example, instructions can be of various types, such as data transfer instructions, arithmetic and logical operation instructions, and shift operation instructions. For instance, arithmetic and logical operation instructions include arithmetic operation instructions, logical operation instructions, and shift instructions. Arithmetic operation instructions are basic numerical calculation instructions that a computer can execute, including addition instructions (add), subtraction instructions (sub), multiplication instructions (mul), and division instructions (div). Logical operation instructions are instructions that perform logical operations on data, including the three basic logical operation instructions (and), logical OR instructions (or), and logical NOT instructions (not), as well as combined logical operation instructions such as XNOR instructions and XOR instructions. This disclosure does not limit the specific type of instructions.

[0044] For example, an instruction can include one source operand. For instance, the instruction `load a0 a1`; "load" indicates that this is a load instruction, meaning `a0 = a1`, that is, assigning `a1` to `a0`. This instruction only includes one source operand, `a1`. An instruction can also include multiple source operands. For instance, the instruction `add a2a3 a4`; "add" indicates that this is an addition instruction, meaning `a2 = a3 + a4`, that is, adding `a3` (the value stored in the physical register corresponding to source operand `a3`) to `a4` (the value stored in the physical register corresponding to source operand `a4`) and assigning the result of the addition operation to `a2`. This instruction can include two source operands, `a3` and `a4`.

[0045] It should be noted that the instructions can also be instructions from other instruction sets, and the embodiments disclosed herein do not impose any restrictions on this.

[0046] For example, each source operand corresponds to a logical register, and the value of the source operand is stored in one or more physical registers corresponding to that logical register. When an instruction is executed, data is read from the physical registers corresponding to each source operand of the instruction and the relevant operations are performed.

[0047] For example, the instruction also includes a destination operand, and the result of the instruction execution is written into the physical register corresponding to the logical register corresponding to the destination operand.

[0048] For example, the instruction: load a0 a1; the destination operand of this instruction is a0, and the result of the instruction is to retrieve the value stored in the physical register corresponding to the logical register corresponding to the source operand a1, and then write the value stored in the physical register corresponding to the logical register corresponding to the destination operand a0 into the physical register corresponding to the logical register corresponding to the destination operand a0.

[0049] For example, for the instruction: add a2 a3 a4; the destination operand is a2, and the result of the instruction is the sum of the value stored in the physical register corresponding to the logical register corresponding to the source operand a3 and the value stored in the physical register corresponding to the logical register corresponding to the source operand a4. Then, this sum is written into the physical register corresponding to the logical register corresponding to the destination operand a2.

[0050] like Figure 1 As shown, in step S120, the instruction is decoded to determine the bit width of the operands corresponding to the instruction.

[0051] For example, in step S120, the instruction can be decoded to determine at least one source operand of the instruction, and then the operand bit width can be determined based on the at least one source operand.

[0052] For example, in an instruction, all operands (including source and destination operands) have the same bit width.

[0053] For example, the operand bit width can be the bit width of each source operand. For example, in some embodiments, the operand bit width can be 64 bits, 128 bits, 256 bits, etc.

[0054] like Figure 1 As shown, in step S130, the bit width of the physical register port corresponding to the instruction is determined.

[0055] For example, the physical register port width represents the bit width of the data port corresponding to the physical register, that is, the amount of data that the data port can transmit each time. The physical register port width can be determined according to the actual situation. For example, the physical register port width can be 128 bits. It should be noted that once the processor architecture is designed, the physical register port width is fixed and remains unchanged during instruction execution.

[0056] For example, the bit width of the physical register port can be the same as the bit width of the execution unit used to execute the instruction. During instruction execution, the data path includes data passing through components (e.g., execution unit, signal lines, etc.), and the bit width of the execution unit can be the bit width of the data path.

[0057] Figure 2 A schematic diagram of a physical register file provided for at least one embodiment of this disclosure.

[0058] For example, in some embodiments, the processor includes multiple physical register files, such as floating-point physical register files, integer physical register files, etc., each physical register file including multiple physical registers. Figure 2 As shown, the physical register file can include multiple physical registers, such as p1 to p6, etc. For example, in some examples, Figure 2 Each physical register in the physical register file shown can store up to 128 bits of data, meaning the physical register port width is 128 bits.

[0059] If the instruction represents an operation between floating-point data, the data of the source operand of the instruction is stored in the floating-point physical register file. In this case, the port width of the physical register corresponding to the instruction can be the port width of the physical register in the floating-point physical register file. If the instruction represents an operation between integer data, the data of the source operand of the instruction is stored in the integer physical register file. In this case, the port width of the physical register corresponding to the instruction can be the port width of the physical register in the integer physical register file.

[0060] For example, each physical register in the physical register file has a label for easy lookup.

[0061] like Figure 1 As shown, in step S140, a register renaming operation is performed based on the operand bit width and the physical register port bit width to determine the register mapping table.

[0062] For example, a register map is used to represent the mapping relationship between logical registers and physical registers. In the register map, the logical register corresponding to each source operand of an instruction is mapped to multiple physical registers in the physical register file corresponding to the instruction, and the logical register corresponding to the destination operand of an instruction is mapped to multiple physical registers in the physical register file. In other words, the logical register corresponding to each operand (source operand / destination operand) corresponds to multiple physical registers.

[0063] For example, instructions in a processor are usually executed in parallel and in out-of-order order. So it is possible that while one instruction is reading a physical register, another instruction is writing to the same physical register. To avoid data conflicts and improve the processor's instruction-level parallelism, the processor usually assigns different physical registers to different instructions during the register renaming phase of instruction execution. The processor can obtain the physical registers allocated to each instruction through the register mapping table.

[0064] For example, the operand bit width is greater than the physical register port bit width. For example, in some embodiments, the operand bit width can be twice the physical register port bit width, such as 256 bits for the operand bit width and 128 bits for the physical register port bit width. This disclosure is not limited thereto, and the operand bit width can be many times the physical register port bit width (e.g., three times, four times, etc.).

[0065] For example, in step S140, firstly, based on the operand bit width and the physical register port bit width, the number of physical registers corresponding to each logical register can be determined. Then, when performing a register renaming operation, physical registers can be allocated to each logical register based on the determined number, thereby determining the register mapping table. It should be noted that the register mapping table can be represented in tabular form or in other suitable form, and the embodiments of this disclosure do not limit this.

[0066] For example, the number of physical registers associated with the logical register mapping corresponding to each source operand is related to the ratio between the operand bit width and the physical register port bit width. For example, in some embodiments, the number of physical registers associated with the logical register mapping corresponding to each source operand is equal to the ratio between the operand bit width and the physical register port bit width (i.e., operand bit width / physical register port bit width). For example, in some embodiments, the operand bit width is 256 bits and the physical register port bit width is 128 bits. In this case, the logical register corresponding to each source operand of the instruction is associated with two physical register mappings.

[0067] For example, a register renaming operation can include reading a source register and allocating a destination register. Reading a source register establishes a mapping between the logical registers and physical registers corresponding to each source operand in the instruction, while allocating a destination register establishes a mapping between the logical registers and physical registers corresponding to the destination operand in the instruction.

[0068] like Figure 1 As shown, in step S150, instructions are executed based on the register mapping table to obtain the instruction execution result.

[0069] For example, in some embodiments, step S150 can include determining, based on the register mapping table, all physical registers associated with the at least one logical register mapping corresponding to the at least one source operand respectively; and processing all data in all physical registers associated with the at least one logical register mapping to obtain the instruction execution result.

[0070] For example, in some embodiments, processing data in all physical registers associated with the at least one logical register mapping to obtain the instruction execution result includes reading all data in all physical registers associated with the at least one logical register mapping; and processing all data in all physical registers associated with the at least one logical register mapping to obtain the instruction execution result.

[0071] For example, in some embodiments, the instruction can be an addition instruction and is represented as: add a2 a3 a4, where the instruction includes one destination operand and two source operands, the destination operand is a2, and the two source operands are source operand a3 and source operand a4 respectively. In some embodiments, the physical register file corresponding to the instruction can be as shown in the following table: Figure 2 Based on the register mapping table, all physical registers corresponding to source operand a3 and source operand a4 can be determined, for example, the physical register associated with the logical register mapping corresponding to source operand a3 can be physical register p1 and physical register p2 as shown in the following table: Figure 2 The physical register associated with the logical register mapping corresponding to source operand a4 can be physical register p3 and physical register p4 as shown in the following table: Figure 2 Then, data in all physical registers corresponding to source operand a3 and source operand a4 is read, that is, data in physical register p1 to physical register p4 is read, and the read data is processed (for example, addition) accordingly to obtain the instruction execution result.

[0072] For example, the plurality of data in the plurality of physical registers associated with each logical register mapping is read through a plurality of time-continuous clock cycles respectively, that is, in a clock cycle, for one source operand, data is read only from one physical register corresponding to the source operand.

[0073] It should be noted that in the embodiments of the present disclosure, the plurality of time-continuous clock cycles means that in time, the plurality of clock cycles are continuous and uninterrupted.

[0074] For example, each of the operands corresponds to one data transfer port to implement data read and write. For example, when the instruction includes multiple source operands, the multiple source operands correspond to multiple data transfer ports respectively, and the data corresponding to the multiple source operands can be read simultaneously. For example, in some examples, the multiple source operands include a first source operand and a second source operand, and the data in one physical register corresponding to the first source operand and the data in one physical register corresponding to the second source operand can be read simultaneously in the same clock cycle, i.e., in one clock cycle, the data in the physical register corresponding to the first source operand is read, and at the same time, the data in the physical register corresponding to the second source operand is also read. For example, for the instruction: add a2 a3 a4, the physical register corresponding to the logical register mapping associated with the source operand a3 can be the physical register p1 and the physical register p2 as shown in the following figure, and the physical register corresponding to the logical register mapping associated with the source operand a4 can be the physical register p3 and the physical register p4 as shown in the following figure, and at this time, the data corresponding to the source operand a3 and the data corresponding to the source operand a4 can be read through two clock cycles, for example, in the first clock cycle, the data in the physical register p1 and the data in the physical register p3 are read, and in the second clock cycle, the data in the physical register p2 and the data in the physical register p4 are read. Figure 2 Figure 2

[0075] For example, in some embodiments, the method of instruction execution further includes performing a broadcast wake-up operation on the multiple physical registers associated with the logical register mapping corresponding to the destination operand to update the state of the multiple physical registers associated with the logical register mapping corresponding to the destination operand.

[0076] For example, the broadcast wake-up operation can be performed after reading all the data in all the physical registers associated with the at least one logical register mapping and before processing all the data in all the physical registers associated with the at least one logical register mapping.

[0077] For example, the broadcast wake-up operation means that the logical register corresponding to the destination operand of the instruction is issued to the issue queue (the issue queue can also be called the reservation station), and the instruction in the issue queue that uses the same logical register as the source operand can be executed, i.e., the destination operand of the instruction is broadcasted to match the source operand of the instruction in the issue queue.

[0078] ​​For example, the broadcast wake-up operation on the plurality of physical registers associated with the logical register mapped to the destination operand is performed through a plurality of clock cycles respectively, i.e., the broadcast wake-up operation on each of the physical registers associated with the logical register mapped to the destination operand can be performed in one clock cycle. For example, the plurality of clock cycles can be a plurality of clock cycles that are continuous in time.

[0079] For example, for the case of instruction out-of-order execution, after the instruction is decoded, the decoded instruction is not directly sent to the pipeline, but is sent to the corresponding reservation station according to the type of the instruction and is saved in the reservation station. If the data corresponding to the operand of the instruction is located in a physical register, the data corresponding to the operand of the instruction is read out from the physical register and is placed in the reservation station together with the instruction. Conversely, if some of the operands of the instruction are still being calculated by the remaining instructions, the identification information of the instruction is saved. Then, the reservation station sends the instructions with complete operands to the pipeline in sequence for operation. If the data corresponding to the operand of the instruction is not ready, the instruction cannot start execution, so the execution order of the instructions in the reservation station is inconsistent with the program (out-of-order). In addition, the reservation station monitors the results output by the execution pipeline, and if the generated result is exactly the operand of the instruction waiting, it is read in, so that the waiting instruction can be executed after the operand is complete. Whether the data corresponding to the operand of the instruction is in a ready state can be determined according to the state of the physical register storing the data.

[0080] For example, in some embodiments, before the instruction is executed, the instruction execution method further includes a dispatch calculation process of the instruction, and the dispatch calculation process includes: determining the state of all physical registers in the physical register file; and in response to the state of all physical registers associated with at least one logical register mapped to at least one source operand respectively being in a matching state, determining that the state of the instruction is in an issuable state.

[0081] For example, the state of the physical register being in the matching state indicates that the data in the physical register is in a ready state, i.e., the data in the physical register can be read out for processing.

[0082] For example, the dispatch calculation process can solve the problem of the dependency between instructions. In the dispatch calculation process, the dispatch queue can accept the tag broadcasted from the physical register, update the state of the instruction in the dispatch queue, when the state of all physical registers corresponding to the source operand of the instruction changes to the matching state, the state of the instruction can be updated to a dispatchable execution state (i.e., an issuable state), and then, whether the instruction can be selected and issued for execution is determined by the priority.

[0083] For example, in some embodiments, the method of executing instructions further comprises: in response to the state of the instruction being the launchable state and the instruction being selected, performing a port conflict judgment on the instruction, and in response to the instruction not having a port conflict, launching the instruction to execute the instruction.

[0084] For example, the number of clock cycles corresponding to the execution process of each instruction is different, so that a port (data write back port) conflict can be generated, and therefore, when the instruction is selected for execution, a port conflict judgment can be performed on the instruction to avoid a port conflict with an instruction being executed. For example, for two instructions, instruction 1 and instruction 2, the execution of instruction 1 requires 3 clock cycles, the execution of instruction 2 requires 1 clock cycle, instruction 1 is scheduled to be executed in clock cycle 1, and the execution process of this instruction 1 requires 3 clock cycles (i.e., consecutive clock cycle 1, clock cycle 2, and clock cycle 3), then in clock cycle 4 (the next adjacent clock cycle of clock cycle 3), the execution result of this instruction 1 needs to be written into the corresponding physical register through the data write back port, and if in clock cycle 3, instruction 2 is selected for launching to execute, then in clock cycle 4, the execution result of instruction 2 also needs to be written into the corresponding physical register through the data write back port, so that instruction 1 and instruction 2 have a port conflict, and therefore, in order to avoid the port conflict, instruction 2 needs to wait until instruction 2 does not have a port conflict, and then instruction 2 can be launched to execute.

[0085] For example, in some embodiments, the method of executing instructions further comprises: writing back the execution result of the instruction into a plurality of physical registers associated with the logical register mapping corresponding to the destination operand.

[0086] For example, in some embodiments, the execution result of the instruction includes a plurality of sub-results, and writing back the execution result of the instruction into a plurality of physical registers associated with the logical register mapping corresponding to the destination operand comprises: writing back the plurality of sub-results into the plurality of physical registers associated with the logical register mapping corresponding to the destination operand one by one through a plurality of clock cycles. Here, the plurality of clock cycles can be a plurality of clock cycles that are consecutive in time. For example, the number of sub-results is the same as the number of clock cycles, i.e., one sub-result is written back in each clock cycle.

[0087] For example, for the instruction: add a2 a3 a4, the physical registers associated with the logical register mapping corresponding to the destination operand a2 can be physical register p5 and physical register p6 as shown in the figure, and the execution result of the instruction can include two sub-results, which are written back to physical register p5 and physical register p6 in two clock cycles, respectively. Figure 2

[0088] ​For example, in embodiments of the present disclosure, each instruction can be executed by one execution unit or by multiple execution units.

[0089] For example, for the instruction: add a2 a3 a4, the operand bit width of each source operand (a3 or a4) can be 256 bits, each source operand includes two parts, the bit width of each part is 128 bits, for example, each source operand is represented as 0-255 bits, the two parts are a first part and a second part, the first part is the high 128 bits (i.e. 128-255 bits), and the second part is the low 128 bits (i.e. 0-127 bits). The physical register p1 corresponding to the source operand a3 stores the data corresponding to the first part of the source operand a3, the physical register p2 corresponding to the source operand a3 stores the data corresponding to the second part of the source operand a3, similarly, the physical register p3 corresponding to the source operand a4 stores the data corresponding to the first part of the source operand a4, and the physical register p4 corresponding to the source operand a4 stores the data corresponding to the second part of the source operand a4. For example, the add instruction represents adding the first part of the source operand a3 and the first part of the source operand a4, and simultaneously adding the second part of the source operand a3 and the second part of the source operand a4.

[0090] For example, in some embodiments, executing the instruction includes executing the instruction by one execution unit corresponding to the instruction through a plurality of clock cycles to obtain an execution result of the instruction. For example, the plurality of clock cycles can be a plurality of clock cycles that are continuous in time.

[0091] For example, in each clock cycle, one execution unit processes the data in at least one physical register corresponding to at least one source operand to obtain a sub-result.

[0092] For example, at least one physical register used to store the data processed by one execution unit in the a-th clock cycle of a plurality of clock cycles is different from at least one physical register used to store the data processed by one execution unit in any clock cycle of the plurality of clock cycles except the a-th clock cycle, where a is a positive integer.

[0093] For example, for the instruction: add a2 a3 a4, the instruction can be executed by one execution unit in two consecutive clock cycles, for example, in the first clock cycle of the two clock cycles, the execution unit processes data corresponding to the first part of source operand a3 and data corresponding to the first part of source operand a4, i.e., the execution unit processes data stored in physical register p1 and data stored in physical register p3 to obtain a first sub-result; in the second clock cycle of the two clock cycles, the execution unit processes data corresponding to the second part of source operand a3 and data corresponding to the second part of source operand a4, i.e., the execution unit processes data stored in physical register p2 and data stored in physical register p4 to obtain a second sub-result. The instruction execution result of the instruction includes the first sub-result and the second sub-result.

[0094] For example, in some embodiments, executing the instruction includes executing the instruction by the plurality of execution units corresponding to the instruction through at least one clock cycle to obtain the instruction execution result.

[0095] For example, in each clock cycle, each execution unit processes data in at least one physical register corresponding to at least one source operand to obtain a sub-result.

[0096] For example, at least one physical register used to store data processed by a bth execution unit in the plurality of execution units is different from at least one physical register used to store data processed by any execution unit in the plurality of execution units except the bth execution unit, where b is a positive integer.

[0097] For example, for the instruction: add a2 a3 a4, the instruction can be executed by two execution units in one clock cycle, for example, a first execution unit of the two execution units can process data corresponding to the first part of source operand a3 and data corresponding to the first part of source operand a4, i.e., the first execution unit processes data stored in physical register p1 and data stored in physical register p3 to obtain a first sub-result, and a second execution unit of the two execution units can process data corresponding to the second part of source operand a3 and data corresponding to the second part of source operand a4, i.e., the second execution unit processes data stored in physical register p2 and data stored in physical register p4 to obtain a second sub-result. The instruction execution result of the instruction includes the first sub-result and the second sub-result.

[0098] For example, for the instruction `add b1 b2 b3`, the operand width can be four times the width of the physical register port corresponding to the instruction. In this case, each source operand includes four parts: a first part, a second part, a third part, and a fourth part. This instruction can be executed by two execution units in two clock cycles. For example, in the first clock cycle, the first execution unit can process the data corresponding to the first part of source operand b2 and the first part of source operand b3 to obtain the first sub-result. At the same time, the second execution unit can process the data corresponding to the second part of source operand b2 and the second part of source operand b3 to obtain the second sub-result. In the second clock cycle, the first execution unit can process the data corresponding to the third part of source operand b2 and the third part of source operand b3 to obtain the third sub-result. At the same time, the second execution unit can process the data corresponding to the fourth part of source operand b2 and the fourth part of source operand b3 to obtain the fourth sub-result.

[0099] For example, when an instruction is executed by multiple execution units, since each execution unit has a corresponding data transmission port, the data that multiple execution units need to process can be read simultaneously, thereby reducing the clock cycle for reading data. For example, for the instruction: add a2 a3 a4, this instruction can be executed by two execution units. In this case, all the data in physical registers p1 to p4 can be read simultaneously in one clock cycle. For example, the first execution unit reads the data stored in physical register p1 and physical register p3, and the second execution unit reads the data stored in physical register p2 and physical register p4.

[0100] Figure 3 A flowchart illustrating an instruction execution method provided in at least one embodiment of this disclosure.

[0101] like Figure 3 As shown, in some embodiments, the execution process of the instructions may include steps S301 to S309.

[0102] In step S301, the instruction is read, which is the process of fetching an instruction from main memory into the instruction register.

[0103] In step S302, instruction decoding is performed, i.e., the instruction is decoded. In step S302, the instruction decoder breaks down and interprets the retrieved instruction according to a predetermined instruction format, identifies the instruction, and obtains information such as the operands and operand bit width.

[0104] In step S303, register renaming, i.e. assigning physical registers to the logical registers corresponding to the operands of the instruction, is performed to achieve the mapping between logical registers and physical registers, and to obtain a register mapping table. If the instruction is determined to be a specific instruction in the instruction decoding stage, i.e. the bit width of the operand corresponding to the instruction is greater than the bit width of the physical register port, in the register mapping table corresponding to the instruction, each logical register corresponds to multiple (e.g. two, three, four, etc.) physical registers.

[0105] It should be noted that if the bit width of the operand corresponding to the instruction is less than or equal to the bit width of the physical register port, in the register mapping table corresponding to the instruction, each logical register corresponds to one physical register.

[0106] In step S304, scheduling calculation. In step S304, the scheduling calculation process can solve the problem of the dependency between instructions, for example, the scheduling queue can accept the tag broadcast from the physical register, update the state of the instruction in the scheduling queue, when the state of all physical registers corresponding to the source operand of the instruction becomes the matching state, the state of the instruction can be updated to the schedulable execution state, and then, the priority is selected to determine whether the instruction can be selected and transmitted for execution.

[0107] In step S305, port conflict judgment. When the instruction is selected to be transmitted for execution, the port conflict (Block) judgment needs to be performed to avoid the conflict of the write back port and prevent the program from being incorrect. For example, the number of clock cycles of the instruction selected to be executed is calculated, and the instruction that needs to be stopped and cannot be selected for execution due to the write back port conflict is calculated. When the instruction selected to be executed is the instruction that needs to be stopped and cannot be selected for execution, it indicates that the instruction selected to be executed has port conflict, so that the instruction selected to be executed is temporarily not executed until the instruction selected to be executed does not have port conflict.

[0108] When it is determined in step S305 that the selected instruction does not have port conflict, step S306 is performed to read data. That is, data is read from all physical registers corresponding to the source operand of the instruction, for example, for the above instruction: add a2a3 a4, data is read from physical register p1 to physical register p4 through two clock cycles in time sequence.

[0109] For example, when reading data, it is necessary to determine the number of physical registers corresponding to each logical register, that is, to determine the number of times data needs to be read from the physical registers. When it is determined that each logical register corresponds to multiple physical registers, it is determined that data needs to be read from the physical registers in the physical register file multiple times, and data is read from these multiple physical registers in multiple consecutive clock cycles; when it is determined that each logical register corresponds to one physical register, it is determined that data only needs to be read from the physical registers in the physical register file once, and data is read from this single physical register in one clock cycle.

[0110] After the data is read, step S307 is executed to process the data and generate the instruction execution result.

[0111] When the instruction is executed and a result is generated, step S308 is executed to write back the instruction execution result. For example, when the bit width of the instruction execution result is greater than the bit width of the write-back path, multiple clock cycles are needed to write back the instruction execution result. For example, for the above instruction: add a2 a3 a4, the instruction execution result can be written back in two consecutive clock cycles.

[0112] It should be noted that in step S308, the instruction execution result is written back to a certain storage format. For example, the instruction execution result is often written to the internal physical register of the central processing unit (CPU) so that it can be quickly accessed by subsequent instructions. In some cases, the instruction execution result can also be written to the relatively slower but cheaper and larger main memory.

[0113] like Figure 3 As shown, after step S306, step S309, the broadcast wake-up operation, can also be executed. Since the logical register corresponding to the destination operand is mapped to multiple physical registers, it is necessary to perform the broadcast wake-up operation on the multiple physical registers mapped to the logical register corresponding to the destination operand through multiple clock cycles.

[0114] At least one embodiment of this disclosure also provides an instruction execution device.

[0115] Figure 4 This is a schematic block diagram of an instruction execution apparatus provided for at least one embodiment of the present disclosure.

[0116] For example, such as Figure 4 As shown, the instruction execution device 400 includes an instruction fetch unit 401, a decoding unit 402, a renaming unit 403, and an instruction execution unit 404.

[0117] The instruction fetch unit 401 is configured to read instructions. For example, the instructions include at least one source operand. The instruction fetch unit 401 is configured to implement Figure 1 As shown in step S110, the specific operations performed by the instruction fetch unit 401 can be referred to the description above for step S110, and will not be repeated here.

[0118] The decode unit 402 is configured to decode the instructions to determine the operand bit width of the instructions; and determine the physical register port bit width corresponding to the instructions. The decode unit 402 is configured to implement Figure 1 As shown in steps S120 and S130, the specific operations performed by the decode unit 402 can be referred to the description above for steps S120 and S130, and will not be repeated here.

[0119] The renaming unit 403 is configured to perform register renaming operation based on the operand bit width and the physical register port bit width, to determine a register mapping table. For example, in the register mapping table, each source operand of the instructions is associated with a logical register and a plurality of physical registers in the physical register file corresponding to the instructions. The renaming unit 403 is configured to implement Figure 1 As shown in step S140, the specific operations performed by the renaming unit 403 can be referred to the description above for step S140, and will not be repeated here.

[0120] The instruction execution unit 404 is configured to execute the instructions based on the register mapping table, to obtain an instruction execution result. The instruction execution unit 404 is configured to implement Figure 1 As shown in step S150, the specific operations performed by the instruction execution unit 404 can be referred to the description above for step S150, and will not be repeated here.

[0121] For example, in some embodiments, the instruction fetch unit 401, the decode unit 402, the renaming unit 403 and / or the instruction execution unit 404 can be implemented by hardware, software, firmware and combinations thereof.

[0122] For example, in some embodiments, the instruction fetch unit 401, the decode unit 402, the rename unit 403, and / or the instruction execution unit 404 can include code and programs stored in a memory; the processor can execute the code and programs to implement some or all of the functions of the instruction fetch unit 401, the decode unit 402, the rename unit 403, and / or the instruction execution unit 404 as described above. For example, the instruction fetch unit 401, the decode unit 402, the rename unit 403, and / or the instruction execution unit 404 can be a special-purpose hardware device to implement some or all of the functions of the instruction fetch unit 401, the decode unit 402, the rename unit 403, and / or the instruction execution unit 404 as described above. For example, the instruction fetch unit 401, the decode unit 402, the rename unit 403, and / or the instruction execution unit 404 can be a combination of one or more circuit boards to implement the functions as described above. In embodiments of the present disclosure, the combination of one or more circuit boards can include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memory and executable by the processors.

[0123] For example, the number of physical registers associated with each logical register mapping corresponding to each source operand is related to the ratio between the operand bit width and the physical register port bit width.

[0124] For example, in some embodiments, in performing the operation of executing the instruction based on the register mapping table to obtain the instruction execution result, the instruction execution unit 404 is configured to: determine, based on the register mapping table, all physical registers associated with at least one logical register mapping corresponding to at least one source operand, respectively; and process all data in all physical registers associated with at least one logical register mapping to obtain the instruction execution result.

[0125] For example, in performing the operation of processing data in all physical registers associated with at least one logical register mapping to obtain the instruction execution result, the instruction execution unit 404 is configured to: read all data in all physical registers associated with at least one logical register mapping; and process all data in all physical registers associated with at least one logical register mapping to obtain the instruction execution result.

[0126] For example, the instruction execution unit 404 is configured to read multiple data in multiple physical registers associated with each logical register mapping through multiple consecutive clock cycles, i.e., reading data from one physical register in one clock cycle.

[0127] For example, the instruction further includes a destination operand, and the logical register corresponding to the destination operand is mapped to a plurality of physical registers in the physical register file. The instruction execution apparatus 400 can further include a broadcast wake-up unit configured to perform a broadcast wake-up operation on the plurality of physical registers mapped to the logical register corresponding to the destination operand to update the state of the plurality of physical registers mapped to the logical register corresponding to the destination operand.

[0128] For example, the instruction execution apparatus 400 can further include a write-back unit configured to write back the instruction execution result to the plurality of physical registers mapped to the logical register corresponding to the destination operand.

[0129] For example, the instruction execution result includes a plurality of sub-results, and the write-back unit is configured to write the plurality of sub-results into the plurality of physical registers mapped to the logical register corresponding to the destination operand one by one through a plurality of clock cycles when performing the step of writing back the instruction execution result to the plurality of physical registers mapped to the logical register corresponding to the destination operand.

[0130] For example, the broadcast wake-up operation is performed after reading all data in all physical registers associated with at least one logical register and before processing all data in all physical registers associated with at least one logical register.

[0131] For example, the instruction execution apparatus 400 can further include a scheduling unit configured to determine the state of all physical registers in the physical register file before executing the instruction, and determine that the state of the instruction is a launchable state in response to the state of all physical registers associated with at least one logical register corresponding to at least one source operand being a matching state.

[0132] For example, the instruction execution apparatus 400 can further include a conflict judgment unit configured to perform a port conflict judgment on the instruction in response to the state of the instruction being a launchable state and the instruction being selected, and launch the instruction to execute the instruction in response to the instruction not having a port conflict.

[0133] For example, the instruction execution unit 404 includes one execution unit corresponding to the instruction when performing the operation of executing the instruction, and the execution unit is configured to execute the instruction through a plurality of clock cycles to obtain an instruction execution result. For example, in each clock cycle, one execution unit processes data in at least one physical register corresponding to at least one source operand one by one to obtain one sub-result.

[0134] For example, at least one physical register used to store data processed by an execution unit in an a-th clock cycle of a plurality of clock cycles is different from at least one physical register used to store data processed by the execution unit in any clock cycle of the plurality of clock cycles except the a-th clock cycle, where a is a positive integer.

[0135] For example, in performing the operation of the execution instruction, the instruction execution unit 404 includes a plurality of execution units corresponding to the instruction, which are configured to execute the instruction through at least one clock cycle to obtain an instruction execution result. For example, in each clock cycle, each execution unit processes data in at least one physical register corresponding to at least one source operand to obtain a sub-result.

[0136] For example, at least one physical register used to store data processed by a b-th execution unit of a plurality of execution units is different from at least one physical register used to store data processed by any execution unit of the plurality of execution units except the b-th execution unit, where b is a positive integer.

[0137] For example, the operand bit width is greater than the physical register port bit width.

[0138] It should be noted that the instruction execution apparatus 400 can achieve similar technical effects as the foregoing instruction execution method, and will not be described here.

[0139] The present disclosure at least one embodiment also provides an electronic device, Figure 5 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0140] For example, as Figure 5 shown, the electronic device 500 includes a processor 501 and a memory 502. It should be noted that Figure 5 The components of the electronic device 500 shown are only exemplary and are not limiting, and the electronic device 500 can also have other components according to actual application needs.

[0141] For example, the processor 501 and the memory 502 can realize mutual communication. In some examples, the processor 501 and the memory 502 can communicate through a communication bus 503, or can communicate through a network. For example, the communication bus 503 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 503 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5Only one bus is shown for simplicity, but there can be more buses or more types of buses. The network can include wireless networks, wired networks, or any combination thereof. Embodiments of the present disclosure are not limited in this regard.

[0142] For example, the memory 502 is configured to store computer-executable instructions non-transitorily. The processor 501 is configured to execute the computer-executable instructions. When the computer-executable instructions are run by the processor 501, the instruction execution method according to any of the above embodiments is implemented. For the specific implementation of each step of the instruction execution method and the related explanations, refer to the above embodiments of the instruction execution method, which will not be repeated here.

[0143] For example, other implementation manners of the instruction execution method implemented by the processor 501 executing the computer-executable instructions stored on the memory 502 are the same as the implementation manners mentioned in the above method embodiment part, which will not be repeated here.

[0144] For example, the electronic device 500 can further include a communication interface 504 configured to implement communication between the electronic device 500 and other devices.

[0145] For example, the processor 501 and the memory 502 can be disposed at a server end (or cloud end).

[0146] For example, the processor 501 can control other components in the electronic device 500 to perform desired functions. The processor 501 can be a central processing unit (CPU), a network processing unit (NP), a tensor processing unit (TPU), or a graphics processing unit (GPU), etc., which has data processing ability and / or program execution ability; can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The central processing unit (CPU) can be X86 or ARM architecture, etc.

[0147] For example, the memory 502 can include any combination of one or more computer program products. The computer program product can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. Non-volatile memory, for example, can include read only memory (ROM), hard disk, erasable programmable read only memory (EPROM), compact disc read only memory (CD-ROM), USB memory, flash memory, and / or the like. One or more computer-executable instructions can be stored on the computer-readable storage medium, and the processor 501 can execute the computer-executable instructions to implement various functions of the electronic device 500. Various application programs and various data, and the like can also be stored in the storage medium.

[0148] For example, detailed descriptions about the process in which the electronic device 500 executes the instruction execution method can refer to the related descriptions in the embodiments of the instruction execution method, and repeated descriptions will not be repeated.

[0149] It should be noted that the electronic device 500 can achieve similar technical effects as the foregoing instruction execution method, and will not be repeated here.

[0150] Figure 6 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure is shown. For example, as shown in FIG. 6, one or more computer-executable instructions 601 can be stored non-transiently on the non-transitory computer-readable storage medium 600. For example, when the computer-executable instructions 601 are executed by a processor, one or more steps in the instruction execution method according to any of the above embodiments can be executed. Figure 6

[0151] For example, the non-transitory computer-readable storage medium 600 can be applied in the electronic device 500 described above, for example, the non-transitory computer-readable storage medium 600 can include the memory 502 in the electronic device 500.

[0152] For example, the description of the non-transitory computer-readable storage medium 600 can refer to the description of the memory 502 in the embodiments of the electronic device 500, and repeated descriptions will not be repeated.

[0153] For the present disclosure, the following points also need to be explained:

[0154] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0155] ​(2) For clarity, in the drawings used to describe embodiments of the present application, the thickness and size of layers or structures are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0156] (3) Embodiments of the present disclosure and features in the embodiments can be combined with each other to obtain new embodiments, without conflict.

[0157] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for instruction execution, comprising: reading an instruction, wherein the instruction comprises at least one source operand; decoding the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; performing a register renaming operation based on the operand bit width and the physical register port bit width to determine a register mapping table, wherein in the register mapping table, each source operand of the instruction is associated with a logical register and a plurality of physical registers in a physical register file corresponding to the instruction; and executing the instruction based on the register mapping table to obtain an instruction execution result; wherein the performing the register renaming operation based on the operand bit width and the physical register port bit width comprises: determining a number of the plurality of physical registers associated with each source operand based on a ratio between the operand bit width and the physical register port bit width, and allocating a physical register to each logical register based on the determined number; the executing the instruction based on the register mapping table to obtain the instruction execution result comprises: determining all physical registers associated with at least one logical register corresponding to the at least one source operand based on the register mapping table; and processing all data in all physical registers associated with the at least one logical register to obtain the instruction execution result.

2. The instruction execution method of claim 1, wherein, the processing data in all physical registers associated with the at least one logical register to obtain the instruction execution result comprises: reading all data in all physical registers associated with the at least one logical register; and processing all data in all physical registers associated with the at least one logical register to obtain the instruction execution result.

3. The instruction execution method of claim 2, wherein, the plurality of data in the plurality of physical registers associated with each logical register is read through a plurality of consecutive clock cycles respectively.

4. The instruction execution method of claim 2, wherein, the instruction further comprises a destination operand, wherein in the register mapping table, a logical register corresponding to the destination operand is associated with a plurality of physical registers in the physical register file; the method for instruction execution further comprises: performing a broadcast wake operation on the plurality of physical registers associated with the logical register corresponding to the destination operand to update a state of the plurality of physical registers associated with the logical register corresponding to the destination operand.

5. The method for instruction execution of claim 4, further comprising: writing back the instruction execution result to the plurality of physical registers associated with the logical register corresponding to the destination operand.

6. The instruction execution method of claim 5, wherein, the instruction execution result comprises a plurality of sub-results, the writing back the instruction execution result to the plurality of physical registers associated with the logical register corresponding to the destination operand comprises: writing the plurality of sub-results to the plurality of physical registers associated with the logical register corresponding to the destination operand through a plurality of clock cycles respectively.

7. The instruction execution method of claim 4, wherein, The broadcast wake-up operation is performed after reading all data in all physical registers associated with the at least one logical register mapping and before processing all data in all physical registers associated with the at least one logical register mapping.

8. The instruction execution method of claim 1, wherein, Before executing the instruction, the instruction execution method further includes: determining states of all physical registers in the physical register file; in response to the states of all physical registers associated with the at least one logical register mapping corresponding to the at least one source operand respectively being the matching state, determining that the state of the instruction is the launchable state.

9. The instruction execution method of claim 8, further comprising: in response to the state of the instruction being the launchable state and the instruction being selected, performing a port conflict judgment on the instruction, and in response to the instruction not having a port conflict, launching the instruction to execute the instruction.

10. The instruction execution method of claim 1, wherein, executing the instruction, including: processing, by one execution unit corresponding to the instruction, data in at least one physical register corresponding to each of the at least one source operand in each clock cycle to obtain a sub-result, through a plurality of clock cycles, to obtain an instruction execution result, wherein at least one physical register used to store data processed by the one execution unit in an a-th clock cycle of the plurality of clock cycles is different from at least one physical register used to store data processed by the one execution unit in any clock cycle of the plurality of clock cycles except the a-th clock cycle, where a is a positive integer.

11. The instruction execution method of claim 10, wherein, executing the instruction, including:

12. The instruction execution method of claim 1, wherein, processing, by one execution unit corresponding to the instruction, data in at least one physical register corresponding to each of the at least one source operand in each clock cycle to obtain a sub-result, through a plurality of clock cycles, to obtain an instruction execution result, wherein at least one physical register used to store data processed by the one execution unit in an a-th clock cycle of the plurality of clock cycles is different from at least one physical register used to store data processed by the one execution unit in any clock cycle of the plurality of clock cycles except the a-th clock cycle, where a is a positive integer. The operand bit width is greater than the physical register port bit width.

13. The instruction execution method of claim 12, wherein, 15. An instruction execution apparatus, comprising:

14. The method of claim 1-7, wherein, an instruction fetch unit configured to read an instruction, wherein the instruction includes at least one source operand; a decode unit configured to perform decode processing on the instruction to determine an operand bit width corresponding to the instruction, and determine a physical register port bit width corresponding to the instruction; a rename unit configured to perform a register renaming operation based on the operand bit width and the physical register port bit width to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and an execution unit configured to execute the instruction based on the register mapping table to obtain an instruction execution result. ​ an instruction execution unit configured to execute the instruction based on the register mapping table to obtain an instruction execution result; wherein the executing the register renaming operation based on the operand bit width and the physical register port bit width comprises: determining a number of physical registers associated with a logical register mapping corresponding to each source operand based on a ratio between the operand bit width and the physical register port bit width, and allocating a physical register for each of the logical registers based on the determined number; the executing the instruction based on the register mapping table to obtain an instruction execution result comprises: determining all physical registers associated with at least one logical register mapping corresponding to the at least one source operand based on the register mapping table; processing all data in all physical registers associated with the at least one logical register mapping to obtain the instruction execution result. 16.An electronic device comprising: a memory that stores, non-transitorily, computer-executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the instruction execution method according to any one of claims 1-14.

17. A non-transitory computer-readable storage medium, wherein, the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the instruction execution method according to any one of claims 1-14.

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