Linear feedback shift register and construction method, apparatus, device and medium

Abstract

The application provides a linear feedback shift register and a construction method, device and equipment and a medium, which can be applied to the technical field of registers. The construction method comprises the following steps: determining information of shift chains required by all to-be-supported algorithms, the to-be-supported algorithms being algorithms required to be supported by the linear feedback shift register; and constructing the linear feedback shift register according to the information of the required shift chains. Compared with a static construction method, the construction method provided by the application is more flexible and can implement multiple algorithms. Compared with a dynamic construction method, the linear feedback shift register obtained by the method provided by the application requires less configuration information, so that the cost is smaller.

Description

Technical Field

[0001] This invention relates to the field of registers, and more particularly to a linear feedback shift register and its construction method, apparatus, device, and medium. Background Technology

[0002] Hash algorithms such as SM3 and SHA1 / 2 internally include a message expansion stage. The main operation involves retrieving data from a fixed position in the existing message, performing calculations, appending it to the end of the message, and then performing further calculations based on the appended message. Coarse-grained sequence algorithms such as ZUC and SNOW3G internally include an explicit linear feedback shift register module.

[0003] Existing reconfigurable computing security processors generally employ two approaches to handle such computations. One approach uses memory to store messages and completes the entire message expansion by offsetting read / write pointers; the other uses a dedicated linear feedback shift register module to map the shift chain. The former generates a large number of memory read / write operations and occupies the memory read / write interface, potentially leading to data congestion and ultimately poor performance. The latter requires a large amount of configuration information to map the shift chain. For reconfigurable computing architectures, the more configuration information there is, the more difficult the mapping becomes. Furthermore, a large amount of configuration information consumes significant logic resources, resulting in problems such as excessive chip area. Summary of the Invention

[0004] In view of the above problems, the present invention provides a linear feedback shift register and a method, apparatus, device and medium for constructing it.

[0005] According to a first aspect of the present invention, a method for constructing a linear feedback shift register is provided, comprising:

[0006] Determine the information of all shift chains required by the algorithms to be supported, wherein the algorithms to be supported are those required to be supported by the linear feedback shift register;

[0007] The linear feedback shift register is constructed based on the information of the shift chain to be used.

[0008] In one embodiment of the present invention, the information of the shift chains to be used includes the number of shift chains, the length of each shift chain, and the width of each shift chain.

[0009] In one embodiment of the present invention, constructing the linear feedback shift register based on the information of the shift chain to be used includes:

[0010] Obtain the maximum value of the information of the shift chain to be used, which includes the maximum value of the number of shift chains, the maximum value of the length of the shift chain, and the maximum value of the width of the shift chain;

[0011] Based on the maximum value of the information of the shift chain to be used, construct the hardware structure of the linear feedback shift register;

[0012] Based on the information of the shift chain to be used, the operating mode of the linear feedback shift register is constructed.

[0013] In one embodiment of the present invention, the hardware structure for constructing the linear feedback shift register based on the maximum value of the information of the shift chain to be used includes:

[0014] The maximum number of the shift chains is determined as the number of input ports of the linear feedback shift register;

[0015] The maximum length of the shift chain is determined by the number of shift registers in the linear feedback shift register and the number of output ports of the linear feedback shift register.

[0016] The maximum value of the width of the shift chain is determined as the width of the shift register in the linear feedback shift register.

[0017] In one embodiment of the present invention, the operating mode includes a connection mode, and the operating mode of constructing the linear feedback shift register according to the information of the shift chain to be used includes:

[0018] Obtain all types of shift chains that are required;

[0019] Based on all the types of shift chains required, configure at least one connection mode for the linear feedback shift register, each connection mode supporting the storage of one of the required shift chains;

[0020] The connection mode includes the connection method of the input port of the shift register in the linear feedback shift register and the data connection method between the shift registers.

[0021] In one embodiment of the present invention, the information of the shift chain to be used also includes whether each shift chain supports parallelism and the number of parallel calculations.

[0022] In one embodiment of the present invention, the operating mode includes an acceleration mode, and the step of constructing the operating mode of the linear feedback shift register based on the information of the shift chain to be used includes:

[0023] Get the number of parallel computations for the shift chain that supports parallelism;

[0024] Based on the number of parallel computations of all the said parallel-supporting shift chains, configure at least one acceleration mode of the linear feedback shift register, wherein the linear feedback shift register supports storing one of the said parallel-supporting shift chains in each of the acceleration modes;

[0025] The acceleration mode includes the number of input ports simultaneously supported by the linear feedback shift register and the connection method of the input ports, and the number of parallel calculations is equal to the number of input ports.

[0026] A second aspect of the present invention provides an apparatus for constructing a linear feedback shift register, comprising:

[0027] The determination module is used to determine the information of the shift chains required by all algorithms to be supported, wherein the algorithms to be supported are those required to be supported by the linear feedback shift register;

[0028] A construction module is used to construct the linear feedback shift register based on the information of the shift chain to be used.

[0029] A third aspect of the present invention provides a linear feedback shift register, which is constructed according to the method for constructing a linear feedback shift register described in the first aspect.

[0030] A fourth aspect of the present invention provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the method described above.

[0031] A fifth aspect of the invention also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the methods described above.

[0032] According to the linear feedback shift register and its construction method, apparatus, device, and medium provided by the present invention, information on the shift chains required by all algorithms to be supported is determined. These algorithms are the algorithms that the linear feedback shift register needs to support. Based on this information on the required shift chains, the linear feedback shift register is constructed. Compared to static construction methods, the construction method provided by the present invention is more flexible and can implement multiple algorithms. Compared to dynamic construction methods, the linear feedback shift register obtained by the method provided by the present invention requires less configuration information, resulting in lower overhead. Attached Figure Description

[0033] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0034] Figure 1 A flowchart illustrating a method for constructing a linear feedback shift register according to an embodiment of the present invention is shown schematically.

[0035] Figure 2 A flowchart illustrating a method for constructing a linear feedback shift register according to an embodiment of the present invention is shown schematically.

[0036] Figure 3 This schematically illustrates the data connection diagram of a linear feedback shift register in mode 0 according to an embodiment of the present invention;

[0037] Figure 4 This schematically illustrates the data connection diagram of a linear feedback shift register in mode 1 according to an embodiment of the present invention;

[0038] Figure 5 A flowchart illustrating a method for constructing a linear feedback shift register according to an embodiment of the present invention is shown schematically.

[0039] Figure 6 This schematically illustrates the data connection diagram of a linear feedback shift register in an acceleration mode according to an embodiment of the present invention;

[0040] Figure 7 This schematically illustrates the data connection diagram of a linear feedback shift register in another acceleration mode according to an embodiment of the present invention;

[0041] Figure 8 A schematic block diagram illustrating the construction apparatus of a linear feedback shift register according to an embodiment of the present invention is shown.

[0042] Figure 9 A block diagram of an electronic device suitable for implementing a method of constructing a linear feedback shift register according to an embodiment of the present invention is shown schematically. Detailed Implementation

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of a feature, step, operation, and / or component, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0045] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0046] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0047] In the technical solution of this invention, the collection, storage, use, processing, transmission, provision, disclosure and application of user personal information all comply with the provisions of relevant laws and regulations, necessary confidentiality measures have been taken, and they do not violate public order and good morals.

[0048] Embodiments of the present invention provide a method for constructing a linear feedback shift register, comprising: determining information about all shift chains required by algorithms to be supported, wherein the algorithms to be supported are those required to be supported by the linear feedback shift register; and constructing the linear feedback shift register based on the information about the required shift chains. Compared to static construction methods, the construction method provided by the present invention is more flexible and can implement multiple algorithms. Compared to dynamic construction methods, the linear feedback shift register obtained by the method provided by the present invention requires less configuration information, resulting in lower overhead.

[0049] Figure 1 A flowchart illustrating a method for constructing a linear feedback shift register according to an embodiment of the present invention is shown.

[0050] like Figure 1 As shown, the method for constructing this linear feedback shift register includes operations S110 to S120.

[0051] In operation S110, information about the shift chains required by all algorithms to be supported is determined.

[0052] In operation S120, the linear feedback shift register is constructed based on the information of the shift chain to be used.

[0053] The algorithms to be supported are those required by the linear feedback shift register, which can be set according to actual needs. Examples of algorithms to be supported include one or more of SM3, SHA256, ZUC, and SNOW3G. In one example of this invention, the four algorithms to be supported—SM3, SHA256, ZUC, and SNOW3G—are used as examples to illustrate the invention.

[0054] Determining the shift chains required by all algorithms to be supported can be achieved by first identifying the implementation stages of the algorithms and then obtaining the shift chains required in each implementation stage. For example, for the SM3 and SHA256 algorithms, those skilled in the art typically divide their implementation stages into a message expansion stage and a compression function stage. For the ZUC and SNOW3G algorithms, those skilled in the art typically divide their implementation stages into an initialization stage and an operational stage.

[0055] In one embodiment of the present invention, the information of the shift chains to be used includes the number of shift chains, the length of each shift chain, and the width of each shift chain. For example, for the shift chain information required by the SM3 algorithm, the shift chain required in the message expansion stage is one shift chain with a length of 16 bits and a width of 32 bits. The number of shift chains is 1, the length of the shift chain is 16, and the width of the shift chain is 32. For the above example taking the four algorithms to be supported as SM3, SHA256, ZUC, and SNOW3G, the information of all the shift chains to be used determined by operation S110 is shown in Table 1.

[0056] Table 1

[0057]

[0058] As shown in Table 1, the constructed linear feedback shift register needs to support one shift chain of length 16 and width 32 bits, and also needs to support four shift chains of length 4 and width 32 bits. Understandably, the shift chain of length 16 and width 31 bits required by the ZUC algorithm can be considered as requiring the implementation of one shift chain of length 16 and width 32 bits.

[0059] Figure 2 A flowchart illustrating a method for constructing a linear feedback shift register according to an embodiment of the present invention is shown.

[0060] like Figure 2 As shown, Figure 1 The operation S120 shown describes the construction of the linear feedback shift register based on the information of the shift chain to be used, including operations S210 to S230.

[0061] In operation S210, the maximum value of the information of the shift chain to be used is obtained.

[0062] In operation S220, the hardware structure of the linear feedback shift register is constructed based on the maximum value of the information of the shift chain to be used.

[0063] In operation S230, the operating mode of the linear feedback shift register is constructed based on the information of the shift chain to be used.

[0064] The maximum values ​​for the information required for the shift chain include the maximum number of shift chains, the maximum length of the shift chain, and the maximum width of the shift chain. In the example shown in Table 1, the maximum number of shift chains is 4, the maximum length of the shift chain is 16, and the maximum width of the shift chain is 32.

[0065] In one embodiment of the present invention, during operation S220, constructing the hardware structure of the linear feedback shift register based on the maximum value of the information of the shift chain to be used includes: determining the maximum value of the number of shift chains as the number of input ports of the linear feedback shift register, determining the maximum value of the length of the shift chain as the number of shift registers in the linear feedback shift register and the number of output ports of the linear feedback shift register, and determining the maximum value of the width of the shift chain as the width of the shift registers in the linear feedback shift register.

[0066] In the example shown in Table 1 of this invention, the maximum value of the number of shift chains is determined to be the number of input ports of the linear feedback shift register. Therefore, the linear feedback shift register constructed in the example shown in Table 1 has 4 input ports. The maximum value of the length of the shift chain is determined to be the number of shift registers in the linear feedback shift register and the number of output ports of the linear feedback shift register. Therefore, the linear feedback shift register constructed in the example shown in Table 1 has 16 shift registers and 16 output ports. The maximum value of the width of the shift chain is determined to be the width of the shift registers in the linear feedback shift register. Therefore, the width of the shift registers in the linear feedback shift register constructed in the example shown in Table 1 is 32.

[0067] Understandably, each shift register is configured with one output port. The configuration of the input ports and the data connections between shift registers are reconfigurable depending on the algorithm to be implemented.

[0068] In one embodiment of the present invention, the operating mode includes a connection mode. In operation S230, constructing the operating mode of the linear feedback shift register based on the information of the shift chain to be used includes: obtaining all types of shift chains to be used, and configuring at least one connection mode of the linear feedback shift register based on all types of shift chains to be used.

[0069] Each connection mode supports storing one shift chain to be used. The connection mode includes the input port connection method of the shift register in the linear feedback shift register and the data connection method between shift registers. The input port connection method is related to the number of shift chains to be used. Specifically, each shift chain is configured with one input port. The data connection method between shift registers is that the data between each shift chain is not connected, but the data within each shift chain is connected.

[0070] In this invention, the different types of shift chains are defined by the different information of the shift chains required. In the example shown in Table 1, there are two types of shift chains required: one is a single shift chain with a length of 16 bits and a width of 32 bits, and the other is four shift chains with a length of 4 bits and a width of 32 bits. Therefore, the configured linear feedback shift register has two connection modes, such as mode 0 and mode 1. Mode 0 supports storing one shift chain with a length of 16 bits and a width of 32 bits, while mode 1 supports storing four shift chains with a length of 4 bits and a width of 32 bits.

[0071] Optionally, multiple modes can be switched during the implementation of the same algorithm using a linear feedback shift register, and the data stored in the shift register remains unchanged during mode switching. Understandably, this invention does not impose specific restrictions on the switching method. For example, for the aforementioned modes 0 and 1, a dynamically reconfigurable 1-bit configuration can be used to switch between the two operating modes.

[0072] Figure 3 The schematic diagram illustrates the data connection of a linear feedback shift register in mode 0 according to an embodiment of the present invention.

[0073] Mode 0 can be applied to the message extension phase of the SM3 and SHA256 algorithms, as well as the ZUC and SNOW3G algorithms. The 16 shift registers Reg0-Reg15 of the linear feedback shift register have interconnected data paths.

[0074] Understandably, since mode 0 supports storing one shift chain with a length of 16 bits and a width of 32 bits, and the number of shift chains is one, only one input port needs to be connected. That is, only one of the four input ports needs to be active. Figure 3 The input port in_port0 is selected as Reg0.

[0075] Figure 4 The schematic diagram illustrates the data connection of a linear feedback shift register in mode 1 according to an embodiment of the present invention.

[0076] Mode 1 can be applied to the compression function stage of the SM3 and SHA256 algorithms. Since Mode 1 supports storing four shift chains of length 4 and width 32 bits each, the shift registers in the linear feedback shift register are divided into four groups, each group corresponding to one shift chain of length 4 and width 32 bits, with data interconnected within each group. For example... Figure 4 As shown, data is connected between Reg0 and Reg3, between Reg4 and Reg7, between Reg8 and Reg11, and between Reg12 and Reg15. Figure 4 As shown, each shift register is connected to an input port.

[0077] In one embodiment of the present invention, the information of the shift chain to be used also includes whether each shift chain supports parallelism and the number of parallel computations, as shown in Table 2.

[0078] Table 2

[0079]

[0080]

[0081] As shown in Table 2, the linear feedback shift register needs to support one shift chain of length 16 bits and width 32 bits, and also needs to support four shift chains of length 4 and width 32 bits each. Among them, the shift chain of length 16 bits and width 32 bits needs to support parallel computing to improve algorithm efficiency.

[0082] Figure 5 A flowchart illustrating a method for constructing a linear feedback shift register according to an embodiment of the present invention is shown.

[0083] like Figure 5 As shown, the linear feedback shift register also includes an acceleration mode. Figure 5 The operation S230 shown describes the construction of the operating mode of the linear feedback shift register based on the information of the shift chain to be used, including operations S510 to S520.

[0084] When operating S510, obtain the number of parallel computations of the shift chain that supports parallelism.

[0085] When operating S520, at least one acceleration mode of the linear feedback shift register is configured based on the number of parallel computations of all the parallel-supporting shift chains.

[0086] The linear feedback shift register supports storing one parallel shift chain in each of the acceleration modes. The acceleration mode includes the number of input ports that the linear feedback shift register supports at the same time and the connection method of the input ports. The number of parallel calculations is equal to the number of input ports.

[0087] In the example in Table 2 above, during the message extension phase of the SM3 and SHA256 algorithms, a 16*32 shift chain needs to support two parallel calculations. That is, the linear feedback shift register also needs to include an acceleration mode that supports two parallel calculations. The number of connected input ports is equal to the number of parallel calculations, so the number of connected input ports is 2. Of the 4 input ports constructed, 2 input ports remain valid. Figure 6 This schematically illustrates the data connection diagram of a linear feedback shift register in an acceleration mode according to an embodiment of the present invention, as shown below. Figure 6 In the example shown, the acceleration mode uses ports in_port0 and in_port1 as input ports to form a 16*32 shift chain, supporting a shift width of 2 when both ports are input simultaneously.

[0088] Optionally, in the above example, for the three working modes of Mode 0, Mode 1 and Acceleration Mode, a dynamically reconfigurable 2-bit configuration can be used to switch between these three working modes.

[0089] Optionally, if the algorithm to be supported by the linear feedback shift register needs to use a shift chain that also supports 4 parallel calculations, 8 parallel calculations, etc., more acceleration modes can be set according to actual needs. Figure 7 This schematically illustrates the data connection diagram of a linear feedback shift register in another acceleration mode according to an embodiment of the present invention, such as... Figure 7 As shown, the linear feedback shift register also supports four parallel computations. Correspondingly, a dynamically reconfigurable 2-bit configuration can be used to switch between four operating modes: Mode 0, Mode 1, and two acceleration modes.

[0090] Understandably, the working mode that supports 4 parallel calculations can be used in shift chain data initialization scenarios to speed up the initialization process.

[0091] Optionally, operating mode configuration information can be stored in the valid bits of the port data, thereby selecting a specific operating mode by recognizing the valid bits of the port data.

[0092] Optionally, configuration information equal to the number of input ports can be added to support operating modes that do not require shift storage. For example, four 4-bit configuration bits can be added to indicate which register to write to when port data is valid. By adding configuration information, data caching applications can be supported, enabling use in other scenarios where shift storage is not required.

[0093] Based on the above Figures 1 to 7 In addition to the method described above, this invention also provides an apparatus for constructing a linear feedback shift register. The following will combine... Figure 8 The construction apparatus for this linear feedback shift register is described in detail.

[0094] Figure 8 A schematic block diagram illustrating the construction apparatus of a linear feedback shift register according to an embodiment of the present invention is shown.

[0095] like Figure 8 As shown, the linear feedback shift register construction apparatus 800 of this embodiment includes a determination module 810 and a construction module 820.

[0096] The determining module 810 is used to determine the information of the shift chains required by all algorithms to be supported, which are algorithms required to be supported by the linear feedback shift register. In one embodiment, the determining module 810 can be used to perform the operation S110 described above, which will not be repeated here.

[0097] The construction module 820 is used to construct the linear feedback shift register based on the information of the shift chain to be used. In one embodiment, the construction module 820 can be used to perform the operation S210 described above, which will not be repeated here.

[0098] In one embodiment of the present invention, the information of the shift chains to be used includes the number of shift chains, the length of each shift chain, and the width of each shift chain.

[0099] In one embodiment of the present invention, constructing the linear feedback shift register based on the information of the shift chain to be used includes:

[0100] Obtain the maximum value of the information of the shift chain to be used, which includes the maximum number of shift chains, the maximum length of the shift chain, and the maximum width of the shift chain.

[0101] Based on the maximum value of the information of the shift chain to be used, construct the hardware structure of the linear feedback shift register;

[0102] Based on the information of the shift chain to be used, construct the operating mode of the linear feedback shift register.

[0103] In one embodiment of the present invention, the hardware structure for constructing the linear feedback shift register based on the maximum value of the information of the shift chain to be used includes:

[0104] The maximum number of shift chains is determined as the number of input ports of the linear feedback shift register;

[0105] The maximum length of the shift chain is determined by the number of shift registers in the linear feedback shift register and the number of output ports of the linear feedback shift register;

[0106] The maximum value of the width of the shift chain is determined as the width of the shift register in the linear feedback shift register.

[0107] In one embodiment of the present invention, the operating mode includes a connection mode, wherein the operating mode for constructing the linear feedback shift register based on the information of the shift chain to be used includes:

[0108] Obtain all types of shift chains that need to be used;

[0109] Based on all the types of shift chains that need to be used, configure at least one connection mode for the linear feedback shift register, each connection mode supporting the storage of one type of shift chain that needs to be used;

[0110] The connection mode includes the connection method of the input ports of the shift registers in the linear feedback shift register and the data connection method between the shift registers.

[0111] In one embodiment of the present invention, the information of the shift chain to be used also includes whether each shift chain supports parallelism and the number of parallel computations.

[0112] In one embodiment of the present invention, the operating mode includes an acceleration mode, wherein the operating mode for constructing the linear feedback shift register based on the information of the shift chain to be used includes:

[0113] Get the number of parallel computations for the shift chain that supports parallelism;

[0114] Based on the number of parallel computations of all the parallel-enabled shift chains, configure at least one acceleration mode for the linear feedback shift register, which supports storing one of the parallel-enabled shift chains in each acceleration mode;

[0115] The acceleration mode includes the number of input ports that the linear feedback shift register supports simultaneously and the connection method of the input ports. The number of parallel calculations is equal to the number of input ports.

[0116] According to embodiments of the present invention, taking the determining module 810 and the building module 820 as examples, any plurality of modules in the determining module 810 and the building module 820 can be merged into one module, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of the present invention, at least one of the determining module 810 and the building module 820 can be at least partially implemented as a hardware circuit, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented by any other reasonable means of integrating or packaging the circuit, or implemented by any one of the three implementation methods of software, hardware, and firmware, or by a suitable combination of any of them. Alternatively, at least one of the determining module 810 and the building module 820 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0117] The present invention also provides a linear feedback shift register, according to Figures 1-7 It is constructed using any of the methods shown in the article.

[0118] In one embodiment, the linear feedback shift register is connected to multiple computational cores, at least one of which is used to implement an algorithm to be processed. The linear feedback shift register includes a reconfigurable configuration module, which is used to receive configuration information of the shift chain to be used by the algorithm to be processed, generate a configuration instruction based on the configuration information, and send the configuration instruction to the shift register array in the linear feedback shift register. The shift register array includes multiple shift registers, which are used to store the shift chain in the multiple shift registers according to the configuration instruction. The configuration information of the shift chain includes the number of shift chains, the length of each shift chain, and the width of each shift chain.

[0119] Figure 9 A block diagram of an electronic device suitable for implementing a method of constructing a linear feedback shift register according to an embodiment of the present invention is shown schematically.

[0120] like Figure 9As shown, an electronic device 900 according to an embodiment of the present invention includes a processor 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage portion 908 into a random access memory (RAM) 903. The processor 901 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 901 may also include onboard memory for caching purposes. The processor 901 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0121] RAM 903 stores various programs and data required for the operation of electronic device 900. Processor 901, ROM 902, and RAM 903 are interconnected via bus 904. Processor 901 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 902 and / or RAM 903. It should be noted that the programs may also be stored in one or more memories other than ROM 902 and RAM 903. Processor 901 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0122] According to an embodiment of the present invention, the electronic device 900 may further include an input / output (I / O) interface 905, which is also connected to a bus 904. The electronic device 900 may also include one or more of the following components connected to the I / O interface 905: an input section 906 including a keyboard, mouse, etc.; an output section 907 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN card, modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. A removable medium 911, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 910 as needed so that computer programs read from it can be installed into the storage section 908 as needed.

[0123] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0124] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 902 and / or RAM 903 and / or one or more memories other than ROM 902 and RAM 903 described above.

[0125] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the data processing method provided in the embodiments of the present invention.

[0126] When the computer program is executed by the processor 901, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0127] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 909, and / or installed from a removable medium 911. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0128] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 909, and / or installed from the removable medium 911. When the computer program is executed by the processor 901, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0129] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0130] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0131] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0132] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for constructing a linear feedback shift register, characterized in that, include: Determine the information of all shift chains required by the algorithms to be supported, wherein the algorithms to be supported are those required to be supported by the linear feedback shift register; Based on the information of the shift chains to be used, the linear feedback shift register is constructed. The information of the shift chains to be used includes the number of shift chains, the length of each shift chain, and the width of each shift chain. The step of constructing the linear feedback shift register based on the information of the shift chain to be used includes: Obtain the maximum value of the information of the shift chain to be used, which includes the maximum value of the number of shift chains, the maximum value of the length of the shift chain, and the maximum value of the width of the shift chain; Based on the maximum value of the information of the shift chain to be used, construct the hardware structure of the linear feedback shift register; Based on the information of the shift chain to be used, construct the operating mode of the linear feedback shift register; The operating mode includes a connection mode. The step of constructing the operating mode of the linear feedback shift register based on the information of the shift chain to be used includes: Obtain all types of shift chains to be used; based on all types of shift chains to be used, configure at least one connection mode of the linear feedback shift register, each connection mode supporting the storage of one type of shift chain to be used; wherein, the connection mode includes the input port connection method of the shift register in the linear feedback shift register and the data connection method between shift registers.

2. The method for constructing a linear feedback shift register according to claim 1, characterized in that, The operating mode includes an acceleration mode. The step of constructing the operating mode of the linear feedback shift register based on the information of the shift chain to be used includes: Obtain the number of parallel computations for all parallel shift chains; based on the number of parallel computations for all parallel shift chains, configure at least one acceleration mode for the linear feedback shift register, wherein the linear feedback shift register supports storing one of the parallel shift chains in each acceleration mode; wherein the acceleration mode includes the number of input ports simultaneously supported by the linear feedback shift register and the connection method of the input ports, and the number of parallel computations is equal to the number of input ports.

3. The method for constructing a linear feedback shift register according to claim 2, characterized in that, The hardware structure for constructing the linear feedback shift register based on the maximum value of the information of the shift chain to be used includes: The maximum number of the shift chains is determined as the number of input ports of the linear feedback shift register; The maximum length of the shift chain is determined by the number of shift registers in the linear feedback shift register and the number of output ports of the linear feedback shift register. The maximum value of the width of the shift chain is determined as the width of the shift register in the linear feedback shift register.

4. The method for constructing a linear feedback shift register according to claim 2, characterized in that, The information about the shift chains to be used also includes whether each shift chain supports parallelism and the number of parallel computations.

5. A device for constructing a linear feedback shift register, characterized in that, include: The determination module is used to determine the information of the shift chains required by all algorithms to be supported, wherein the algorithms to be supported are those required to be supported by the linear feedback shift register; A construction module is used to construct the linear feedback shift register based on the information of the shift chains to be used, wherein the information of the shift chains to be used includes the number of shift chains, the length of each shift chain, and the width of each shift chain. The step of constructing the linear feedback shift register based on the information of the shift chain to be used includes: Obtain the maximum value of the information of the shift chain to be used, which includes the maximum value of the number of shift chains, the maximum value of the length of the shift chain, and the maximum value of the width of the shift chain; Based on the maximum value of the information of the shift chain to be used, construct the hardware structure of the linear feedback shift register; Based on the information of the shift chain to be used, construct the operating mode of the linear feedback shift register; The operating mode includes a connection mode. The step of constructing the operating mode of the linear feedback shift register based on the information of the shift chain to be used includes: Obtain all types of shift chains to be used; based on all types of shift chains to be used, configure at least one connection mode of the linear feedback shift register, each connection mode supporting the storage of one type of shift chain to be used; wherein, the connection mode includes the input port connection method of the shift register in the linear feedback shift register and the data connection method between shift registers.

6. A linear feedback shift register, characterized in that, It is constructed using the method described in any one of claims 1 to 4 for constructing a linear feedback shift register.

7. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method according to any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that, It stores executable instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 4.

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