IP functional safety system and method, IP module, SoC chip

Abstract

An IP function safety system and method, an IP module and an SoC chip, comprising: an AXI host and an IP module, the AXI host is configured to be connected with a CPU, and the IP module is configured to be connected with a data storage, the AXI host is configured to encode first data from the CPU by using a first encoding mode and send the first data to the IP module, and is further configured to decode second data from the IP module by using a second decoding mode, and send the second data to the CPU when no error occurs in the decoding; the IP module is configured to decode the first data from the AXI host by using a first decoding mode, and output the first data to the data storage when no error occurs in the decoding; and is further configured to encode second data from the data storage by using a second encoding mode and send the second data to the AXI host. The embodiment of the present disclosure can encode and decode when data is transmitted, thereby ensuring the reliability of data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of automotive electronic chip, in particular to an IP functional safety system and method, an IP module and a SoC chip. BACKGROUND

[0002] Automotive electronic chip is a general term for automotive chips, which is crucial to the safety of vehicle driving. The automotive electronic chip is a SoC chip, and the IP module is the most important component of the SoC chip. The IP module interacts with the AXI master to realize the chip to obtain data transmitted from the data acquisition module and transmit data to the automotive enable module.

[0003] In the related art, the IP module includes an AXI slave and a RAM, and the IP module and the AXI master interact with data in a direct transmission manner. However, this manner cannot guarantee the reliability of data. SUMMARY

[0004] The present application provides an IP functional safety design system and method, which can guarantee the reliability of data transmission between the IP module and the AXI master.

[0005] In one aspect, the present application provides an IP functional safety system, comprising:

[0006] an AXI master and an IP module, wherein the AXI master is configured to be connected with a CPU, and the IP module is configured to be connected with a data storage, and wherein:

[0007] the AXI master is configured to encode first data from the CPU in a first encoding manner, and send the encoded first data to the IP module; and configured to decode second data from the IP module in a second decoding manner corresponding to a second encoding manner, and send the decoded second data to the CPU when no error occurs in the decoding process;

[0008] the IP module is configured to decode the first data from the AXI master in a first decoding manner corresponding to the first encoding manner, and output the decoded first data to the data storage when no error occurs in the decoding process; and configured to encode the second data from the data storage in the second encoding manner, and send the encoded second data to the AXI master.

[0009] In another aspect, the present disclosure provides an IP module. The IP module comprises an AXI slave, a random memory, and the AXI slave and the random memory are configured to be connected with an AXI master and a data memory, respectively, wherein:

[0010] The AXI slave is configured to decode the first data encoded by the AXI master using the first decoding mode, encode the decoded first data using a third encoding mode when no error occurs in the decoding process, and write the encoded first data into the random memory; and decode the second data encoded by the random memory using a fourth decoding mode corresponding to the fourth encoding mode, encode the decoded second data using the second encoding mode when no error occurs in the decoding process, and send the encoded second data to the AXI master.

[0011] The random memory is configured to decode the first data encoded by the AXI slave using a third decoding mode corresponding to the third encoding mode, and output the decoded first data to the data memory when no error occurs in the decoding process; and encode the second data from the data memory using the fourth encoding mode, and send the encoded second data to the AXI slave.

[0012] In yet another aspect, the present disclosure provides a SoC chip comprising the IP module.

[0013] In yet another aspect, the present disclosure provides a service testing method, comprising:

[0014] Compared with the related art, the present disclosure comprises a method of encoding and decoding data transmitted between the AXI master and the IP module during data transmission, thereby ensuring the reliability of data transmission and improving the security of IP function.

[0015] Other features and advantages of the present disclosure will be described in the following description, and some will become apparent from the description, or will be learned through practice of the present disclosure. Other advantages of the present disclosure can be achieved and obtained through the solutions described in the specification and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0017] Figure 1 A structural schematic diagram of an IP function security system provided by an embodiment of the present disclosure;

[0018] Figure 2 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0019] Figure 3 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0020] Figure 4 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0021] Figure 5 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0022] Figure 6 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0023] Figure 7 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0024] Figure 8 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0025] Figure 9 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6;

[0026] Figure 10 Another structure schematic diagram of an IP function safety system provided by an embodiment of the present disclosure is shown in FIG. 6; DETAILED DESCRIPTION

[0027] The present disclosure describes a plurality of embodiments, but the description is exemplary rather than limiting, and it is obvious to those skilled in the art that there can be more embodiments and implementation schemes within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment can be used in combination with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.

[0028] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0029] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0030] This disclosure provides an IP functional safety system, such as Figure 1 As shown, it includes: an AXI host 11 and an IP module 12. The AXI host 11 is configured to be connected to a CPU (not shown in the figure), and the IP module 12 is configured to be connected to a data storage device (not shown in the figure), wherein:

[0031] The AXI host 11 is configured to encode first data from the CPU using a first encoding method and send the encoded first data to the IP module 12; it is also configured to decode the second data encoded from the IP module 12 using a second decoding method corresponding to the second encoding method, and send the decoded second data to the CPU if no error occurs during the decoding process;

[0032] The IP module 12 is configured to decode the first data encoded from the AXI host 11 using a first decoding method corresponding to the first encoding method, and output the decoded first data to the data storage when no error occurs during the decoding process; it is also configured to encode the second data from the data storage using the second encoding method, and send the encoded second data to the AXI host 11.

[0033] Exemplarily, the first encoding mode and the second encoding mode can be the same, and specifically can be an ECC encoding mode in which 64 ratio data bits are added with 8-bit ECC check bits.

[0034] The application of automotive electronic chips is related to life safety, and the design of environmental adaptability performance is full of challenges. It needs to go through various harsh environments such as high temperature, rain and snow, electromagnetic wave interference and vibration. Different driving environments also put different requirements on the design of controller performance. Anti-interference performance is a key indicator for evaluating the actual performance of vehicle-mounted controllers in the current market. Reliability is also improved by many orders of magnitude compared with consumer products.

[0035] The IP function safety system provided by the embodiment of the present disclosure adopts the encoding and decoding mode to process the transmitted data when the AXI host and the IP module perform data transmission, thereby ensuring the reliability of data transmission and improving the security of IP function.

[0036] In an exemplary example, as shown in Figure 2 The IP module 12 includes an AXI slave 121 and a random memory 122, wherein:

[0037] The AXI slave 121 is configured to decode the first data encoded by the AXI host 11 in the first decoding mode, encode the decoded first data in the third encoding mode when no error occurs in the decoding process, and write the encoded first data to the random memory 122; and is further configured to decode the second data encoded by the random memory 122 in the fourth decoding mode corresponding to the fourth encoding mode, encode the decoded second data in the second encoding mode when no error occurs in the decoding process, and send the encoded second data to the AXI host 11.

[0038] The random memory 122 is configured to decode the first data encoded by the AXI slave 121 in the third decoding mode corresponding to the third encoding mode, and output the decoded first data to the data storage when no error occurs in the decoding process; and is further configured to encode the second data from the data storage in the fourth encoding mode, and send the encoded second data to the AXI slave 121.

[0039] Exemplarily, the third encoding mode and the fourth encoding mode can be the same, and specifically can be an ECC encoding mode in which 8-bit data bits are added with 5-bit ECC check bits.

[0040] Exemplarily, the random memory includes: a random access memory (RAM) and a static random access memory (SRAM).

[0041] In an exemplary instance, as shown in Figure 3 The AXI slave 121 includes an AXI write module 1211 and an AXI read module 1212, the AXI write module 1211 includes a first decoder 1211a and a first encoder 1211b, and the AXI read module 1212 includes a second decoder 1212a and a second encoder 1212b, wherein:

[0042] The first decoder 1211a is configured to decode the first data from the AXI master 11 by using the first decoding mode, and send the decoded first data to the first encoder 1211b when no error occurs in the decoding process.

[0043] The first encoder 1211b is configured to encode the first data by using the third encoding mode, and write the encoded first data into the random memory 122.

[0044] The second decoder 1212a is configured to decode the second data from the random memory 122 by using the fourth decoding mode, and send the decoded second data to the second encoder 1212b when no error occurs in the decoding process.

[0045] The second encoder 1212b is configured to encode the second data by using the second encoding mode, and send the encoded second data to the AXI master 11.

[0046] In an exemplary instance, as shown in Figure 4 The random memory 122 includes a write data random memory 1221, a read data random memory 1222, a third encoder 1223, and a third decoder 1224, wherein:

[0047] The write data random memory 1221 is configured to save the first data encoded by the third encoding mode and written by the first encoder 1211b.

[0048] The third decoder 1224 is configured to decode the encoded first data read from the write data random memory 1222 by using the third decoding mode, and output the decoded first data to the data memory when no error occurs in the decoding process.

[0049] The third encoder 1223 is configured to encode the second data from the data storage in the fourth encoding mode and write the encoded second data into the read data random storage 1221.

[0050] The read data random storage 1222 is configured to save the encoded second data written by the second encoder and receive the read of the encoded second data by the second decoder.

[0051] In an exemplary embodiment, as shown in Figure 5 The AXI write module 1211 further includes a write check unit 1211c, and the AXI read module 1212 further includes a read check unit 1212c.

[0052] The AXI host 11 is further configured to process the write address of the third data to be written into the AXI slave 121 to obtain write check information, send the write address and the third data to the write check unit 1211c together, and process the read address of the fourth data to be read from the AXI slave 121 to obtain read check information and send the read address to the read check unit 1212c together.

[0053] The write check unit 1211c is configured to check the write address according to the write check information, and write the third data into the write data random storage 1221 according to the write address when the check is passed.

[0054] The read check unit 1212c is configured to check the read address according to the read check information, and read the fourth data from the read data random storage 1222 according to the read address when the check is passed, and return to the AXI host 11.

[0055] Exemplarily, the AXI host can specifically perform parity check processing on the write address of the third data to be written into the AXI slave 121 to obtain write check information, and perform parity check processing on the read address of the fourth data to be read from the AXI slave 121 to obtain read check information.

[0056] Exemplarily, parity is a data check mechanism for judging whether bit errors occur in the storage or transmission process of data. ECC check can correct single-bit errors and detect double-bit errors, but cannot correct errors of more than 1 bit, and cannot detect errors of more than 2 bits.

[0057] In an exemplary embodiment, as shown in Figure 6 The IP module 12 further includes a first register 123.

[0058] The first decoder 1211a is further configured to write error information generated when an error occurs in a decoding process of decoding the encoded first data into the first register 123 as a first variable;

[0059] The second decoder 1212a is further configured to write error information generated when an error occurs in a decoding process of decoding the encoded second data into the first register 123 as a second variable;

[0060] The third decoder 1224 is further configured to write error information generated when an error occurs in a decoding process of decoding the encoded first data into the first register 123 as a third variable;

[0061] The first register 123 is configured to store the content of the first variable, the content of the second variable and the content of the third variable, and receive reading of the content of the first variable, the content of the second variable and the content of the third variable by the CPU.

[0062] In an exemplary example, as shown in Figure 7 The IP module further includes a second register 124.

[0063] The write check unit 1211c is further configured to write error information generated when the write address fails to pass the check according to the write check information into a fourth variable of the second register 124.

[0064] The read check unit 1212c is further configured to write error information generated when the read address fails to pass the check according to the read check information into a fifth variable of the second register 124.

[0065] The second register 124 is configured to store the content of the fourth variable and the content of the fifth variable, and receive reading of the content of the fourth variable and the content of the fifth variable by the CPU.

[0066] The IP function safety system provided by the embodiments of the present disclosure involves reaching ASIL B of the IP function safety level according to the requirements and guiding ideology of ISO 26262. ISO 26262 is an important standard in the field of automotive electronics, and is the first functional safety standard applicable to mass production products. The design issue of functional safety has been valued in the automotive field, because it relates to personnel safety and company reputation and other issues. Through hazard analysis and risk assessment and V model design architecture, the functional safety requirement level is consistent with the analysis results, so as to facilitate the life cycle of the automotive electronic system to consider the required failure prevention technology and management requirements, and to be realized by the integrated process of design and development, verification and validation and other capability maturity models, so that the functional safety of the product meets the required automotive safety integrity level (ASIL).

[0067] The embodiments of the present disclosure also provide an IP function safety system, as shown in Figure 8

[0068] The AXI Master module and the IP module perform read and write operations on the internal registers and RAM through the AXI interface protocol of ARM.

[0069] The write path (Data out): the AXI Master needs to perform (64, 8) ECC encoding on WDATA before sending data. The write data (WDATA) sent from the AXI Master is decoded by the (64, 8) ECC decoding module (echeck_axi_wr_in), and the input of the write SRAM (WDATARAM) is encoded by the (8, 5) ECC encoding module (egen_mw). The WDATARAM output is decoded. If an error occurs in the ECC link decoding, the ECC_REG is reported and an interrupt is generated. The AWADDR address is added with a parity bit before being sent to the IP, and the parity check result is output after passing through the PAR CHECK parity check. If the PAR CHECK is wrong, the PAR_REG (corresponding to the second register in the above embodiment) is reported, and an interrupt is generated.

[0070] ​Read path (Data in): read in external data first to the ECC encoding module (8, 5) encoding, and then put into the read SRAM (RDATA RAM), and then through the ECC decoding module (ech eck_mr) (8, 5) decoding. Again through the ECC encoding module (egen_axi_rd_out) (64, 8) encoding RDATA, and finally sent to the AXI Master module. If the ECC link decoding error is reported to the ECC_REG and generates an interrupt. ARADDR address before sending to the IP plus parity bits, through the PAR CHECK parity, output the check result, if the PAR CHECK error, report to the PAR_REG, and generates an interrupt.

[0071] The embodiments of the present disclosure further provide a safety design of an IP functional safety system, which is embodied in the following five parts:

[0072] 1. Write data protection

[0073] AXI host before sending data to WDATA (64, 8) ECC encoding, from the AXI host write data (WDATA), through the ECC decoding module (echeck_axi_wr_in) (64, 8) decoding.

[0074] 2. Read data protection

[0075] Before the IP sends data to the AXI host, the RDATA is encoded by the ECC encoding module (egen_axi_rd_out) (64, 8).

[0076] 3. Read and write address protection

[0077] AWADDR and AWRADDR addresses before sending will be added parity bits, through the PAR CHECK parity, output the check result.

[0078] 4. SRAM (static memory) storage protection

[0079] The input of the read and write SRAM (WDATA RAM and RDATA RAM) will be added (8, 5) ECC encoding, and the output will be ECC decoding.

[0080] 5. Error reporting

[0081] PAR CHECK error, report to the PAR_REG and generate an interrupt; ECC decoding error is reported to the ECC_REG and generates an interrupt.

[0082] The embodiments of the present disclosure further provide an IP module, such as Figure 9As shown, the IP module includes an AXI slave 121 and a random memory 122, and is configured to be connected with an AXI master and a data memory, respectively.

[0083] The AXI slave 121 is configured to decode the first data encoded by the AXI master by using the first decoding mode, encode the decoded first data by using a third encoding mode when no error occurs in the decoding process, and write the encoded first data to the random memory 122; and decode the second data encoded by the random memory 122 by using a fourth decoding mode corresponding to the fourth encoding mode, encode the decoded second data by using the second encoding mode when no error occurs in the decoding process, and send the encoded second data to the AXI master.

[0084] The random memory 122 is configured to decode the first data encoded by the AXI slave 121 by using a third decoding mode corresponding to the third encoding mode, and output the decoded first data to the data memory when no error occurs in the decoding process; and encode the second data from the data memory by using the fourth encoding mode, and send the encoded second data to the AXI slave 121.

[0085] The IP module provided by the embodiments of the present disclosure processes the transmitted data by using the encoding and decoding mode when performing data transmission with the AXI master, thereby ensuring the reliability of data transmission and improving the security of IP function.

[0086] The embodiments of the present disclosure further provide a SoC chip including the IP module described in the above embodiments.

[0087] The embodiments of the present disclosure further provide an IP function security method applied to the IP function security system described in any of the above embodiments, such as Figure 10 As shown, the IP module includes an AXI slave 121 and a random memory 122, and is configured to be connected with an AXI master and a data memory, respectively.

[0088] Step 201: The AXI master encodes first data from a CPU by using a first encoding mode, and sends the encoded first data to the IP module.

[0089] Step 202: The IP module decodes the first data encoded by the AXI master by using a first decoding mode corresponding to the first encoding mode, and outputs the decoded first data to a data memory when no error occurs in the decoding process.

[0090] Step 203, the IP module encodes the second data from the data storage by using the second encoding mode, and sends the encoded second data to the AXI host;

[0091] Step 204, the AXI host decodes the second data encoded by the IP module by using the second decoding mode corresponding to the second encoding mode, and sends the decoded second data to the CPU when no error occurs in the decoding process.

[0092] In an exemplary instance, the IP module comprises: an AXI slave, a random memory.

[0093] In an exemplary instance, the IP function safety method provided by the embodiment of the present disclosure further comprises:

[0094] Firstly, the AXI slave decodes the first data encoded by the AXI host by using the first decoding mode, encodes the decoded first data by using a third encoding mode when no error occurs in the decoding process, and writes the encoded first data to the random memory;

[0095] Secondly, the random memory decodes the first data encoded by the AXI slave by using a third decoding mode corresponding to the third encoding mode, and outputs the decoded first data to the data storage when no error occurs in the decoding process;

[0096] Thirdly, the AXI slave decodes the second data encoded by the random memory by using a fourth decoding mode corresponding to a fourth encoding mode, encodes the decoded second data by using the second encoding mode when no error occurs in the decoding process, and sends the encoded second data to the AXI host;

[0097] Finally, the random memory encodes the second data from the data storage by using the fourth encoding mode, and sends the encoded second data to the AXI slave.

[0098] In an exemplary instance, the AXI slave comprises: an AXI write module and an AXI read module, the AXI write module comprises: a first decoder and a first encoder, and the AXI read module comprises: a second decoder and a second encoder.

[0099] In an exemplary instance, the IP function safety method provided by the embodiment of the present disclosure further comprises:

[0100] Firstly, the first decoder decodes the first data from the AXI host using the first decoding mode, and sends the decoded first data to the first encoder when no error occurs in the decoding process;

[0101] Secondly, the first encoder encodes the first data using the third encoding mode, and writes the encoded first data into the random memory;

[0102] Thirdly, the second decoder decodes the second data from the random memory using the fourth decoding mode, and sends the decoded second data to the second encoder when no error occurs in the decoding process;

[0103] Finally, the second encoder encodes the second data using the second encoding mode, and sends the encoded second data to the AXI host.

[0104] In an exemplary example, the random memory comprises a read data random memory, a write data random memory, a third encoder and a third decoder.

[0105] In an exemplary example, the IP function safety method provided by the embodiment of the present disclosure further comprises:

[0106] Firstly, the write data random memory stores the first data encoded by the third encoding mode and written by the first encoder;

[0107] Secondly, the third decoder decodes the encoded first data read from the write data random memory using the third decoding mode, and outputs the decoded first data to a data storage when no error occurs in the decoding process;

[0108] Thirdly, the third encoder encodes the second data from the data storage using the fourth encoding mode, and writes the encoded second data into the read data random memory;

[0109] Finally, the read data random memory stores the encoded second data written by the second encoder, and receives reading of the encoded second data by the second decoder.

[0110] In an exemplary example, the AXI write module further comprises a write check unit, and the AXI read module further comprises a read check unit.

[0111] In an exemplary example, the IP function safety method provided by the embodiment of the present disclosure further comprises:

[0112] The AXI master processes a write address of third data to be written into the AXI slave to obtain write check information, and sends the write address and the third data to the write check unit; processes a read address of fourth data to be read from the AXI slave to obtain read check information, and sends the read address to the read check unit;

[0113] Secondly, the write check unit checks the write address according to the write check information, and writes the third data into the write data random memory according to the write address when the check is passed;

[0114] Thirdly, the read check unit checks the read address according to the read check information, and reads the fourth data from the read data random memory according to the read address when the check is passed, and returns the fourth data to the AXI master.

[0115] In an exemplary instance, the IP module further comprises a first register.

[0116] In an exemplary instance, the IP function safety method provided by the embodiment of the present disclosure further comprises:

[0117] Firstly, the first decoder writes generated error information into a first variable in the first register when an error occurs in a decoding process of decoding the encoded first data; the second decoder writes generated error information into a second variable in the first register when an error occurs in a decoding process of decoding the encoded second data; the third decoder writes generated error information into a third variable in the first register when an error occurs in a decoding process of decoding the encoded first data;

[0118] Secondly, the first register stores contents of the first variable, contents of the second variable and contents of the third variable, and receives reading of the contents of the first variable, the contents of the second variable and the contents of the third variable by the CPU.

[0119] In an exemplary instance, the IP module further comprises a second register.

[0120] In an exemplary instance, the IP function safety method provided by the embodiment of the present disclosure further comprises:

[0121] Firstly, the write check unit writes generated error information into a fourth variable in the second register when the write address is not checked according to the write check information; the read check unit writes generated error information into a fifth variable in the second register when the read address is not checked according to the read check information;

[0122] Secondly, the second register stores the content of the fourth variable and the content of the fifth variable, and receives reading of the content of the fourth variable and the content of the fifth variable by the CPU.

[0123] The IP function safety method provided by the embodiments of the present disclosure ensures the reliability of data transmission and improves the safety of IP functions by using the encoding and decoding method to process the transmitted data between the AXI host and the IP module during data transmission.

[0124] Those skilled in the art can understand that all or some steps in the above disclosed method, functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit such as an application-specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as known to those skilled in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

Claims

1. An IP functional safety system, characterized in that, The application relates to an AXI host and IP module, the AXI host is arranged to be connected with a CPU, and the IP module is arranged to be connected with a data memory, wherein: the AXI host is used for encoding first data from the CPU in a first encoding mode, and sending the encoded first data to the IP module; and is also used for decoding second data from the IP module in a second decoding mode corresponding to a second encoding mode, and sending the decoded second data to the CPU when no error occurs in the decoding process; the IP module is used for decoding the first data from the AXI host in a first decoding mode corresponding to the first encoding mode, and outputting the decoded first data to the data memory when no error occurs in the decoding process; and is also used for encoding second data from the data memory in the second encoding mode, and sending the encoded second data to the AXI host; the IP module comprises an AXI slave and a random memory, wherein: the AXI slave is used for decoding the first data from the AXI host in the first decoding mode, encoding the decoded first data in a third encoding mode when no error occurs in the decoding process, and writing the encoded first data into the random memory; and is also used for decoding second data from the random memory in a fourth decoding mode corresponding to a fourth encoding mode, encoding the decoded second data in the second encoding mode when no error occurs in the decoding process, and sending the encoded second data to the AXI host; the random memory is used for decoding the first data from the AXI slave in a third decoding mode corresponding to the third encoding mode, and outputting the decoded first data to the data memory when no error occurs in the decoding process; and is also used for encoding second data from the data memory in the fourth encoding mode, and sending the encoded second data to the AXI slave. the AXI slave comprises an AXI write module and an AXI read module, the AXI write module comprises a first decoder and a first encoder, and the AXI read module comprises a second decoder and a second encoder, wherein:

2. The system of claim 1, wherein, the first decoder is used for decoding the first data from the AXI host in the first decoding mode, and sending the decoded first data to the first encoder when no error occurs in the decoding process; the first encoder is used for encoding the first data in the third encoding mode, and writing the encoded first data into the random memory; and the second decoder is used for decoding second data from the random memory in the fourth decoding mode, and sending the decoded second data to the second encoder when no error occurs in the decoding process; the second encoder is used for encoding the second data in the second encoding mode, and sending the encoded second data to the AXI host. The second decoder is configured to decode the second data from the random memory by using the fourth decoding mode, and send the decoded second data to the second encoder when no error occurs in the decoding process; The second encoder is configured to encode the second data by using the second encoding mode, and send the encoded second data to the AXI host.

3. The system of claim 2, wherein, The random memory comprises a read data random memory, a write data random memory, a third encoder and a third decoder, wherein: The write data random memory is configured to save the first data encoded by the third encoding mode and written by the first encoder; The third decoder is configured to decode the encoded first data read from the write data random memory by using the third decoding mode, and output the decoded first data to the data storage when no error occurs in the decoding process; The third encoder is configured to encode the second data from the data storage by using the fourth encoding mode, and write the encoded second data to the read data random memory; The read data random memory is configured to save the encoded second data written by the second encoder, and receive reading of the encoded second data by the second decoder.

4. The system of claim 3, wherein, The AXI write module further comprises a write check unit, and the AXI read module further comprises a read check unit; The AXI host is further configured to process a write address of third data to be written into the AXI slave to obtain write check information, send the write check information to the write check unit together with the write address and the third data, process a read address of fourth data to be read from the AXI slave to obtain read check information, and send the read check information to the read check unit together with the read address; The write check unit is configured to check the write address according to the write check information, and write the third data into the write data random memory according to the write address when the check is passed; The read check unit is configured to check the read address according to the read check information, and read the fourth data from the read data random memory according to the read address when the check is passed, and return the fourth data to the AXI host.

5. The system of claim 3, wherein, The IP module further comprises a first register; The first decoder is further configured to write error information generated when an error occurs in the decoding process of the encoded first data into a first variable in the first register; The second decoder is further configured to write error information generated when an error occurs in the decoding process of the encoded second data into a second variable in the first register; The third decoder is further configured to write error information generated when an error occurs in the decoding process of the encoded first data into a third variable in the first register; and The fourth decoder is further configured to write error information generated when an error occurs in the decoding process of the encoded second data into a fourth variable in the first register. The first register is configured to store the content of the first variable, the content of the second variable and the content of the third variable, and receive reading of the content of the first variable, the content of the second variable and the content of the third variable by the CPU.

6. The system of claim 4, wherein, The IP module further comprises a second register; The write checking unit is further configured to write the generated error information into a fourth variable of the second register when the write address fails to pass the checking according to the write checking information; The read checking unit is further configured to write the generated error information into a fifth variable of the second register when the read address fails to pass the checking according to the read checking information; The second register is configured to store the content of the fourth variable and the content of the fifth variable, and receive reading of the content of the fourth variable and the content of the fifth variable by the CPU.

7. An IP module, characterized by Comprise: An AXI slave and a random memory, the IP module is respectively arranged to be connected with an AXI master and a data memory, wherein: The AXI slave is configured to decode first data from the AXI master by using a first decoding mode, encode the decoded first data by using a third encoding mode when no error occurs in the decoding process, and write the encoded first data into the random memory; and decode second data from the random memory by using a fourth decoding mode corresponding to a fourth encoding mode, encode the decoded second data by using a second encoding mode when no error occurs in the decoding process, and send the encoded second data to the AXI master; The random memory is configured to decode the first data from the AXI slave by using a third decoding mode corresponding to the third encoding mode, and output the decoded first data to the data memory when no error occurs in the decoding process; and encode the second data from the data memory by using the fourth encoding mode, and send the encoded second data to the AXI slave.

8. A SoC chip, characterized by, Comprise the IP module as claimed in claim 7.

9. An IP functional safety method, characterized by, Applied to the IP function safety system as claimed in any one of claims 1-6, comprising: The AXI master encodes first data from the CPU by using a first encoding mode, and sends the encoded first data to the IP module; The IP module decodes the encoded first data from the AXI master by using a first decoding mode corresponding to the first encoding mode, and outputs the decoded first data to a data memory when no error occurs in the decoding process; The IP module encodes second data from the data memory by using the second encoding mode, and sends the encoded second data to the AXI master; The IP module decodes the encoded first data from the AXI master by using a first decoding mode corresponding to the first encoding mode, and outputs the decoded first data to a data memory when no error occurs in the decoding process; The AXI master decodes the second data encoded by the IP module by using a second decoding mode corresponding to the second encoding mode, and sends the decoded second data to the CPU when no error occurs in the decoding process; The IP module comprises an AXI slave and a random memory, and the method further comprises: The AXI slave decodes the first data encoded by the AXI master by using the first decoding mode, encodes the decoded first data by using a third encoding mode when no error occurs in the decoding process, and writes the encoded first data into the random memory; and the AXI slave is further configured to decode second data encoded by the random memory by using a fourth decoding mode corresponding to a fourth encoding mode, encode the decoded second data by using the second encoding mode when no error occurs in the decoding process, and send the encoded second data to the AXI master; The random memory decodes the first data encoded by the AXI slave by using a third decoding mode corresponding to the third encoding mode, and outputs the decoded first data to the data memory when no error occurs in the decoding process; and the random memory is further configured to encode the second data from the data memory by using the fourth encoding mode, and send the encoded second data to the AXI slave.

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