A method for designing FPGA simulation device for voltage sag event inversion

Abstract

The application provides a FPGA simulation device design method for voltage sag event inversion. First, a Field Programmable Gate Array (FPGA) simulation device overall architecture design method based on a distribution network feeder electromagnetic transient model and a reduced-order model thereof is described. Then, a monitor analysis index calculation method is designed through comparison of FPGA calculation results of two types of model algorithms. The position of a fault point, a grounding resistance and voltage transient characteristic values are solved through electromagnetic transient discrete algebraic equation set inversion. Finally, a hardware timing analysis method of the FPGA simulation device for voltage sag event inversion is provided.

Description

Technical Field

[0001] This invention belongs to the field of power quality analysis and management of active distribution networks, and specifically relates to a design method for an FPGA (Field Programmable Gate Array) simulation device for voltage sag event inversion. Background Technology

[0002] The feeders of the distribution network connect to a large number of industrial loads, placing high demands on power quality. Statistics show that over 90% of power quality problems are caused by voltage sags, resulting in significant economic losses for users. Short-circuit faults are the primary cause of voltage sags, with single-phase faults having the highest probability of occurrence among all types of short-circuit faults. In recent years, the penetration rate of renewable energy sources in my country's distribution network has been increasing, and the grounding method of renewable energy sources directly affects the magnitude of single-phase fault current after a fault. Furthermore, current methods for locating voltage sags caused by faults are highly dependent on load conditions and are all conducted at the steady-state level, with few considering transient simulation methods for locating voltage sag sources. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention combines distribution network voltage sag mitigation with Field Programmable Gate Array (FPGA) electromagnetic transient simulation technology to provide a design method for an FPGA simulation device oriented towards voltage sag event inversion. Starting with grounding faults occurring in distribution network feeders, a full electromagnetic transient model of the feeder system is established based on electromagnetic transient simulation modeling methods. Furthermore, based on the relationship between waveform point electrical quantities and discrete simulation time-time variables, the voltage sag phenomenon caused by a single-phase grounding fault is analyzed in depth, along with the corresponding system voltage and current balance at that time. This enables the identification of the fault location causing the voltage sag.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A design method for an FPGA simulation device oriented towards voltage sag event inversion includes the following steps:

[0006] Step (1) Design the overall architecture of the FPGA simulation device based on the electromagnetic transient model of the distribution network feeder and its reduced-order model;

[0007] Step (2) By comparing the FPGA calculation results of two types of model algorithms—namely, the full-order model electromagnetic transient algorithm and the reduced-order model electromagnetic transient algorithm—a method for calculating monitor analysis indicators is designed.

[0008] Step (3) Solve for the fault location, grounding resistance, and voltage transient characteristics;

[0009] Step (4) Design the FPGA simulation device hardware timing analysis method for voltage sag event inversion.

[0010] Further, in step (1), the overall architecture of the simulation device consists of SoC-FPGA-1, SoC-FPGA-2 and a host PC; wherein, the PL side of SoC-FPGA-1 performs electromagnetic transient simulation of the actual distribution network feeder, the PL side of SoC-FPGA-2 performs electromagnetic transient model simulation after the distribution network is reduced in order, the PS side of SoC-FPGA-2 performs voltage sag event inversion algorithm according to the electromagnetic transient model after the reduced in order, and the host PC completes data storage and command interaction.

[0011] Further, step (1) includes the selection of FPGA chips used in the overall architecture design of the simulation device, analysis of computing resources, analysis of interface chips and protocols between SoC-FPGA-1 and SoC-FPGA-2 and between SoC-FPGA-2 and the host PC, interface data transmission methods, and description of the PL and PS side computing processes of SoC-FPGA-1 and SoC-FPGA-2.

[0012] Further, step (2) includes: analyzing and comparing the deviations of the results in RT-Lab, the actual system, i.e. the original all-electromagnetic transient model (FPGA-SoC-1), and the simulated reduced-order model (FPGA-SoC-2), in order to detect voltage sag anomalies in the active distribution network feeder system.

[0013] Furthermore, step (3) uses a set of electromagnetic transient discrete algebraic equations to solve for the location of the fault point, the magnitude of the grounding resistance, and the grounding voltage value. Then, based on the calculation results, a specific inversion process for the voltage sag event is designed.

[0014] Furthermore, step (4) is used to optimize the computational performance of the overall architecture of the simulation device and to analyze the operation timing of the simulator's computation process. Specifically, it includes optimizing the parallel computing capability of the FPGA electromagnetic transient model during the simulation time and the transmission time of the simulation data input to the monitor.

[0015] Beneficial effects:

[0016] This invention is a real-time hardware simulation system that can directly perform test and inversion analysis on voltage sag events, which has the advantages of reducing the manpower and material resources required for on-site testing and being safe and efficient. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall architecture of the FPGA simulation device design method for voltage sag event inversion according to the present invention.

[0018] Figure 2Flowchart for the inversion calculation of voltage sag in distribution network feeders;

[0019] Figure 3 This is a schematic diagram of the hardware timing analysis results for an FPGA simulation device. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0021] The FPGA simulation device design method for voltage sag event inversion according to the present invention specifically includes the following steps:

[0022] Step 1: Design the overall architecture of the FPGA simulation device based on the electromagnetic transient model.

[0023] This step proposes the overall architecture of a Field-Programmable Gate Array (FPGA) simulation device for voltage sag event inversion. The designed simulation device architecture consists of two System-on-a-Chip (SoC) FPGAs and one host PC. Specifically, the Programmable Logic (PL) side of SoC-FPGA-1 performs electromagnetic transient simulation of actual power distribution network feeders. The SFP stands for Small Form Pluggable, meaning a small pluggable fiber optic communication module. The PL side of SoC-FPGA-2 performs electromagnetic transient model simulation after the power distribution network undergoes a reduced-order transformation. The Processing System (PS) side of SoC-FPGA-2 performs a voltage sag event inversion algorithm based on the reduced-order electromagnetic transient model. Additionally, the host PC, via Ethernet and fiber optic ports, primarily handles simulation data storage, sag event recording, and command interaction. It is worth noting that this simulation device also includes the RT-Lab real-time simulator, which performs real-time simulation of the power distribution feeder to realistically simulate the actual system operation. Electromagnetic simulation is performed on the PL side of SoC-FPGA-1 and SoC-FPGA-2, including system simulation calculation modules and simulation modules for important components of the active power distribution network. The simulator calculation flow is as follows: Figure 1 As shown, the specific steps are as follows:

[0024] Step 1.1 The SoC-FPGA board used in this architecture is the ZCU106 evaluation kit, equipped with an xczu7ev-ffvc1156-2-e chip. This chip contains 230,400 LUTs, 460,800 FFs, and 1,728 DSP resources. It is externally connected to Micron's 4Gb MT40A256M16GE-075E DDR4 memory, and the PS side is a quad-core Cortex-A53 processor. The electromagnetic transient simulation calculations of this invention are completed in the ZCU106 board, while the power grid / actual system is simulated in RT-Lab. The ZCU106 is connected to RT-Lab through a high-speed AD module FL9613. The data is input to the PL side of the SoC-FPGA after passing through a filtering module. The AD module contains two AD9613 chips, with a maximum sampling rate of 250M. Because the SoC-FPGA-1 performs full-network electromagnetic simulation, it needs to send a large amount of data to the host computer. Therefore, the host PC and SoC-FPGA-1 are connected via a TL-TC532-1 cable, and the communication protocol on the PL side of the SoC-FPGA-1 is implemented based on the UDP (User Datagram Protocol, a basic communication protocol). Since the SoC-FPGA-2 transmits less data to the host computer and has lower real-time requirements but higher data reliability requirements, the host computer and SoC-FPGA-2 are connected via a network cable, and the communication protocol on the PS side of the SoC-FPGA-2 is implemented based on the LwIP (Lightweight IP, a lightweight TCP / IP protocol).

[0025] Step 1.2 First, the SoC-FPGA-2 acquires the three-phase voltage v of the active nodes of the original power grid (or the power grid topology simulated by RT-Lab). abc Three-phase current i abc The instantaneous value signal of the electrical quantity is then input to the PL side of the SoC-FPGA-2 through the AD module on the FMC interface. After data filtering and instantaneous amplitude calculation, the instantaneous amplitude x is finally calculated. j (j∈[0,1,2,..,M]) is input to the monitor.

[0026] When steps 1.3 and 1.1 are performed in parallel, and the electromagnetic simulation calculation of the Kron reduced-order network in SoC-FPGA-2 is completed, the three-phase voltage of the active node in SoC-FPGA-2 is calculated. Three-phase current The instantaneous signals of electrical quantities are input to calculation modules such as the instantaneous symmetrical component method module for solving, and the instantaneous amplitude is also input to the monitor.

[0027] Step 1.4 The monitor performs anomaly detection on the original network data collected in this time step based on the average deviation of historical data. If an anomaly is found, the voltage sag event inversion module on the PS side of SoC-FPGA-2 can detect the anomaly and send the result to the host computer network port through the SGMII interface of SoC-FPGA-2.

[0028] Step 1.5: The host PC parses the uploaded instruction set data packet. If it receives an error message from SoC-FPGA-2, it locks the original electromagnetic transient simulation of the power grid on SoC-FPGA-1. Since SoC-FPGA-1 performs ultra-real-time simulation, the host PC clears the erroneous simulation data after time t based on the waveform point time t, and inputs the new node admittance matrix and fault point voltage and current information into SoC-FPGA-1 to re-perform the electromagnetic transient simulation of the original power network. The topology inversion algorithm flow for single-feeder and multi-feeder scenarios is as follows: Figure 2 As shown, the data obtained by the algorithm instruction set includes: waveform point time t, fault location τ, and instantaneous grounding resistance R. r Instantaneous node voltage u at the fault location f Historical Current of Energy Storage Components f The system stores data such as historical data in the DDR of the PL side of the SoC-FPGA-2.

[0029] Step 2: Design the monitor analysis index calculation method:

[0030] Based on the overall architecture of the FPGA simulation device design, the monitor on the FPGA-PL side is used to analyze and compare the deviations between the results in RT-Lab / actual system and the analog downgraded system SoC-FPGA-2 in order to detect system anomalies.

[0031] The monitoring process designed in this invention consists of a limiter module and a comparator module. The limiter is calculated by the active nodes of a Krono network at each time step. The absolute error offset T from historical data j Composition, T j The expression is:

[0032]

[0033] In the formula, n is the number of historical data used, N is the time counter, M is the number of measurable electrical quantity nodes, and x j，k This is the measurement value of the j-th source node at time k in the actual system.

[0034] The comparator module is used to calculate the values ​​of each active node. The maximum and minimum values ​​that can be offset to set the maximum offset range H of the active nodes in the actual system.j .

[0035]

[0036] The monitor module is designed based on relevant formulas; if the measured value x j Exceeding the defined offset range H j If so, it is considered that an anomaly has occurred in the actual network.

[0037] Step 3: Design a method for calculating the location of the fault and the transient characteristics of the voltage:

[0038] This invention proposes information regarding the short-circuit location τ and the node voltage at the waveform point. The quadratic equation is as follows:

[0039]

[0040] Solving equation (3) yields:

[0041]

[0042] In formula (3), The nodal admittance matrix is ​​reduced to the contracted admittance matrix at the fault point after being reduced in order. This is the nodal admittance matrix connected to the power source point; The voltage of the node to be determined at the fault point; This refers to the voltage at the power supply node; The historical current source on the side of the line fault point; For the historical current source on the other side of the line fault point; G 23m To account for the admittance value of the line in the event of a fault; Inject a current source into the side of the line fault point at the current moment; Inject a current source into the other side of the line fault point at the current moment. Here, the superscript 0 indicates the previous moment; the superscript 1 indicates the current moment.

[0043] In formula (4), G 23 This is the admittance value of the line when there is no fault; and These are the voltage values ​​at the previous and current moments on the side of the line fault point, respectively; and These are the voltage values ​​on the other side of the line fault point at the previous and current moments, respectively; τ a τ b and τ c These are variables used in the intermediate calculation process.

[0044] Therefore, as Figure 2 As shown, the specific steps for voltage sag event inversion are as follows:

[0045] 1) The measurement equipment collects data streams, and the monitor compares the actual network data transmitted by the measurement equipment with the Kron reduced-order equivalent network simulation data to determine whether there are any anomalies in the actual network.

[0046] 2) Infer the voltage and current information of the locations adjacent to the measurement point, and use fault location algorithms under different scenarios.

[0047] 3) For a single feeder, based on the voltage and current of the first and last nodes of the equivalent network after Kron reduction, solve for the voltage and current values ​​of all active nodes in the network after Kron reduction.

[0048] 4) Solve for the fault location τ of the network after Kron reduction according to equation (4).

[0049] 5) Based on the principle that the fault location is approximately unchanged, the original network fault location τ* can be obtained, and then the node admittance matrix at the waveform point can be formed.

[0050] Step 4: Design of FPGA simulation device hardware timing analysis method

[0051] To optimize the computational performance of the overall architecture of the simulation device, the timing of the simulator's computation process is analyzed. The assumption that the active node data at each time step of the actual system is measurable must be met; that is, the active node data at each time step of both the actual system and the Kron-reduced system can be analyzed by a monitor. Therefore, both SoC-FPGA-1 and SoC-FPGA-2 need to complete ultra-real-time electromagnetic transient simulation. This means that each discrete time step of the electromagnetic transient simulation on the FPGA-PL side needs to be completed within the actual discrete time. Since the electromagnetic transient simulation is time-consuming, the parallel processing capability of the FPGA can be used to parallelize the original power distribution network voltage v. abc Current i abc The steps for inputting actual data into the monitor are as follows: Wait for the electromagnetic simulation to finish before sending the simulation data to the monitor.

[0052] This invention designs a voltage sag event inversion algorithm on the PS side of the SoC-FPGA-2. Since the algorithm has no real-time requirements and, as shown in equation (3), the solution scale is relatively small; furthermore, as shown in equation (4), this invention has already obtained a fixed form of the transient solution, eliminating the need for nonlinear iterative solutions. Therefore, no optimization is performed on the PS side of the SoC-FPGA-2. The computation time of each module designed in this invention was measured at a 125MHz clock. Based on the above analysis, Figure 3 The optimized global timing diagram of this simulator is presented.

[0053] exist Figure 3 In the middle, t RT-lab The original network electromagnetic transient simulation time is t. full-gridThe electromagnetic transient ultra-real-time simulation time of the original network SoC-FPGA-1 is t. AD For the AD sampling time of SoC-FPGA-2, t filter For the SoC-FPGA-2 filtering time, t am Solving for the instantaneous amplitude time t of SoC-FPGA-2 Kron For the electromagnetic transient ultra-real-time simulation time of the SoC-FPGA-2Kron reduced-order network, t monitor The time for monitoring analysis.

[0054] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A design method for an FPGA simulation device oriented towards voltage sag event inversion, characterized in that, Includes the following steps: Step (1) Design the overall architecture of the FPGA simulation device based on the electromagnetic transient model of the distribution network feeder and its reduced-order model; the overall architecture of the simulation device consists of SoC-FPGA-1, SoC-FPGA-2 and a host PC; wherein, the PL side of SoC-FPGA-1 performs electromagnetic transient simulation of the actual distribution network feeder, the PL side of SoC-FPGA-2 performs electromagnetic transient model simulation after the reduced-order transformation of the distribution network, the PS side of SoC-FPGA-2 performs voltage sag event inversion algorithm according to the reduced-order electromagnetic transient model, and the host PC completes data storage and command interaction; Step (2) By embedding two types of model algorithms, namely the full-order model electromagnetic transient algorithm and the reduced-order model electromagnetic transient algorithm, the FPGA calculation results are compared, and a monitor analysis index calculation method is designed; the deviations of the results in RT-Lab, the actual system, namely the original full electromagnetic transient model SoC-FPGA-1 and the simulated reduced-order model SoC-FPGA-2 are analyzed and compared, that is, the deviations of the results in SoC-FPGA-1 and SoC-FPGA-2, in order to detect voltage sag anomalies in the active distribution network feeder system; Step (3) Solve for the fault location, grounding resistance, and voltage transient characteristics; use the electromagnetic transient discrete algebraic equations to solve for the fault location, grounding resistance, and grounding voltage, and then design a specific inversion process for the voltage sag event based on the calculation results; Step (4) Design the FPGA simulation device hardware timing analysis method for voltage sag event inversion.

2. The FPGA simulation device design method for voltage sag event inversion as described in claim 1, characterized in that: Step (1) includes the selection of FPGA chips used in the overall architecture of the simulation device, analysis of computing resources, analysis of interface chips and protocols between SoC-FPGA-1 and SoC-FPGA-2 and between SoC-FPGA-2 and the host PC, interface data transmission methods, and description of the PL and PS side computing processes of SoC-FPGA-1 and SoC-FPGA-2.

3. The FPGA simulation device design method for voltage sag event inversion as described in claim 1, characterized in that: Step (4) is used to optimize the computational performance of the overall architecture of the simulation device and to analyze the operation timing of the simulator's computation process. Specifically, it includes optimizing the parallel computing capability of the FPGA electromagnetic transient model during the simulation time and the transmission time of the simulation data input to the monitor.

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