Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes at least two pixel circuits arranged in an array. Each pixel circuit includes an initialization transistor for initializing the pixel circuit; an initialization line connected to the initialization transistor and used to provide an initialization voltage to the initialization transistor; initialization transistors of two adjacent columns of pixel circuits are connected to the same initialization line extending along the column direction; initialization transistors of two adjacent columns of pixel circuits in the same row share the same via and are connected to the initialization line. The technical solution provided by this embodiment solves the problem of low light transmittance of the display panel, which does not meet the transmittance requirements of under-display optical devices.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for display panels. Existing display panels have low light transmittance, which does not meet the light transmittance requirements of under-display optical devices. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the problem that the light transmittance of the display panel is low and does not meet the transmittance requirements of under-display optical devices.

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution:

[0005] This invention provides a display panel, comprising:

[0006] At least two pixel circuits, arranged in an array;

[0007] Each pixel circuit includes an initialization transistor, which is used to initialize the pixel circuit.

[0008] The initialization line is connected to the initialization transistor and is used to provide the initialization voltage to the initialization transistor.

[0009] The initialization transistors of two adjacent columns of pixel circuits are connected to the same initialization line extending along the column direction;

[0010] The initialization transistors of two adjacent columns of pixel circuits located in the same row share the same via and are connected to the initialization line. This arrangement allows the initialization transistors of two adjacent columns of pixel circuits located in the same row to be directly electrically connected to the initialization line through the same via, which effectively saves the number of initialization lines extending along the column direction and improves the light transmittance of the display panel to meet the light transmittance requirements of under-display optical devices.

[0011] Optionally, initializing the transistors includes:

[0012] A first initialization transistor and a second initialization transistor, wherein the first initialization transistor is used to transmit a second initialization voltage to the anode of the light-emitting element of the pixel circuit, and the second initialization transistor is used to transmit a first initialization voltage to the gate of the driving transistor of the pixel circuit.

[0013] The vias include a first via and a second via;

[0014] The first initialization transistors of two adjacent columns of pixel circuits in the same row share a first via, and the second initialization transistors of two adjacent columns of pixel circuits in the same row share a second via. This configuration reduces the number of vias connected to the initialization lines, thereby reducing the number of initialization lines. By reducing the number of initialization lines, the number of initialization lines with poor light transmittance can be reduced, thereby improving the light transmittance of the pixel circuits and thus improving the light transmittance of the display panel.

[0015] Optionally, the first initialization transistors of the (2n-1)th column pixel circuit and the 2nth column pixel circuit in the same row share the first via.

[0016] The second initialization transistors of the (2n-1)th column pixel circuit and the 2nth column pixel circuit in the same row share a second via; where n is an integer greater than 0. This configuration reduces the number of vias connected to the initialization lines from the first column pixel circuit to the 2nth column pixel circuit, further reducing the number of initialization lines with poor light transmittance, thereby improving the light transmittance of the pixel circuit and further improving the light transmittance of the display panel.

[0017] Optionally, the pixel circuitry includes an active layer;

[0018] Along the column direction, the active layers of adjacent pixel circuits are mirror-symmetrical about the axis of symmetry;

[0019] Preferably, the second vias of the second initialization transistors of the pixel circuits located in adjacent columns are asymmetrically arranged along the axis of symmetry. This arrangement facilitates setting the first initialization transistors of the (2n-1)th and 2nth column pixel circuits in the same row to share a first via, and also facilitates setting the second initialization transistors of the (2n-1)th and 2nth column pixel circuits in the same row to share a second via. This arrangement also facilitates reserving sufficient space for setting the first power line extending along the column direction.

[0020] Optional initialization lines include:

[0021] At least one first initialization line extending along the column direction and at least one first initialization line extending along the row direction; the first initialization line extending along the column direction and the first initialization line extending along the row direction are connected by a third via;

[0022] The first initialization line extending along the column direction is connected to the second initialization transistors of the pixel circuits located in the two adjacent columns through the second via, for transmitting the first initialization voltage to the second initialization transistors of the pixel circuits located in the two adjacent columns. This arrangement facilitates the connection of the first initialization line extending along the column direction and the first initialization line extending along the row direction through the third via, and also saves the size of the connection trace between the first initialization line extending along the column direction and the first initialization line extending along the row direction, further improving the light transmittance of the display panel.

[0023] Optional, the initialization line also includes:

[0024] At least one second initialization line extending along the column direction and at least one second initialization line extending along the row direction; the second initialization line extending along the column direction and the second initialization line extending along the row direction are connected by a fourth via;

[0025] A second initialization line extending along the column direction is connected to the first initialization transistors of the pixel circuits located in two adjacent columns via a first via, for transmitting a second initialization voltage to the first initialization transistors of the pixel circuits located in the two adjacent columns. This configuration allows the pixel circuits located in two adjacent columns to share a single second initialization line, which transmits the second initialization voltage to the first initialization transistors of the pixel circuits located in the two adjacent columns.

[0026] Optionally, each pair of adjacent pixel circuits shares a first initialization line extending along the row direction, and each pair of adjacent pixel circuits shares a second initialization line extending along the row direction.

[0027] Preferably, the pixel circuits in row 2m-1 share the same second initialization line extending along the row direction as the pixel circuits in row 2m, and the pixel circuits in row 2m+1 share the same first initialization line extending along the row direction; where m is an integer greater than 0. This configuration reduces the number of first and second initialization lines extending along the row direction connected to the pixel circuits, thereby further improving the light transmittance of the pixel circuits and further improving the light transmittance of the display panel.

[0028] Optionally, the display panel may also include:

[0029] The first power line and the second power line, wherein the power voltage transmitted by the second power line is greater than the power voltage transmitted by the first power line.

[0030] The first power line extends along the column direction; adjacent column pixel circuits share one first power line.

[0031] Preferably, each row of pixel circuits is provided with two second power lines extending along the row direction;

[0032] Preferably, the first power line is arranged parallel to the initialization line extending along the column direction. This arrangement ensures that each row of pixel circuits has two second power lines extending along the row direction, which can effectively reduce the voltage drop on the second power lines, thereby improving the uniformity of the first voltage signal transmitted on each pixel circuit and thus improving the brightness uniformity of the display panel.

[0033] Optionally, the light-transmitting area of ​​the display panel is greater than 25%. This setting results in a higher light-transmitting area of ​​the display panel, which can better meet the light transmittance requirements of optical components installed under the display panel.

[0034] According to another aspect of the present invention, this embodiment provides a display device, comprising: a display panel as described in any of the first aspects.

[0035] The display panel provided in this embodiment of the invention arranges pixel circuit arrays such that the initialization transistors of two adjacent columns of pixel circuits are connected to the same initialization line extending along the column direction, and the initialization transistors of two adjacent columns of pixel circuits in the same row share the same via and are connected to the initialization line. This allows the pixel circuits in two adjacent columns to be directly electrically connected to the initialization transistors and initialization line in the same row through the same via, which effectively saves the number of initialization lines extending along the column direction and improves the light transmittance of the display panel to meet the light transmittance requirements of under-display optical devices. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of a pixel circuit for a display panel provided in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of a display panel layout provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the active layer of a display panel provided in an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0044] Based on the above-mentioned technical problems, this embodiment proposes the following solutions:

[0045] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. See also: Figure 1 The display device 200 provided in this embodiment includes a display panel 100. The display panel 100 includes multiple pixel circuits 1. The display device 200 may also include multiple scan lines S1-Sn, multiple data lines Vdata1-Vdatan, multiple light emission control lines EM1-EMn, and a driver chip 300. The pixel circuits 1 are disposed in the area defined by the intersection of the scan lines and the data lines. Scan signals are input to the corresponding pixel circuits 1 through the scan lines. Under the action of the scan signals input to the scan lines electrically connected to them, the pixel circuits 1 are connected to the corresponding electrically connected data lines. The driver chip 300 inputs data signals to the corresponding pixel circuits 1 through the data lines. The voltage of the data signals corresponds to the driving voltage, which determines the light emission brightness of the light-emitting element D1, that is, determines the display grayscale of the light-emitting element D1.

[0046] The light-emitting element D1 may include light-emitting elements with different emitting colors. It should be noted that this application uses light-emitting elements with red, green and blue emitting colors as examples for illustration. The light-emitting element D1 may also include light-emitting elements of other colors, and no limitation is made here.

[0047] The display panel 100 also includes an initialization line. Each pixel circuit 1 is connected to a first power line VSS, a second power line VDD, and the initialization line, respectively. The first power line VSS is used to transmit a second voltage signal to the cathode of the light-emitting element D1, which is typically a low-level signal. The second power line VDD is used to transmit a first voltage signal to the anode of the light-emitting element D1, which is typically a high-level signal.

[0048] Figure 2 This is a schematic diagram of the pixel circuit of a display panel according to an embodiment of the present invention. See also... Figure 2Pixel circuit 1 may include multiple thin-film transistors and a storage capacitor Cst. The thin-film transistors may include a driving transistor T1 and a switching transistor. The driving transistor T1 and the light-emitting element D1 are sequentially connected between the second power line VDD and the first power line VSS. The driving transistor T1 generates a driving current to drive the light-emitting element D1 connected to pixel circuit 1 to emit light. The switching transistor mainly functions as a switch. The switching transistor includes an initialization transistor. The light-emitting element D1 is driven by pixel circuit 1 to emit light. Pixel circuit 1 may, for example, employ... Figure 2 The pixel circuit shown. Combined with... Figure 1 and Figure 2 The pixel circuit 1 provided in this embodiment can correspond to Figure 1 A specific circuit structure of the pixel circuit 1 in the display panel 100 shown is, for example, a 7T1C pixel circuit.

[0049] Figure 3 This is a schematic diagram of a display panel layout provided in an embodiment of the present invention. See also: Figure 3 The display panel provided in this embodiment includes at least two pixel circuits 1, which are arranged in an array. Each pixel circuit 1 includes an initialization transistor for initializing the pixel circuit 1. An initialization line Vref is connected to the initialization transistor and is used to provide an initialization voltage to the initialization transistor. The initialization transistors of two adjacent columns of pixel circuits 1 are connected to the same initialization line Vref extending along the column direction. The initialization transistors Vref of two adjacent columns of pixel circuits 1 located in the same row share the same via and are connected to the initialization line Vref.

[0050] Specifically, the array arrangement of pixel circuits 1 can improve the wiring efficiency of pixel circuits 1 and save wiring space. Each pixel circuit 1 includes an initialization transistor, and the pixel circuit 1 is connected to the initialization line Vref through the initialization transistor. The initialization line Vref is used to transmit the initialization voltage, and the initialization transistor is turned on according to the scan signal at its control terminal to initialize the pixel circuit 1.

[0051] By setting initialization lines Vref extending along the column direction within the display panel, the number of initialization lines Vref extending along the row direction can be reduced. Connecting the initialization transistors of two adjacent columns of pixel circuits 1 to the same initialization line Vref along the column direction allows them to share the same line, reducing the number of Vref lines. Setting the initialization transistors of two adjacent columns of pixel circuits 1 in the same row to share the same via and initialization line Vref allows them to share the same via, reducing the number of vias and thus the size of the traces connecting the vias and initialization lines Vref. This configuration allows the initialization transistors of two adjacent columns of pixel circuits 1 in the same row to be directly electrically connected to the initialization line Vref through the same via, effectively saving the number of Vref lines extending along the column direction and improving the light transmittance of the display panel.

[0052] The display panel provided in this embodiment uses a pixel circuit 1 array arrangement. The initialization transistors of two adjacent columns of pixel circuit 1 are connected to the same initialization line Vref extending along the column direction. The initialization transistors of two adjacent columns of pixel circuit 1 in the same row share the same via and are connected to the initialization line Vref. This allows the pixel circuit 1 in two adjacent columns to be directly electrically connected to the initialization transistors of two adjacent columns of pixel circuit 1 in the same row and the initialization line Vref through the same via. This effectively saves the number of initialization lines Vref extending along the column direction and improves the light transmittance of the display panel to meet the light transmittance requirements of under-display optical devices.

[0053] Optionally, based on the above embodiments, further combinations can be made... Figure 2 and Figure 3 The initialization transistor of the pixel circuit 1 provided in this embodiment includes: a first initialization transistor T7 and a second initialization transistor T4. The first initialization transistor T7 is used to transmit a first initialization voltage to the anode of the light-emitting element D1 of the pixel circuit 1, and the second initialization transistor T4 is used to transmit a second initialization voltage to the gate of the driving transistor T1 of the pixel circuit 1. The vias include a first via N1 and a second via N2. The first initialization transistors T7 of two adjacent columns of the pixel circuit 1 located in the same row share the first via N1, and the second initialization transistors T4 of two adjacent columns of the pixel circuit 1 located in the same row share the second via N2.

[0054] Specifically, in combination Figures 1 to 3The pixel circuit 1 may include a driving transistor T1, a first initialization transistor T7, a second initialization transistor T4, a third transistor T2, a fourth transistor T5, a fifth transistor T6, a sixth transistor T3, and a storage capacitor Cst. The first initialization transistor T7 is electrically connected to the anode of the light-emitting element D1 of the pixel circuit 1. The first terminal of the first initialization transistor T7 is connected to the second initialization line Vref2. The first initialization transistor T7 transmits a second initialization voltage to the anode of the pixel circuit 1 to initialize the anode of the light-emitting element D1. The first terminal of the second initialization transistor T4 is connected to the gate of the driving transistor T1 of the pixel circuit 1. The second terminal of the second initialization transistor T4 is connected to the first initialization line Vref1. The second initialization transistor T4 is used to transmit a first initialization voltage to the gate of the driving transistor T1 of the pixel circuit 1 to initialize the gate of the driving transistor T1.

[0055] By configuring the first initialization transistors T7 of two adjacent columns of pixel circuit 1 located in the same row to share a first via N1, the first initialization transistors T7 of two adjacent columns of pixel circuit 1 located in the same row are all connected to the second initialization line Vref2 through the first via N1. By configuring the second initialization transistors T4 of two adjacent columns of pixel circuit 1 located in the same row to share a second via N2, the second initialization transistors T4 of two adjacent columns of pixel circuit 1 located in the same row are all connected to the first initialization line Vref1 through the second via N2. This configuration reduces the number of vias connected to the initialization line Vref, thereby reducing the number of initialization lines Vref. Since the initialization line Vref is generally an opaque metal trace, reducing the number of initialization lines Vref with poor light transmittance can reduce the number of initialization lines Vref with poor light transmittance, thereby improving the light transmittance of pixel circuit 1 and thus improving the light transmittance of the display panel.

[0056] In one optional implementation, the first initialization transistors T7 of the (2n-1)th column pixel circuit 1 and the 2nth column pixel circuit 1 located in the same row can share a first via N1, or the first initialization transistors T7 of the 2nth column pixel circuit 1 and the 2n+1th column pixel circuit 1 located in the same row can share a first via N1. The second initialization transistors T4 of the (2n-1)th column pixel circuit 1 and the 2nth column pixel circuit 1 located in the same row can share a second via N2, or the second initialization transistors T4 of the 2nth column pixel circuit 1 and the 2n+1th column pixel circuit 1 located in the same row can share a second via N2.

[0057] Optionally, based on the above embodiments, see also... Figure 3The first initialization transistor T7 of the (2n-1)th column pixel circuit 1 and the 2nth column pixel circuit 1 in the same row share the first via N1; the second initialization transistor T4 of the (2n-1)th column pixel circuit 1 and the 2nth column pixel circuit 1 in the same row share the second via N2; where n is an integer greater than 0.

[0058] Specifically, this configuration ensures that the first initialization transistors T7 of the (2n-1)th and 2nth column pixel circuits 1 in the same row are connected to the initialization line through the same first via N1, and the second initialization transistors T4 of the (2n-1)th and 2nth column pixel circuits 1 in the same row are connected to the initialization line through the same second via N2. This configuration reduces the number of vias connected to the initialization line Vref from the first to the 2nth column pixel circuits 1, further reducing the number of initialization lines Vref with poor light transmittance, thereby improving the light transmittance of the pixel circuits 1 and further improving the light transmittance of the display panel.

[0059] Optional, Figure 4 This is a schematic diagram of the active layer of a display panel according to an embodiment of the present invention. Based on the above embodiment, see... Figure 4 The pixel circuit 1 provided in this embodiment includes an active layer; along the column direction, the active layers of two adjacent columns of pixel circuit 1 are mirror-symmetrical about the axis of symmetry; preferably, the second via N2 of the second initialization transistor T4 located in two adjacent columns of pixel circuit 1 is asymmetrically arranged about the axis of symmetry.

[0060] Specifically, the active layer material can include amorphous silicon (a-Si), polycrystalline silicon (P-Si), organic semiconductor materials, or undoped metal oxides, etc. Along the column direction, the active layers of adjacent columns of pixel circuits 1 are mirror-symmetrical. This mirror symmetry ensures that the positions of each switching transistor, driving transistor T1, and storage capacitor in pixel circuit 1 are symmetrically arranged. This facilitates setting the first initialization transistor T7 of the (2n-1)th and 2nth column pixel circuits 1 in the same row as a shared first via N1, and the second initialization transistor T4 of the (2n-1)th and 2nth column pixel circuits 1 in the same row as a shared second via N2.

[0061] Preferably, the second vias N2 of the second initialization transistors T4 in two adjacent columns of pixel circuit 1 are asymmetrically arranged with respect to the axis of symmetry of the active layer of the two adjacent columns of pixel circuit 1. That is, the second vias N2 of the second initialization transistors T4 in two adjacent columns of pixel circuit 1 are not located on the axis of symmetry of the active layer of the two adjacent columns of pixel circuit 1. The second vias N2 of the second initialization transistors T4 in the (2n-1)th column of pixel circuit 1 in the same row can be shared with the second vias N2 of the second initialization transistors T4 in the 2nth column of pixel circuit 1, and both can be located near the gate of the second initialization transistors T4 in the (2n-1)th column of pixel circuit 1, or both can be located near the gate of the second initialization transistors T4 in the 2nth column of pixel circuit 1. This facilitates connecting the second initialization transistors T4 in the (2n-1)th column of pixel circuit 1 in the same row and the second initialization transistors T4 in the 2nth column of pixel circuit 1 to the same initialization line through the shared second vias N2, and facilitates reserving sufficient space to set up the first power line VSS extending along the column direction.

[0062] Optionally, based on the above embodiments, see also... Figure 3 and Figure 4 The initialization line provided in this embodiment may include: at least one first initialization line Vref1 extending along the column direction and at least one first initialization line Vref1 extending along the row direction; the first initialization line Vref1 extending along the column direction and the first initialization line Vref1 extending along the row direction are connected through a third via N3; the first initialization line Vref1 extending along the column direction is connected through a second via N2 to the second initialization transistor T4 of the pixel circuit 1 located in two adjacent columns, respectively, for transmitting a first initialization voltage to the second initialization transistor T4 of the pixel circuit 1 located in two adjacent columns.

[0063] Specifically, the third via N3 can be set at the intersection of the first initialization line Vref1 extending along the column direction and the first initialization line Vref1 extending along the row direction. This facilitates the connection between the first initialization line Vref1 extending along the column direction and the first initialization line Vref1 extending along the row direction through the third via N3. It also saves the size of the connection trace between the first initialization line Vref1 extending along the column direction and the first initialization line Vref1 extending along the row direction, further improving the light transmittance of the display panel.

[0064] The first initialization line Vref1, extending along the column direction, is connected to the second initialization transistor T4 of the pixel circuit 1 located in two adjacent columns through the second via N2, so that the pixel circuit 1 located in two adjacent columns shares a first initialization line Vref1, and the first initialization line Vref1 transmits the first initialization voltage to the second initialization transistor T4 of the pixel circuit 1 located in two adjacent columns.

[0065] Optionally, based on the above embodiments, see also... Figure 3 and Figure 4 The initialization line Vref provided in this embodiment may further include: at least one second initialization line Vref2 extending along the column direction and at least one second initialization line Vref2 extending along the row direction; the second initialization line Vref2 extending along the column direction and the second initialization line Vref2 extending along the row direction are connected through a fourth via N4; the second initialization line Vref2 extending along the column direction is connected through a first via N1 to the first initialization transistor T7 of the pixel circuit 1 located in two adjacent columns, respectively, for transmitting a second initialization voltage to the first initialization transistor T7 of the pixel circuit 1 located in two adjacent columns.

[0066] Specifically, the fourth via N4 can be set at the intersection of the second initialization line Vref2 extending along the column direction and the second initialization line Vref2 extending along the row direction. This facilitates the connection between the second initialization line Vref2 extending along the column direction and the second initialization line Vref2 extending along the row direction through the fourth via N4. It also saves the size of the connection trace between the second initialization line Vref2 extending along the column direction and the second initialization line Vref2 extending along the row direction, further improving the light transmittance of the display panel.

[0067] The second initialization line Vref2, extending along the column direction, is connected to the first initialization transistor T7 of the pixel circuit 1 located in two adjacent columns through the first via N1, so that the pixel circuit 1 located in two adjacent columns shares a second initialization line Vref2, and the second initialization line Vref2 transmits the second initialization voltage to the first initialization transistor T7 of the pixel circuit 1 located in two adjacent columns.

[0068] Optionally, based on the above embodiments, see also... Figure 3 and Figure 4 In this embodiment, the display panel shares a first initialization line Vref1 extending along the row direction for every two adjacent rows of pixel circuits 1, and shares a second initialization line Vref2 extending along the row direction for every two adjacent rows of pixel circuits 1; preferably, the pixel circuits 1 in the 2m-1th row and the pixel circuits 1 in the 2mth row share the same second initialization line Vref2 extending along the row direction, and the pixel circuits 1 in the 2mth row and the pixel circuits 1 in the 2m+1th row share the same first initialization line Vref1 extending along the row direction; where m is an integer greater than 0.

[0069] Specifically, each pair of adjacent rows of pixel circuits 1 shares a first initialization line Vref1 extending along the row direction, and each pair of adjacent rows of pixel circuits 1 shares a second initialization line Vref2 extending along the row direction. Specifically, the first initialization lines Vref1 and second initialization lines Vref2 extending along the row direction are arranged alternately from top to bottom along the column direction. This arrangement reduces the number of first initialization lines Vref1 and second initialization lines Vref2 extending along the row direction connected to the pixel circuits 1. Since the first initialization lines Vref1 and second initialization lines Vref2 are opaque metal traces, reducing the number of first initialization lines Vref1 and second initialization lines Vref2 with poor light transmittance can reduce the number of such lines, thereby further improving the light transmittance of the pixel circuits 1 and further improving the light transmittance of the display panel.

[0070] Preferably, the pixel circuit 1 in row 2m-1 shares the same second initialization line Vref2 extending along the row direction with the pixel circuit 1 in row 2m-1, and the pixel circuit 1 in row 2m+1 shares the same first initialization line Vref1 extending along the row direction with the pixel circuit 1 in row 2m+1. This arrangement ensures that the first initialization line Vref1 and the second initialization line Vref2 extending along the row direction are shared equally by the two rows of pixel circuit 1.

[0071] Optional, Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 5 The display panel provided in this embodiment may further include: a first power line VSS and a second power line VDD, wherein the power supply voltage transmitted by the second power line VDD is greater than the power supply voltage transmitted by the first power line VSS; the first power line VSS extends along the column direction; two adjacent columns of pixel circuits 1 share one first power line VSS; each row of pixel circuits 1 is correspondingly provided with two second power lines VDD extending along the row direction (not shown in the figure); preferably, the first power line VSS is arranged parallel to the initialization line extending along the column direction.

[0072] Specifically, the first power line VSS extends along the column direction, and two adjacent columns of pixel circuits 1 share one first power line VSS. On the one hand, extending the first power line VSS to the display area of ​​the display panel can effectively reduce the voltage drop of the first power line VSS, thereby reducing the power consumption of the display panel. On the other hand, this arrangement also allows two adjacent columns of pixel circuits 1 to share one first power line VSS, thereby reducing the number of first power lines VSS and further improving the light transmittance of the display panel.

[0073] Each row of pixel circuit 1 is provided with two second power lines VDD extending along the row direction. This allows each row of pixel circuit 1 to be provided with two second power lines VDD extending along the row direction, which can effectively improve the voltage drop on the second power lines VDD, thereby improving the uniformity of the first voltage signal transmitted on each pixel circuit 1, and thus improving the brightness uniformity of the display panel.

[0074] Optionally, the light-transmitting area of ​​the display panel is greater than 25%. Specifically, this setting results in a higher light-transmitting area of ​​the display panel, which can better meet the light transmittance requirements of optical devices installed under the display panel.

[0075] Optionally, the display panel may include a substrate, with an active layer disposed on one side of the substrate. The display panel further includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially disposed on the side of the active layer away from the substrate. The gate of the driving transistor T1 may be disposed on the first metal layer. The storage capacitor Cst may be disposed on the second metal layer, and the source and drain of the switching transistor may be disposed on the third metal layer. The first initialization line Vref1 and the second initialization line Vref2 extending along the row direction may be disposed on the second metal layer, and the first initialization line Vref1 and the second initialization line Vref2 extending along the column direction may be disposed on the third metal layer. The second power line VDD extending along the row direction may be disposed on the second metal layer, and the first power line VSS extending along the column direction may be disposed on the third metal layer. The second power line VDD extending along the column direction may be disposed on the fourth metal layer, and the data line may be disposed on the fourth metal layer.

[0076] The fourth metal layer of the pixel circuits located in adjacent columns can be arranged with a mirror-symmetric pattern, which can improve the flatness of the fourth metal layer. An anode layer can be placed on the side of the fourth metal layer away from the substrate, thereby improving the flatness of the anode, which in turn improves the color and thus the display effect of the display panel.

[0077] Figure 6 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. See also: Figure 6 This invention provides a display device 200, including the display panel 100 described in any of the above embodiments, and possesses the beneficial effects of the display panel 100 described in any of the above embodiments, which will not be repeated here. The display device 200 provided in this invention can include terminals such as mobile phones, tablet computers, and wearable devices.

[0078] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: At least two pixel circuits, wherein the pixel circuits are arranged in an array; Each of the pixel circuits includes an initialization transistor for initializing the pixel circuit; An initialization line is connected to the initialization transistor and is used to provide an initialization voltage to the initialization transistor. The initialization transistors of two adjacent columns of pixel circuits are connected to the same initialization line extending along the column direction; The initialization transistors of two adjacent columns of pixel circuits located in the same row share the same via and are connected to the initialization line; The initialization transistor includes a first initialization transistor and a second initialization transistor, wherein the first initialization transistor is used to transmit a second initialization voltage to the anode of the light-emitting element of the pixel circuit, and the second initialization transistor is used to transmit a first initialization voltage to the gate of the driving transistor of the pixel circuit; the via includes a first via and a second via. The first initialization transistors of two adjacent columns of the pixel circuits located in the same row share the first via, and the second initialization transistors of two adjacent columns of the pixel circuits located in the same row share the second via.

2. The display panel according to claim 1, characterized in that, The pixel circuit in the (2n-1)th column of the same row shares the first via with the first initialization transistor of the pixel circuit in the 2nth column; The second initialization transistor of the pixel circuit located in the (2n-1)th column of the same row shares the second via with the second initialization transistor of the pixel circuit located in the 2nth column; where n is an integer greater than 0.

3. The display panel according to claim 1, characterized in that, The pixel circuit includes an active layer; Along the column direction, the active layers of adjacent two column pixel circuits are mirror-symmetric about the axis of symmetry.

4. The display panel according to claim 3, characterized in that, The second via of the second initialization transistor of the pixel circuit located in two adjacent columns is asymmetrically arranged with respect to the axis of symmetry.

5. The display panel according to claim 1, characterized in that, The initialization line includes: At least one first initialization line extending along the column direction and at least one first initialization line extending along the row direction; the first initialization line extending along the column direction and the first initialization line extending along the row direction are connected by a third via; The first initialization line extending along the column direction is connected to the second initialization transistors of the pixel circuits located in two adjacent columns through the second via, for transmitting a first initialization voltage to the second initialization transistors of the pixel circuits located in two adjacent columns.

6. The display panel according to claim 5, characterized in that, The initialization line also includes: At least one second initialization line extending along the column direction and at least one second initialization line extending along the row direction; the second initialization line extending along the column direction and the second initialization line extending along the row direction are connected by a fourth via; The second initialization line extending along the column direction is connected to the first initialization transistors of the pixel circuits located in two adjacent columns through the first via, for transmitting a second initialization voltage to the first initialization transistors of the pixel circuits located in two adjacent columns.

7. The display panel according to claim 6, characterized in that, Each pair of adjacent rows of pixel circuits shares a first initialization line extending along the row direction, and each pair of adjacent rows of pixel circuits shares a second initialization line extending along the row direction.

8. The display panel according to claim 7, characterized in that, The pixel circuits in row 2m-1 and row 2m share the same second initialization line extending along the row direction, and the pixel circuits in row 2m and row 2m+1 share the same first initialization line extending along the row direction; where m is an integer greater than 0.

9. The display panel according to claim 1, characterized in that, The display panel further includes: A first power line and a second power line, wherein the power voltage transmitted by the second power line is greater than the power voltage transmitted by the first power line. The first power line extends along the column direction; two adjacent columns of pixel circuits share one first power line.

10. The display panel according to claim 9, characterized in that, Each row of pixel circuits is provided with two second power lines extending along the row direction.

11. The display panel according to claim 9, characterized in that, The first power line is arranged parallel to the initialization line extending along the column direction.

12. The display panel according to claim 1, characterized in that, The light-transmitting area of ​​the display panel is greater than 25%.

13. A display device, characterized in that, include: The display panel according to any one of claims 1 to 12.

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