Memory chip and memory system

Abstract

Embodiments of the present disclosure provide a storage chip and a storage system. The storage chip is configured such that characterization parameters representing the process corner of the storage chip are stored therein, and a reference voltage with an adjustable magnitude is further provided therein. The magnitude of the reference voltage is adjustable based on the characterization parameters, and the storage chip adjusts the delay of data read from a storage unit to output from a data port based on the reference voltage. Embodiments of the present disclosure are beneficial to improving the neatness of data signal transmission and preventing data conflicts.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a memory chip and a memory system. Background Art

[0002] Semiconductor memory can be divided into non-volatile memory and volatile memory. As a volatile memory, Dynamic Random Access Memory (DRAM) has the advantages of high storage density, fast read and write speed, etc., and is widely used in various electronic systems.

[0003] A DRAM system usually consists of a controller and multiple memory chips. Due to differences in manufacturing processes and the like, the performance of different memory chips also has corresponding differences, which will affect the overall performance of the DRAM system. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory chip and a memory system to improve the problem of data signal transmission conflict in the memory system.

[0005] According to some embodiments, on the one hand, an embodiment of the present disclosure provides a memory chip applied to a memory system. The memory chip is configured to store a characterization parameter representing the process corner of the memory chip therein, and also has an adjustable reference voltage therein. The magnitude of the reference voltage is adjustable based on the characterization parameter, and the memory chip adjusts the delay of data read from the memory cell to output from the data port based on the reference voltage.

[0006] In some embodiments, the data has a read path, and the read path includes the process of data being read from the memory cell to being output from the data port. The data transmitted on the read path is defined as intermediate data. The memory chip includes: a delay module disposed on the read path, with an input end receiving the intermediate data, a control end receiving the reference voltage, and an output end outputting the intermediate data based on the reference voltage. The length of the delay from receiving the intermediate data to outputting the intermediate data by the delay module corresponds to the magnitude of the reference voltage; an adjustment module, with an output end connected to the control end of the delay module, an input end receiving a preset reference voltage, a control end receiving a control signal, and an output end outputting the adjustable reference voltage based on the control signal and the preset reference voltage.

[0007] In some embodiments, the adjustment module includes: an operational amplifier, the positive input terminal of the operational amplifier receives the preset reference voltage; an adjustment unit, the adjustment unit is connected to the negative input terminal and the output terminal of the operational amplifier, the output terminal of the adjustment unit outputs the reference voltage, and further based on the control signal, adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, or adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal.

[0008] In some embodiments, the adjustment unit includes: N first resistors connected in series between the negative input terminal and the output terminal of the operational amplifier, N is an integer greater than 1, at least one second resistor, the second resistor is connected between the negative input terminal and the ground terminal; M first switches, the first switches connect the output terminal of the adjustment unit and one end of the corresponding first resistor, and the first switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, M is a positive integer less than or equal to N.

[0009] In some embodiments, the adjustment unit includes: X second resistors connected in series between the negative input terminal and the ground terminal, X is a positive integer greater than 1; Y second switches, the second switches connect the output terminal of the adjustment unit and one end of the corresponding second resistor, and the second switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal, Y is a positive integer less than or equal to X.

[0010] In some embodiments, the delay module includes: an even number of inverters connected in sequence, the power supply terminals of the inverters are connected to the reference voltage, the input terminal of the inverter at the first position receives the intermediate data, and the output terminal of the inverter at the last position outputs the intermediate data.

[0011] In some embodiments, the storage chip includes: a non-volatile storage module, and the non-volatile storage module is used to store the characterization parameters.

[0012] In some embodiments, the non-volatile storage module includes a one-time programmable storage unit.

[0013] In some embodiments, the storage chip further includes: a scan chain interface, and the scan chain interface is configured to obtain the characterization parameters based on a command signal issued by a controller and output the characterization parameters to the controller.

[0014] According to some embodiments, on the other hand, an embodiment of the present disclosure further provides a storage system, including the storage chip provided in any of the above embodiments; a controller configured to obtain the characterization parameter of the storage chip and adjust the magnitude of the reference voltage of the storage chip corresponding to the characterization parameter based on the characterization parameter.

[0015] In some embodiments, the data has a read path, which includes the process of the data being read out from the storage unit to being output from the data port. The data transmitted on the read path is defined as intermediate data; the storage chip includes: a delay module provided on the read path, with an input end receiving the intermediate data, a control end receiving the reference voltage, and an output end outputting the intermediate data based on the reference voltage. The length of the delay from the delay module receiving the intermediate data to outputting the intermediate data corresponds to the magnitude of the reference voltage; an adjustment module, with an output end connected to the control end of the delay module, an input end receiving a preset reference voltage, a control end receiving a control signal, and an output end outputting an adjustable reference voltage based on the control signal and the preset reference voltage; the controller is connected to the control end of the adjustment module, and the controller is configured to obtain the characterization parameter and generate the control signal based on the characterization parameter.

[0016] In some embodiments, the adjustment module includes: an operational amplifier, with a positive input end receiving the preset reference voltage; an adjustment unit connected to the negative input end and the output end of the operational amplifier, with the output end of the adjustment unit outputting the reference voltage and further adjusting the magnitude of the equivalent resistance between the output end of the adjustment unit and the output end of the operational amplifier, or adjusting the magnitude of the equivalent resistance between the output end of the adjustment unit and the ground end based on the control signal; the controller is connected to the adjustment unit and provides the control signal to the adjustment unit.

[0017] In some embodiments, the adjustment unit includes: N first resistors connected in series between the negative input end and the output end of the operational amplifier, where N is an integer greater than 1, at least one second resistor connected between the negative input end and the ground end; M first switches, with the first switches connecting the output end of the adjustment unit and one end of the corresponding first resistor, and the first switches selectively conducting based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the adjustment unit and the output end of the operational amplifier, where M is a positive integer less than or equal to N; the controller is connected to the M first switches.

[0018] In some embodiments, the adjustment unit includes: X second resistors connected in series between the negative input terminal and the ground terminal, where X is a positive integer greater than 1; Y second switches, the second switches being connected to the output terminal of the adjustment unit and one end of the corresponding second resistor, the second switches being selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal, where Y is a positive integer less than or equal to X; and the controller is connected to the Y second switches.

[0019] In some embodiments, the controller is configured to generate the control signal for controlling the reference voltage to be less than the standard reference voltage if the characterization parameter characterizes the fast process corner, and generate the control signal for controlling the reference voltage to be greater than the standard reference voltage if the characterization parameter characterizes the slow process corner.

[0020] In some embodiments, the memory chip further includes: a scan chain interface configured to obtain the characterization parameter based on a command signal issued by the controller and output the characterization parameter to the controller; the controller further includes: a parameter acquisition module configured to issue the command signal to the scan chain interface and receive the characterization parameter output by the scan chain interface.

[0021] In some embodiments, the memory chip includes: a non-volatile storage module; the memory chip is configured to obtain the characterization parameter and store the characterization parameter in the non-volatile storage module before being packaged with the controller.

[0022] In some embodiments, the controller is configured to, after each startup of the storage system, obtain the characterization parameter of each memory chip and adjust the magnitude of the reference voltage of the memory chip corresponding to the characterization parameter until polling to obtain the characterization parameters of all the memory chips and adjusting the magnitudes of the reference voltages of all the memory chips.

[0023] In some embodiments, a plurality of the memory chips are stacked on the surface of the controller in sequence; alternatively, the storage system further includes: a carrier substrate, the controller is located on the surface of the carrier substrate, and a plurality of the memory chips are stacked on the surface of the carrier substrate in sequence.

[0024] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0025] In the technical solution provided by the embodiments of the present disclosure, since the reference voltage is adjustable based on the characterization parameter, if the characterization parameter indicates that the process corner of the memory chip is a slow process corner, the reference voltage of the memory chip is adjusted to be larger than that of the memory chip with a faster process corner, so as to shorten the delay of the data of the memory chip with the slow process corner. In this way, the reference voltages of different memory chips are compensated based on their different process corners, so that the data transmission delays of different memory chips will meet the expectations, improving the neatness of the data signals, preventing the problem of data transmission conflicts between different memory chips, and improving the read and write performance of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0027] Figure 1 It is a schematic structural diagram of a memory system;

[0028] Figure 2 is Figure 1 a schematic diagram of data transmission in the provided memory system;

[0029] Figure 3 It is a schematic structural diagram of a memory chip provided by an embodiment of the present disclosure;

[0030] Figure 4 It is a schematic structural diagram of an adjustment module in the memory chip provided by an embodiment of the present disclosure;

[0031] Figure 5 It is a schematic circuit diagram of an adjustment module in the memory chip provided by an embodiment of the present disclosure;

[0032] Figure 6 It is another schematic circuit diagram of an adjustment module in the memory chip provided by an embodiment of the present disclosure;

[0033] Figure 7 It is still another schematic circuit diagram of an adjustment module in the memory chip provided by an embodiment of the present disclosure;

[0034] Figure 8 It is a schematic circuit diagram of a delay module in the memory chip provided by an embodiment of the present disclosure;

[0035] Figure 9 It is a schematic structural diagram of a memory system provided by an embodiment of the present disclosure;

[0036] Figure 10 It is a schematic functional module diagram of a memory chip and a controller in the memory system provided by an embodiment of the present disclosure;

[0037] Figure 11 Structural schematic diagrams of an adjustment module and a controller of a storage system provided by an embodiment of the present disclosure;

[0038] Figure 12 Another structural schematic diagram of a storage system provided by an embodiment of the present disclosure. Detailed implementation manners

[0039] Figure 1 It is a structural schematic diagram of a storage system, Figure 2 is Figure 1 a schematic diagram of data transmission in the provided storage system. Refer to Figure 1 , the storage system may include: a controller 13; a plurality of storage chips 12 stacked on the surface of the controller 13, and the storage chips 12 may be DRAM chips.

[0040] Due to process differences among different storage chips 12, the electrical performances exhibited by different storage chips 12 are also different. For example, the threshold voltages or conduction currents of transistors in different storage chips 12 are different, resulting in different data transmission delays inside different storage chips 12. This will cause the data signals received by the controller 13 from different storage chips 12 to be non-uniform (skew), the levels of different data signals to be inconsistent, and data signal conflicts to exist among different storage chips 12, affecting the overall performance of the storage system. Specifically, refer to Figure 2 , Figure 2 In Example 1 in, it is an ideal transmission schematic diagram of data signals corresponding to two storage chips 12, where DQ1 and DQ2 are data signals respectively corresponding to different storage chips 12 transmitted to the controller 13, Figure 2 In Example 2 in, it is an actual transmission example diagram of data signals corresponding to two storage chips 12. DQ1 corresponds to a storage chip 12 with a slow process corner, and DQ2 corresponds to a storage chip 12 with a fast process corner. During the actual transmission process, the data of DQ2 has started to be transmitted before the data of DQ1 is completely transmitted, which causes a data conflict (data confliction) between DQ1 and DQ2, resulting in a deterioration of the storage performance of the storage system.

[0041] Based on this, an embodiment of the present disclosure provides a storage chip. The storage chip is applied to a storage system, and a reference voltage for controlling data transmission delay in the storage chip is adjustable based on a characterization parameter characterizing the process corner, so as to improve the data conflict problem of the storage system, improve the alignment neatness of data signals, and further improve the read and write performance of the storage system.

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0043] Figure 3 FIG. is a schematic structural diagram of a storage chip provided by an embodiment of the present disclosure.

[0044] Referring to Figure 3 , the storage chip 100 provided by an embodiment of the present disclosure is applied to a storage system and includes: the storage chip 100 is configured such that the storage chip 100 stores characterization parameters representing the process corner of the storage chip 100, and the storage chip 100 further has a reference voltage V with adjustable magnitude ref , the magnitude of the reference voltage V ref is adjustable based on the characterization parameters, and the storage chip 100 adjusts the delay of data read from the storage unit 10 to output from the data port DQ based on the reference voltage V ref .

[0045] The reference voltage V ref is related to the delay of data read from the storage unit 10 to output from the data port DQ. Specifically, for the same storage chip 100 or the same storage chip 100 with the same process corner, the larger the reference voltage V ref , the smaller the delay of data read from the storage unit 10 to output from the data port DQ. That is to say, different storage chips 100 have the problem of different chip delays due to different process corners. The storage chip 100 with a slow process corner has a larger delay itself, and the storage chip 100 with a fast process corner has a smaller delay itself. In the embodiments of the present disclosure, since the reference voltage V ref is adjustable based on the characterization parameters, the delay can be compensated based on the process corner of the storage chip 100 to improve the delay consistency of each storage chip 100. Specifically, if the characterization parameters represent that the process corner of the storage chip 100 is a slow process corner, the reference voltage V ref of the storage chip 100 is increased to shorten the delay of the data of the storage chip 100 with a slow process corner; if the characterization parameters represent that the process corner of the storage chip 100 is a fast process corner, the reference voltage V ref, so as to extend the delay of the data of the storage chip 100 with a fast process corner. In this way, different storage chips 100 perform corresponding compensation on the reference voltage based on the process corner, so that the actual delays of the storage chips 100 tend to be the same or exactly the same. In this way, the data transmission delays of different storage chips 100 will meet the expectations, improve the neatness of data signals, prevent data transmission conflict problems of different storage chips 100, and improve the read and write performance of the storage system.

[0046] The storage chip 100 provided by the embodiments of the present disclosure will be described in more detail below with reference to the drawings.

[0047] In some embodiments, the storage chip 100 may be a DRAM storage chip, such as a DDR (double data rate) 4 DRAM storage chip or a DDR5 DRAM storage chip. In other embodiments, the storage chip 100 may also be an SRAM (Static Random-Access Memory) storage chip, a NAND storage chip, a NOR storage chip, a FeRAM storage chip, or a PcRAM storage chip.

[0048] The design of the storage chip 100 needs to meet conditions such as process corner, voltage, and temperature. The combination formed by the process corner, voltage, and temperature is called PVT (process, voltage, temperature) condition.

[0049] In some embodiments, if a 5-process corner model is adopted, the process corners of different storage chips 100 can be divided into TT (typical nmos and typical pmos) process corners, FF (fast nmos and fast pmos) process corners, SS (slow nmos and slow pmos) process corners, FS (fast nmos and slow pmos) process corners, and SF (slow nmos and fast pmos) process corners. Among them, Typical means that the drive current is an average value, Fast means that the drive current is its maximum value, and Slow means that the drive current is its minimum value (this drive current is the Ids current). This is an explanation from the measurement perspective. Typical, Fast, and Slow can also be understood as the speed of carrier mobility. Carrier mobility refers to the average drift velocity of carriers under the action of a unit electric field.

[0050] The characterization parameter can be a binary value. In some embodiments, if there are three types of process corners, the corresponding relationship between the characterization parameter and the process corner can be as shown in Table 1:

[0051] Process corner Characterization parameter SS 01 TT 00 FF 10

[0052] Table 1

[0053] In some other embodiments, if there are five types of process corners, the corresponding relationship between the characterization parameters and the process corners can be as shown in Table 2:

[0054] Process corner Characterization parameter SS 000 TT 001 SF 010 FS 011 FF 100

[0055] Table 2

[0056] Reference Figure 3 , the memory chip 100 may include a non-volatile memory module 110 for storing the characterization parameters. By using the non-volatile memory module 110 to store the characterization parameters, in this way, even if the memory chip 100 is powered on or off, the ability of the memory chip 100 to store the characterization parameters remains unchanged.

[0057] In some embodiments, the non-volatile memory module 110 may include one-time programmable storage units (OTP, OneTime Programable). In some other embodiments, the non-volatile memory module 110 may also be a programmable read-only memory (PROM, Programmable read-only memory) unit or an electrically erasable programmable read-only memory (EEPROM, Electrically erasable programmable read only memory).

[0058] It can be understood that after the memory chip 100 is designed and manufactured, the process corners of the memory chip 100 can be detected, and the characterization parameters of the detected process corners can be stored in the non-volatile memory module 110 of the memory chip 100. Specifically, before the memory wafer is cut to obtain discrete memory chips 100, the process corners can be detected and the characterization parameters can be stored in the non-volatile memory module 110 of each memory chip 100; or, after the memory wafer is cut to obtain discrete memory chips 100, the process corners can be detected and the characterization parameters can be stored in the non-volatile memory module 110 of each memory chip 100.

[0059] In some embodiments, the data has a readout path, and the readout path includes the process of data being read out from the storage unit 10 to being output from the data port DQ. The data transmitted on the readout path is defined as intermediate data; the memory chip 100 includes: a delay module 101, which is arranged on the readout path, receives the intermediate data at the input end, and receives the reference voltage V at the control end ref, and the output terminal is based on the reference voltage V ref Output intermediate data, and the length of the delay of the delay module 101 from receiving the intermediate data to outputting the intermediate data corresponds to the magnitude of the reference voltage V ref Adjustment module 102, the output terminal of the adjustment module 102 is connected to the control terminal of the delay module 101, the input terminal receives the preset reference voltage V R , the control terminal receives the control signal Con, and the output terminal outputs an adjustable reference voltage V R based on the control signal Con and the preset reference voltage V ref .

[0060] Through the delay module 101, the delay of the data can be controlled on any transmission path on the data read path, making the design of the memory chip 100 more flexible; through the adjustment module 102, an adjustable reference voltage V R can be output based on the preset reference voltage V ref and the control signal Con. The preset reference voltage V R can be the preset reference voltage specified in the user manual of the memory chip 100, that is, the preset reference voltage can be the voltage value designed for the memory chip 100 under ideal conditions.

[0061] Specifically, there can be a driving module, a buffer module, a latch module, etc. on the data read path. The delay module 101 can be set at any position on the read path, such as before or after the driving module, before or after the buffer module, before or after the latch module, or inside the driving module, buffer module, or latch module. The control signal Con can be given by the controller of the memory system, and the control signal Con is also related to the process corner of the memory chip 102.

[0062] Figure 4 FIG. is a schematic structural diagram of an adjustment module in the memory chip provided by the embodiment of the present disclosure. Refer to Figure 4 , in some embodiments, the adjustment module 102 may include: an operational amplifier 112, and the positive input terminal of the operational amplifier 112 receives the preset reference voltage V R ; an adjustment unit 122, the adjustment unit 122 is connected to the negative input terminal and the output terminal of the operational amplifier 112, and the output terminal OUT of the adjustment unit 122 outputs the reference voltage V ref , and also based on the control signal, adjusts the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, or adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit 122 and the ground terminal.

[0063] According to the principle of "virtual short" of the operational amplifier, the voltage at the negative input terminal of the operational amplifier 112 is the same as the voltage at the positive input terminal. The adjustable reference voltage V is obtained through the structure of the operational amplifier 112 and the adjustment unit 122 ref , so that the circuit structure of the adjustment module 102 is simple, and the adjustment module 102 occupies a small area of the storage chip 100, which is beneficial to saving the chip area of the storage chip 100. Specifically, define the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal as R1, and define the equivalent resistance between the negative input terminal of the operational amplifier 112 and the ground terminal as R2. Then the reference voltage V ref and the preset reference voltage V R satisfy the following relationship:

[0064] V ref =(V R / R2)*R1 (1)

[0065] Adjusting at least one of R1 or R2 can adjust the magnitude of the reference voltage V ref . Therefore, the magnitude of R1 can be selected for adjustment, or the magnitude of R2 can be selected for adjustment, or the magnitudes of both R1 and R2 can be adjusted simultaneously to adjust the magnitude of the reference voltage V ref .

[0066] Reference Figure 5 , Figure 5 FIG. is a schematic circuit diagram of a circuit structure of the adjustment module. The adjustment unit 122 may include: N first resistors r1 connected in series between the negative input terminal and the output terminal of the operational amplifier 112, where N is an integer greater than 1, at least one second resistor r2, and the second resistor r2 is connected between the negative input terminal and the ground terminal; M first switches k1, the first switch k1 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding first resistor r1, and the first switch k1 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit 122 and the output terminal of the operational amplifier 112, and M is a positive integer less than or equal to N. N can be any natural number greater than 1 such as 2, 3, or 4, and M can be any natural number such as 1, 2, or 3

[0067] Among them, the first switch k1 can be a MOS transistor or a transmission gate. It should be noted that the resistance values of each first resistor r1 can be the same or different; the resistance values of each second resistor r2 can be the same or different. According to the different conduction conditions of the first switch k1, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 is also different

[0068] Reference Figure 5According to the principle of "virtual short" of the operational amplifier, the voltage at the negative input terminal of the operational amplifier 112 is the same as the voltage at the positive input terminal, that is, the voltage at the negative input terminal is V R , based on the voltage of the negative input terminal and the resistance from the negative input terminal to the ground terminal, the current from the negative input terminal to the ground terminal can be obtained, and the current is also the current of the path from the output terminal of the operational amplifier 112 to the ground terminal; only one of the multiple first switches k1 is turned on, and based on the different conduction conditions of the first switches k1, combined with the current and the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, the reference voltage V output by the output terminal OUT of the adjustment unit 122 can be calculated. ref For example, if the first switch k1 connected to the node connecting the first resistor r1 and the second resistor r2 is turned on, the reference voltage V outputted by the output terminal OUT of the adjustment unit 122 is ref With the preset reference voltage V R same.

[0069] In addition, the more the number of the first resistors r1 and the first switches k1 is, the greater the reference voltage V output by the adjustment module 102 is. ref The more gears there are, the more gears the data transmission delay can be adjusted to, and the more favorable it is to adjust the delay to match the required data. In the specific actual circuit, it is also necessary to consider the area of ​​the memory chip 100 occupied by the adjustment module 102. If the number of the first resistors r1 and the first switches k1 is too large, the area of ​​the memory chip 100 will also increase accordingly. To this end, the number of the first resistors r1 and the first switches k1 can be reasonably selected based on the above two requirements. Reference Figure 6 , Figure 6 Another circuit structure diagram of the adjustment module, the adjustment unit 122 includes: X second resistors r2 connected in series between the negative input terminal and the ground terminal, X is a positive integer greater than 1; Y second switches k2, the second switch k2 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding second resistor r2, the second switch k2 is selectively turned on based on the control signal Con to adjust the size of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, Y is a positive integer less than or equal to X. X can be any natural number greater than 1 such as 2, 3 or 4, and Y can be any natural number such as 1, 2 or 3.

[0070] The second switch k2 may be a MOS tube or a transmission gate. It should be noted that the resistance of each second resistor r2 may be the same or different. Depending on the conduction status of the second switch k2, the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal may also be different.

[0071] In addition, the more the number of the second resistors r2 and the second switches k2 is, the greater the reference voltage V output by the adjustment module 102 is.ref The more the number of levels of the size, the more corresponding levels can be adjusted for the delay of data transmission, which is more beneficial for adjusting to obtain the delay of data meeting the requirements. When designing a specific actual circuit, it is also necessary to consider the area of the storage chip 100 occupied by the adjustment module 102. If the number of the second resistors r2 and the second switches k2 is too large, the area of the storage chip 100 will also increase accordingly. Therefore, based on the above two requirements, the number of the second resistors r2 and the second switches k2 can be reasonably selected.

[0072] Reference Figure 6 , in some embodiments, the adjustment unit 122 may further include: at least one first resistor r1, the first resistor r1 is connected between the negative input terminal and the output terminal of the operational amplifier 112, and for the case where there are multiple first resistors r1, the multiple first resistors r1 are connected in series.

[0073] Reference Figure 6 , according to the principle of "virtual short" of the operational amplifier, the voltage of the negative input terminal of the operational amplifier 112 is the same as the voltage of the positive input terminal. For the calculation method of the output terminal OUT of the adjustment unit 122, reference can be made to the foregoing related description.

[0074] Reference Figure 7 , Figure 7 FIG. is another schematic structural diagram of the adjustment module. In some embodiments, the adjustment unit 122 may include: N first resistors r1 connected in series between the negative input terminal and the output terminal of the operational amplifier 112, where N is an integer greater than 1; M first switches k1, the first switches k1 are connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding first resistor r1, and the first switches k1 are selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, where M is a positive integer less than or equal to N; X second resistors r2 connected in series between the negative input terminal and the ground terminal, where X is a positive integer greater than 1; Y second switches k2, the second switches k2 are connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding second resistor r2, and the second switches k2 are selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, where Y is a positive integer less than or equal to X.

[0075] For the calculation method of the voltage of the output terminal OUT of the adjustment unit 122, reference can be made to the foregoing as Figure 5 and Figure 6 the related description.

[0076] Specifically, by means of the first switch k1 and the second switch k2, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 can be adjusted, and the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal can also be adjusted. In this way, it is beneficial to adjust the reference voltage V ref more flexibly, and the space for the gear positions of the reference voltage V ref is larger.

[0077] Reference Figure 8 , Figure 8 FIG. is a schematic circuit diagram of a delay module. The delay module 101 may include: an even number of inverters 111 connected in sequence. The power supply terminals of the inverters 111 are connected to the reference voltage V ref . The input terminal of the first inverter 111 receives intermediate data, and the output terminal of the last inverter 111 outputs intermediate data.

[0078] Among them, the intermediate data output by the output terminal of the last (i.e., the last-positioned) inverter 111 has a delay compared with the intermediate data received by the first (i.e., the first-positioned) inverter 111. And the magnitude of this delay is related to the delay time of each inverter 111. By adjusting the magnitude of the reference voltage V ref , the magnitude of the delay time of the inverter 111 can be adjusted, so as to finally adjust the magnitude of the delay of the intermediate data transmitted through the delay module 101, so as to achieve the purpose of changing the magnitude of the delay from when the data is read out from the storage unit to when it is output from the data port DQ. It should be noted that in some embodiments, the sizes of the inverters 111 may be the same, and the inverters 111 have the same delay characteristics; in other embodiments, the sizes of the inverters 111 may also be different, and the inverters 111 have different delay characteristics.

[0079] Using an even number of inverters 111 connected in sequence to form the delay module 101 can not only realize the function of delaying the transmission of intermediate data, but also the circuit structure of the delay module 101 is simple, occupies a small space in the chip area of the storage chip 100, and is beneficial to reducing the design difficulty of the storage chip 100 while saving the chip area.

[0080] It can be understood that in other embodiments, other suitable delay circuits may also be used as the delay module.

[0081] In some embodiments, referring to Figure 3 , the storage chip 100 may further include: a scan chain interface 103, and the scan chain interface 103 is configured to obtain characterization parameters based on a command signal issued by the controller and output the characterization parameters to the controller.

[0082] Specifically, the scan chain interface 103 can serve as a medium for transmitting signals between the controller and the non-volatile storage module 110, and the characterization parameters are transmitted to the controller via the scan chain interface 103.

[0083] In the technical solution of the storage chip 100 provided by the above embodiment, the delay of data transmitted from the storage unit to the data port can be adjusted according to the magnitude of the reference voltage. Since the magnitude of the reference voltage can be adjusted based on the process corner, the influence of different process corners on the data transmission delay can be solved, ensuring that the data transmission delay meets the expectation and preventing the problem of data signal conflict.

[0084] For example, if the characterization parameter indicates a fast process corner, the reference voltage of the corresponding storage chip 100 is reduced, so that the speed of data read from the storage unit to output from the data port becomes relatively slower, increasing the delay of data read from the storage unit to output from the data port; if the characterization parameter indicates a slow process corner, the reference voltage of the corresponding storage chip 100 is increased, so that the speed of data read from the storage unit to output from the data port becomes relatively faster, increasing the delay of data read from the storage unit to output from the data port.

[0085] Correspondingly, the embodiments of the present disclosure further provide a storage system, which includes the storage chip provided in any of the above embodiments. The storage system provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated here.

[0086] Figure 9 FIG. is a schematic structural diagram of the storage system provided by the embodiments of the present disclosure.

[0087] With reference to Figure 3 and Figure 9 , the storage system includes: a plurality of storage chips 100 provided in any of the above embodiments. The storage chip 100 is configured such that the storage chip 100 stores a characterization parameter representing the process corner of the storage chip 100, and the storage chip 100 also has an adjustable reference voltage V ref , the magnitude of the reference voltage V ref is adjustable based on the characterization parameter, and the storage chip 100 adjusts the delay of data read from the storage unit 10 to output from the data port DQ based on the reference voltage V ref ; a controller 200, which is configured to obtain the characterization parameter of the storage chip 100 and adjust the magnitude of the reference voltage V ref of the storage chip 100 corresponding to the characterization parameter.

[0088] The storage system includes multiple storage chips 100. Even though the storage system has pre-designed the delay of data read from the storage unit to output from the data port DQ for different storage chips 100, due to the problem of different process corners in the storage chips 100, there is still a problem that the delay of data read deviates from the pre-design. In the embodiments of the present disclosure, the controller 200 further obtains the process corner of each storage chip 100 and adjusts the reference voltage V of the storage chip 100 according to the characterization parameter corresponding to the process corner ref , that is, compensates the reference voltage V ref according to the process corner to adjust the delay of data read from the storage unit to output from the data port DQ of the storage chip 100, so that the actually manifested delay of data read conforms to the pre-design, avoiding the problem of data transmission conflict corresponding to different storage chips 100, and improving the storage performance of the storage system.

[0089] Figure 10 FIG. is a schematic diagram of a functional module of a storage chip and a controller. Refer to Figure 10 , in some embodiments, the data has a read path, and the read path includes the process of data read from the storage unit 10 to output from the data port DQ. The data transmitted on the read path is defined as intermediate data; the storage chip 100 includes: a delay module 101, the delay module 101 is arranged on the read path, the input end receives the intermediate data, the control end receives the reference voltage V ref , and the output end outputs the intermediate data based on the reference voltage V ref . The length of the delay from the delay module 101 receiving the intermediate data to outputting the intermediate data corresponds to the magnitude of the reference voltage V ref ; an adjustment module 102, the output end of the adjustment module 102 is connected to the control end of the delay module 101, the input end receives the preset reference voltage V R , the control end receives the control signal Con, and the output end outputs an adjustable reference voltage V R based on the control signal Con and the preset reference voltage V ref ; the controller 200 is connected to the control end of the adjustment module 102, and the controller 200 is used to obtain the characterization parameter and generate the control signal Con based on the characterization parameter.

[0090] For the relevant description of the delay module 101, reference can be made to the corresponding detailed description of the foregoing embodiments and will not be elaborated herein.

[0091] Specifically, different control signals Con correspond to different characterization parameters, different control signals correspond to different reference voltages V ref , and the controller 200 generates the corresponding control signal Con based on the characterization parameter, so that the storage chip 100 obtains the reference voltage V ref corresponding to the characterization parameter.

[0092] As Figure 11 shown Figure 11 is a schematic structural diagram of an adjustment module and a controller. In some embodiments, the adjustment module 102 may include: an operational amplifier 112, and the positive input terminal of the operational amplifier 112 receives a preset reference voltage V R ; an adjustment unit 122, the adjustment unit 122 is connected to the negative input terminal and the output terminal of the operational amplifier 112, and the output terminal OUT of the adjustment unit 122 outputs a reference voltage V ref , and further based on the control signal Con, adjusts the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, or adjusts the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal; the controller 200 is connected to the adjustment unit 122 and provides a control signal to the adjustment unit 122.

[0093] Specifically, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, and / or the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, is determined by the control signal Con issued by the controller 200.

[0094] As Figure 5 shown, in some embodiments, the adjustment unit 122 may include: N first resistors r1 connected in series between the negative input terminal and the output terminal of the operational amplifier 112, N is an integer greater than 1, at least one second resistor r2, and the second resistor r2 is connected between the negative input terminal and the ground terminal; M first switches k1, the first switches k1 are connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding first resistor r1, and the first switches k1 are selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, M is a positive integer less than or equal to N; the controller 200 is connected to the M first switches k1.

[0095] In addition, the first switch k1 is also connected between the negative input terminal of the operational amplifier 112 and the output terminal OUT of the adjustment unit 122. The first switch k1 is selectively turned on according to the control signal Con, that is, the controller 200 issues a corresponding independent control signal Con to each first switch k1 to select which first switch k1 is turned on, so as to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, and further adjust the reference voltage V ref magnitude.

[0096] Reference Figure 6, in some embodiments, the adjustment unit 122 also includes: X second resistors r2 connected in series between the negative input terminal of the operational amplifier 112 and the ground terminal, where X is a positive integer greater than 1; Y second switches k2, the second switches k2 are connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding second resistor r2, and the second switches k2 are selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, where Y is a positive integer less than or equal to X; the controller 200 is connected to the Y second switches k2.

[0097] The second switch k2 is selectively turned on according to the control signal Con, that is, the controller 200 sends a corresponding independent control signal Con to each second switch k2 to select which second switch k2 is turned on, so as to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, and further adjust the reference voltage V ref magnitude.

[0098] It can be understood that, in some embodiments, as Figure 7 shown, the adjustment unit 122 may include only one of the first switch k1 or the second switch k2. In other embodiments, the adjustment unit 122 may also include both the first switch k1 and the second switch k2.

[0099] It should also be noted that, as shown in the foregoing embodiments, regarding the design of the adjustment unit 122, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 can be adjusted only, or the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal can be adjusted only, or both the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 and the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal can be adjusted. For the specific circuit implementation, reference can be made to the description of the foregoing embodiments, and details are not described herein again.

[0100] In some embodiments, referring to Figure 9 , the storage chip 100 may include: a non-volatile storage module 110; the storage chip 100 is configured to obtain characterization parameters and store the characterization parameters in the non-volatile storage module 110 before being packaged with the controller 200.

[0101] In some embodiments, referring to Figure 9, the memory chip 100 may further include: a scan chain interface 103 configured to obtain characterization parameters based on a command signal issued by the controller 200 and output the characterization parameters to the controller 200; the controller 200 further includes: a parameter acquisition module 201 configured to issue a command signal to the scan chain interface 103 and receive the characterization parameters output by the scan chain interface 103.

[0102] Specifically, the parameter acquisition module 201 issues a command signal to the scan chain interface 103. After receiving the command signal, the scan chain interface 103 acquires the characterization parameters stored in the non-volatile storage module 110, and then the characterization parameters are transmitted to the parameter acquisition module 201 via the scan chain interface 103. After the controller 200 acquires the characterization parameters, it generates a corresponding control signal Con.

[0103] In some embodiments, the controller 200 is configured to, if the characterization parameters indicate a fast process corner, generate a control signal Con for controlling the reference voltage V ref less than the standard reference voltage, and if the characterization parameters indicate a slow process corner, generate a control signal Con for controlling the reference voltage V ref greater than the standard reference voltage.

[0104] Wherein, the standard reference voltage may be the ideal reference voltage of the pre-designed memory chip 100. Under ideal conditions, the delay of the data read from the storage unit to be transmitted to the data port of the memory chip 100 at this standard reference voltage meets the expectation. If the characterization parameters indicate a fast process corner, the control signal generated by the controller 200 can make the value of the reference voltage V ref smaller than the standard reference voltage, that is, compensate the reference voltage V ref of the memory chip 100 with a fast process corner. In this way, the delay of the data read from the storage unit to be transmitted to the data port is longer than that before compensation, which can compensate for the problem of fast transmission speed caused by the fast process corner, making the delay of the data read from the storage unit to be transmitted to the data port more in line with the expectation, that is, the delay after compensation tends to be consistent with the delay in the ideal situation (i.e., pre-designed). If the characterization parameters indicate a standard slow process corner, the control signal generated by the controller 200 can make the value of the reference voltage V ref greater than the standard reference voltage, that is, compensate the reference voltage V refCompensation is performed, so that the delay from when data is read out from the storage unit to when it is transmitted to the data port is shorter than before compensation. This can compensate for the slow transmission speed problem caused by the slow process corner, making the delay from when data is read out from the storage unit to when it is transmitted to the data port more in line with expectations, that is, the delay after compensation tends to be consistent with the delay in the ideal case. In this way, the timing of the data signals output from the data ports within different memory chips 100 will not conflict, which is beneficial to improving the performance of the memory system.

[0105] In addition, in some embodiments, if the characterization parameter characterizes the standard process corner, the reference voltage V of the corresponding memory chip 100 ref can be the same as the standard reference voltage.

[0106] In some embodiments, the controller 200 is configured to, after each startup of the memory system, obtain the characterization parameter of each memory chip 100, and adjust the reference voltage V of the memory chip 100 corresponding to the characterization parameter ref until polling to obtain the characterization parameters of all memory chips 100 and adjusting the reference voltages V of all memory chips 100 ref are completed.

[0107] The working principle of the controller 200 will be described in more detail below.

[0108] In one example, the controller 200 can adjust the reference voltage of the memory chip 100 in the following manner: perform read and write operation tests, obtain the delay from when data of each memory chip 100 is read out from the storage unit to when it is transmitted to the data port, and obtain the memory chips 100 with delays that do not meet expectations; use the memory chips 100 with delays that meet expectations as a standard, or use the memory chips 100 with the standard process corner as a standard, obtain the characterization parameters of the memory chips 100 with delays that do not meet expectations, and adjust the reference voltages of these memory chips 100. After the adjustment, the memory chips 100 are again subjected to read and write operation tests. If the delay of the data still does not meet the requirements, continue to adjust the reference voltages of the memory chips 100 until the data of the adjusted memory chips 100 meets the requirements.

[0109] As Figure 9 shown, in some embodiments, multiple memory chips 100 are stacked on the surface of the controller 200 in sequence, and the memory system is a 3D stacked structure. Figure 12 Another structural schematic diagram of the memory system provided by the embodiments of the present disclosure. In other embodiments, as Figure 12 shown, the memory system may further include: a carrier substrate 300, the controller 200 is located on the surface of the carrier substrate 300, and multiple memory chips 100 are stacked on the surface of the carrier substrate 300 in sequence, and the memory system forms a 2.5D stacked structure.

[0110] Embodiments of the present disclosure provide a storage system with superior structural performance, which can adjust the reference voltage for controlling the speed of data transmission according to the process corners of the storage chips 100, so that the delay of data transmission of each storage chip 100 meets the expectation and improves the read and write performance of the storage system.

[0111] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A storage chip, applied to a storage system, characterized in that, Including: The storage chip is configured such that characterization parameters representing the process corner of the storage chip are stored therein, and a reference voltage with adjustable magnitude is further provided in the storage chip. The magnitude of the reference voltage is adjustable based on the characterization parameters, and the storage chip adjusts the delay of data read from the storage unit to output from the data port based on the reference voltage.

2. The storage chip according to claim 1, characterized in that, The data has a read path, which includes the process of data being read from the storage unit to output from the data port. The data transmitted on the read path is defined as intermediate data. The storage chip includes: A delay module, which is arranged on the read path, receives the intermediate data at the input end, receives the reference voltage at the control end, and outputs the intermediate data at the output end based on the reference voltage. The length of the delay from receiving the intermediate data to outputting the intermediate data by the delay module corresponds to the magnitude of the reference voltage. An adjustment module, whose output end is connected to the control end of the delay module, receives a preset reference voltage at the input end, receives a control signal at the control end, and outputs the reference voltage with adjustable magnitude at the output end based on the control signal and the preset reference voltage.

3. The storage chip according to claim 2, wherein The adjustment module includes: An operational amplifier, whose positive input end receives the preset reference voltage. An adjustment unit, which is connected to the negative input end and the output end of the operational amplifier. The output end of the adjustment unit outputs the reference voltage, and further adjusts the magnitude of the equivalent resistance between the output end of the adjustment unit and the output end of the operational amplifier, or adjusts the magnitude of the equivalent resistance between the output end of the adjustment unit and the ground end, based on the control signal.

4. The storage chip according to claim 3, wherein, The adjustment unit includes: N first resistors connected in series between the negative input end and the output end of the operational amplifier, where N is an integer greater than 1, and at least one second resistor connected between the negative input end and the ground end. M first switches, where the first switch connects the output end of the adjustment unit and one end of the corresponding first resistor, and the first switch selectively conducts based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the adjustment unit and the output end of the operational amplifier, where M is a positive integer less than or equal to N.

5. The storage chip according to claim 3 or 4, characterized in that, The adjustment unit includes: X second resistors connected in series between the negative input end and the ground end, where X is a positive integer greater than 1. Y second switches, where the second switch connects the output end of the adjustment unit and one end of the corresponding second resistor, and the second switch selectively conducts based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the adjustment unit and the ground end, where Y is a positive integer less than or equal to X.

6. The storage chip according to claim 2, wherein The delay module includes: An even number of inverters connected in sequence, where the power supply terminal of the inverter is connected to the reference voltage, the input end of the first inverter receives the intermediate data, and the output end of the last inverter outputs the intermediate data.

7. The memory chip according to claim 1, wherein The storage chip includes: a non-volatile storage module for storing the characterization parameters.

8. The storage chip according to claim 7, wherein The non-volatile storage module includes one-time programmable storage cells.

9. The storage chip according to claim 1, characterized in that, The storage chip further includes: a scan chain interface configured to obtain the characterization parameters based on a command signal issued by a controller and output the characterization parameters to the controller.

10. A storage system, characterized in that, Including: A plurality of storage chips as described in any one of claims 1-9; A controller configured to obtain the characterization parameters of the storage chip and adjust the magnitude of the reference voltage of the storage chip corresponding to the characterization parameters based on the characterization parameters.

11. The storage system according to claim 10, wherein, The data has a readout path, which includes the process of the data being read out from the storage cell to being output from the data port. The data transmitted on the readout path is defined as intermediate data; the storage chip includes: A delay module provided on the readout path, having an input terminal receiving the intermediate data, a control terminal receiving the reference voltage, and an output terminal outputting the intermediate data based on the reference voltage. The length of the delay from receiving the intermediate data to outputting the intermediate data by the delay module corresponds to the magnitude of the reference voltage; An adjustment module, the output terminal of which is connected to the control terminal of the delay module, having an input terminal receiving a preset reference voltage, a control terminal receiving a control signal, and an output terminal outputting an adjustable reference voltage based on the control signal and the preset reference voltage; The controller is connected to the control terminal of the adjustment module, and the controller is used to obtain the characterization parameters and generate the control signal based on the characterization parameters.

12. The storage system according to claim 11, wherein The adjustment module includes: An operational amplifier, the positive input terminal of which receives the preset reference voltage; An adjustment unit connected to the negative input terminal and the output terminal of the operational amplifier. The output terminal of the adjustment unit outputs the reference voltage and also adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier or adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal based on the control signal; The controller is connected to the adjustment unit and provides the control signal to the adjustment unit.

13. The storage system according to claim 12, wherein The adjustment unit includes: N first resistors connected in series between the negative input terminal and the output terminal of the operational amplifier, where N is an integer greater than 1, and at least one second resistor connected between the negative input terminal and the ground terminal; M first switches, each of which connects the output terminal of the adjustment unit and one end of the corresponding first resistor. The first switches selectively conduct based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, where M is a positive integer less than or equal to N; The controller is connected to the M first switches.

14. The storage system according to claim 12 or 13, characterized in that, The adjustment unit includes: X second resistors connected in series between the negative input terminal and the ground terminal, where X is a positive integer greater than 1; Y second switches, where the second switches are connected to the output end of the regulating unit and one end of the corresponding second resistor, and the second switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the regulating unit and the ground end, where Y is a positive integer less than or equal to X; The controller is connected to the Y second switches.

15. The storage system according to claim 10, wherein The controller is configured to generate a control signal for controlling the reference voltage to be less than the standard reference voltage if the characterization parameter characterizes a fast process corner, and generate the control signal for controlling the reference voltage to be greater than the standard reference voltage if the characterization parameter characterizes a slow process corner.

16. The storage system according to claim 10, wherein The memory chip further includes: a scan chain interface, which is configured to obtain the characterization parameter based on a command signal issued by the controller and output the characterization parameter to the controller; the controller further includes: A parameter acquisition module, which is configured to issue the command signal to the scan chain interface and receive the characterization parameter output by the scan chain interface.

17. The storage system according to claim 10, wherein The memory chip includes: a non-volatile storage module; the memory chip is configured to obtain the characterization parameter and store the characterization parameter in the non-volatile storage module before being packaged with the controller.

18. The storage system according to claim 17, wherein The controller is configured to, after each startup of the storage system, obtain the characterization parameter of each memory chip and adjust the magnitude of the reference voltage of the memory chip corresponding to the characterization parameter until the characterization parameters of all the memory chips are obtained by polling and the magnitudes of the reference voltages of all the memory chips are adjusted.

19. The storage system according to claim 10, wherein A plurality of the memory chips are stacked on the surface of the controller in sequence; or, the storage system further includes: a carrier substrate, the controller is located on the surface of the carrier substrate, and a plurality of the memory chips are stacked on the surface of the carrier substrate in sequence.

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