High-voltage release circuits, memory and electronic devices

Abstract

This application relates to the field of memory technology and discloses a high-voltage release circuit, including a control circuit, a bias current circuit, a first release circuit, and a second release circuit. The control circuit receives a positive high voltage output from the charge pump of the memory and outputs a control signal based on the positive high voltage. The bias current circuit provides a bias current to the first release circuit according to the control signal. The first release circuit releases the positive high voltage to a first preset value according to the control signal and a preset current. The second release circuit releases the positive high voltage to a second preset value when the voltage reaches the first preset value. Thus, the voltage drop of the positive high voltage is linear during the release to the first preset value, thereby improving the reliability of the memory. This application also discloses a memory and an electronic device.

Description

Technical Field

[0001] This application relates to the field of memory technology, such as a high-voltage release circuit, a memory, and an electronic device. Background Technology

[0002] In memory design, the high voltage applied during programming needs to be released after programming is complete. Figure 1 For existing high-voltage release circuits, combined with Figure 1 As shown, one end of the fourth resistor 1 is grounded, and the other end of the fourth resistor 1 is connected to one end of the fifth resistor 2 and the first input terminal of the second comparator 4; the second input terminal of the second comparator 4 is used to receive a preset reference voltage; the other end of the fifth resistor 2 is connected to the drain and gate of the eleventh NMOS transistor 5, and is used to receive the positive high voltage (HVPOS) for memory programming output by the charge pump of the memory; the source of the eleventh NMOS transistor 5 is connected to the drain of the ninth NMOS transistor 6; the gate of the ninth NMOS transistor 6 is connected to the power supply; the source of the ninth NMOS transistor 6 is connected to the drain of the tenth NMOS transistor 7; the gate of the tenth NMOS transistor 7 is connected to the output terminal of the second comparator 4; the source of the tenth NMOS transistor 7 is grounded. The power supply is VCC, and the ground is GND.

[0003] Using the existing high-voltage release circuit, HVPOS starts releasing from a relatively high voltage, for example, HVPOS is 10V and VCC is 2V. When the voltage divider signal DET of HVPOS is greater than the reference voltage VREF, the output of the second comparator is high, the tenth NMOS transistor turns on, and HVPOS releases rapidly. As the voltage value of HVPOS decreases, the release current decreases until HVPOS approaches the third preset value or falls below the fourth preset value, at which point HVPOS stops releasing. The third preset value is equal to VCC + VTH2; the fourth preset threshold value is equal to the fifth resistor / fourth resistor * VREF. VCC is the power supply voltage, VTH2 is the threshold voltage of the ninth NMOS transistor, " / " represents division, "*" represents multiplication, and "+" represents addition.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] In related technologies, the release speed of HVPOS varies depending on the HVPOS voltage value. This results in a faster release speed when HVPOS is high and a slower release speed when HVPOS is low, affecting the reliability of the memory. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] This disclosure provides a high-voltage release circuit, a memory, and an electronic device to improve the reliability of the memory.

[0008] In some embodiments, the high-voltage release circuit includes: a control circuit connected to a bias current circuit, a first release circuit, and a second release circuit; the control circuit is used to receive a positive high voltage output from the charge pump of the memory and output a control signal according to the positive high voltage; a bias current circuit connected to the first release circuit and the second release circuit; the bias current circuit is used to provide a bias current to the first release circuit according to the control signal; the first release circuit is connected to the second release circuit; the first release circuit is used to release the voltage value of the positive high voltage to a first preset value according to the control signal and a preset current; the second release circuit is used to release the voltage value of the positive high voltage to a second preset value when the voltage value of the positive high voltage reaches the first preset value.

[0009] In some embodiments, the control circuit includes: a first resistor, a second resistor, and a first comparator; one end of the first resistor is grounded, and the other end of the first resistor is connected to one end of the second resistor and the first input terminal of the first comparator; the other end of the second resistor is connected to a first release circuit and a second release circuit, and is used to receive the positive high voltage output by the charge pump of the memory; the second input terminal of the first comparator is used to receive a preset reference voltage; the output terminal of the first comparator is connected to the first release circuit, the bias current circuit, and the second release circuit.

[0010] In some embodiments, the bias current circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, and a current source; one end of the current source is connected to a power supply, and the other end of the current source is connected to the drain and gate of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to a first release circuit, and the source of the sixth NMOS transistor is connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to a control circuit, a first release circuit, and a second release circuit, and the source of the fifth NMOS transistor is grounded.

[0011] In some embodiments, the first release circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the drain and gate of the third NMOS transistor are connected to a control circuit and receive a positive high voltage output from the charge pump of the memory; the source of the third NMOS transistor is connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is connected to a power supply, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor and the second release circuit; the gate of the first NMOS transistor is connected to a bias current circuit; the source of the first NMOS transistor is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the control circuit, the bias current circuit, and the second release circuit, and the source of the fourth NMOS transistor is grounded.

[0012] In some embodiments, the high-voltage release circuit has one or more seventh NMOS transistors connected in parallel with the first NMOS transistor.

[0013] In some embodiments, the second release circuit includes: a PMOS transistor, a third resistor, an eighth NMOS transistor, and an inverter; one end of the third resistor is connected to the control circuit and receives the positive high voltage output from the charge pump of the memory; the other end of the third resistor is connected to the source of the PMOS transistor; the gate of the PMOS transistor is connected to the first release circuit; the drain of the PMOS transistor is connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor is connected to the power supply; the gate of the eighth NMOS transistor is connected to the output terminal of the inverter; the input terminal of the inverter is connected to the control circuit, the bias current circuit, and the first release circuit.

[0014] In some embodiments, the bias current circuit is used to provide a bias current to the first release circuit according to a control signal, including: when the control signal is high, the bias current circuit provides a bias current to the first release circuit.

[0015] In some embodiments, the first release circuit is used to release the positive high voltage value to a first preset value according to a preset current based on a control signal, including: when the control signal is at a high level, the first release circuit releases the positive high voltage value to the first preset value according to a preset current.

[0016] In some embodiments, the memory includes the high-voltage release circuit described above.

[0017] In some embodiments, the electronic device includes the memory described above.

[0018] The high-voltage release circuit, memory, and electronic device provided in this disclosure can achieve the following technical effects: A control circuit connects a bias current circuit, a first release circuit, and a second release circuit. The control circuit receives the positive high voltage output from the charge pump of the memory and outputs a control signal based on the positive high voltage. The bias current circuit is connected to the first release circuit and provides a bias current to the first release circuit according to the control signal. The first release circuit is connected to the second release circuit and releases the positive high voltage to a first preset value according to the control signal and a preset current. The second release circuit releases the positive high voltage to a second preset value when the positive high voltage reaches the first preset value. Thus, during the release of the positive high voltage to the first preset value, the positive high voltage is released according to a set preset current. That is, during the release of the positive high voltage to the first preset value, the voltage drop of the positive high voltage changes linearly. This improves the reliability of the memory.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0021] Figure 1 This is a schematic diagram of a conventional high-voltage release circuit provided in an embodiment of this disclosure;

[0022] Figure 2 This is a schematic diagram of a high-voltage release circuit provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of the structure of a control circuit provided in an embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram of a bias current circuit provided in an embodiment of this disclosure;

[0025] Figure 5 This is a schematic diagram of the structure of a first release circuit provided in an embodiment of this disclosure;

[0026] Figure 6 This is a schematic diagram of the structure of a second release circuit provided in an embodiment of this disclosure;

[0027] Figure 7 This is a schematic diagram of another high-voltage release circuit provided in an embodiment of this disclosure.

[0028] Figure label:

[0029] 1: Fourth resistor; 2: Fifth resistor; 3: PMOS transistor; 4: Second comparator; 5: Eleventh NMOS transistor; 6: Ninth NMOS transistor; 7: Tenth NMOS transistor; 8: Control circuit; 9: Bias current circuit; 10: First release circuit; 11: Second release circuit; 12: First resistor; 13: Second resistor; 14: Third resistor; 15: First comparator; 16: Fifth NMOS transistor; 17: Sixth NMOS transistor; 18: Current source; 19: First NMOS transistor; 20: Second NMOS transistor; 21: Third NMOS transistor; 22: Fourth NMOS transistor; 23: Eighth NMOS transistor; 24: Inverter; 25: Seventh NMOS transistor. Detailed Implementation

[0030] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0031] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0032] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0033] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0034] Unless otherwise stated, the term "multiple" means two or more.

[0035] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0036] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0038] Combination Figure 2 As shown, this embodiment of the disclosure provides a high-voltage release circuit, including: a control circuit 8, a bias current circuit 9, a first release circuit 10, and a second release circuit 11. The control circuit is connected to the bias current circuit, the first release circuit, and the second release circuit; the control circuit is used to receive a positive high voltage output from the charge pump of the memory, and output a control signal according to the positive high voltage; the bias current circuit is connected to the first release circuit; the bias current circuit is used to provide a bias current to the first release circuit according to the control signal; the first release circuit is connected to the second release circuit; the first release circuit is used to release the positive high voltage value to a first preset value according to the control signal and a preset current; the second release circuit is used to release the positive high voltage value to a second preset value when the positive high voltage value reaches the first preset value.

[0039] The high-voltage release circuit provided in this embodiment connects a bias current circuit, a first release circuit, and a second release circuit via a control circuit. The control circuit receives the positive high voltage output from the charge pump of the memory and outputs a control signal based on the positive high voltage. The bias current circuit is connected to the first release circuit and provides a bias current to the first release circuit according to the control signal. The first release circuit is connected to the second release circuit and releases the positive high voltage to a first preset value according to the control signal and a preset current. The second release circuit releases the positive high voltage to a second preset value when the positive high voltage reaches the first preset value. Thus, during the release of the positive high voltage to the first preset value, the positive high voltage is released according to a set preset current. That is, the voltage drop of the positive high voltage is linear during the release to the first preset value. Because the instantaneous current under high voltage is controllable, the reliability of the memory can be improved, thereby increasing the service life of products containing the memory.

[0040] Combination Figure 3 As shown, optionally, the control circuit includes: a first resistor 12, a second resistor 13, and a first comparator 15. One end of the first resistor 12 is grounded, and the other end of the first resistor 12 is connected to one end of the second resistor 13 and the first input terminal of the first comparator 15; the other end of the second resistor 13 is connected to a first release circuit and a second release circuit, and is used to receive the positive high voltage output by the charge pump of the memory; the second input terminal of the first comparator 15 is used to receive a preset reference voltage; the output terminal of the first comparator 15 is connected to the first release circuit, the bias current circuit, and the second release circuit.

[0041] Combination Figure 4 As shown, optionally, the bias current circuit includes: a fifth NMOS transistor 16, a sixth NMOS transistor 17, and a current source 18; one end of the current source 18 is connected to a power supply, and the other end of the current source 18 is connected to the drain and gate of the sixth NMOS transistor 17; the gate of the sixth NMOS transistor 17 is connected to a first release circuit, and the source of the sixth NMOS transistor 17 is connected to the drain of the fifth NMOS transistor 16; the gate of the fifth NMOS transistor 16 is connected to a control circuit, a first release circuit, and a second release circuit, and the source of the fifth NMOS transistor 16 is grounded. The current source is a constant bias current source. In this way, the bias current circuit provides bias current to the first release circuit. Users can change the release speed of HVPOS by changing the magnitude of the bias current. This allows users to easily change the release speed of HVPOS according to the specifications and model of the memory, thereby better protecting the memory.

[0042] Optionally, the first release circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The drain and gate of the third NMOS transistor are connected to the control circuit and receive the positive high voltage output from the charge pump of the memory. The source of the third NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor and the second release circuit; the gate of the first NMOS transistor is connected to the bias current circuit; the source of the first NMOS transistor is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the control circuit, the bias current circuit, and the second release circuit, and the source of the fourth NMOS transistor is grounded.

[0043] Optionally, one or more seventh NMOS transistors are connected in parallel with the first NMOS transistor. The seventh NMOS transistors and the first NMOS transistors have the same channel width-to-length ratio. Thus, by changing the number of seventh NMOS transistors connected in parallel, the magnitude of the preset current can be changed, thereby allowing the HVPOS to release linearly according to the user's needs.

[0044] Combination Figure 5 As shown, in some embodiments, the first release circuit includes: a first NMOS transistor 19, a second NMOS transistor 20, a third NMOS transistor 21, a fourth NMOS transistor 22, and a seventh NMOS transistor 25. The drain and gate of the third NMOS transistor 21 are connected to the control circuit and receive the positive high voltage output from the charge pump of the memory; the source of the third NMOS transistor 21 is connected to the drain of the second NMOS transistor 20; the gate of the second NMOS transistor 20 is connected to the power supply, and the source of the second NMOS transistor 20 is connected to the drain of the first NMOS transistor 19, the drain of the seventh NMOS transistor 25, and the second release circuit; the gate of the first NMOS transistor 19 is connected to the gate of the seventh NMOS transistor 25 and the bias current circuit; the source of the first NMOS transistor 19 is connected to the drain of the fourth NMOS transistor 22 and the source of the seventh NMOS transistor 25; the gate of the fourth NMOS transistor 22 is connected to the control circuit, the bias current circuit, and the second release circuit, and the source of the fourth NMOS transistor 22 is grounded.

[0045] Combination Figure 6 As shown, optionally, the second release circuit includes: a PMOS transistor 3, a third resistor 14, an eighth NMOS transistor 23, and an inverter 24; one end of the third resistor 14 is connected to the control circuit and receives the positive high voltage output from the charge pump of the memory; the other end of the third resistor 14 is connected to the source of the PMOS transistor 3; the gate of the PMOS transistor 3 is connected to the first release circuit; the drain of the PMOS transistor 3 is connected to the drain of the eighth NMOS transistor 23; the source of the eighth NMOS transistor 23 is connected to the power supply; the gate of the eighth NMOS transistor 23 is connected to the output terminal of the inverter 24; the input terminal of the inverter 24 is connected to the control circuit, the bias current circuit, and the first release circuit.

[0046] In some embodiments, the first preset value is equal to or approximately equal to the sum of the power supply voltage and the threshold voltage of the PMOS transistor. The second preset value is equal to the power supply voltage.

[0047] In some embodiments, the end of the second resistor in the control circuit furthest from the first resistor is connected to the drain of the third NMOS transistor in the first release circuit and the third resistor in the second release circuit. The output of the first comparator in the control circuit is connected to the gate of the fourth NMOS transistor in the first release circuit, the gate of the fifth NMOS transistor in the bias current circuit, and the input port of the inverter in the second release circuit. The gate of the sixth NMOS transistor in the bias current circuit is connected to the gate of the first NMOS transistor in the first release circuit. The gate of the PMOS transistor in the second release circuit is connected to the source of the second NMOS transistor in the first release circuit and the drain of the first NMOS transistor.

[0048] Combination Figure 7As shown, in some embodiments, one end of the first resistor 12 is grounded, and the other end of the first resistor 12 is connected to one end of the second resistor 13 and the first input terminal of the first comparator 15; the other end of the second resistor 13 is connected to one end of the third resistor 14, the drain of the third NMOS transistor 21, and the gate of the third NMOS transistor 21, and is used to receive the positive high voltage output by the charge pump of the memory; the second input terminal of the first comparator 15 is used to receive a preset reference voltage; the output terminal of the first comparator 15 is connected to the gate of the fourth NMOS transistor 22, the gate of the fifth NMOS transistor 16, and the input terminal of the inverter 24. One end of the current source 18 is connected to the power supply, and the other end of the current source 18 is connected to the drain of the sixth NMOS transistor 17 and the gate of the sixth NMOS transistor 17; the gate of the sixth NMOS transistor 17 is connected to the gate of the first NMOS transistor 19, and the source of the sixth NMOS transistor 17 is connected to the drain of the fifth NMOS transistor 16; the source of the fifth NMOS transistor 16 is grounded. The source of the third NMOS transistor 21 is connected to the drain of the second NMOS transistor 20; the gate of the second NMOS transistor 20 is connected to the power supply, and the source of the second NMOS transistor 20 is connected to the drain of the first NMOS transistor 19 and the gate of the PMOS transistor 3; the source of the first NMOS transistor 19 is connected to the drain of the fourth NMOS transistor 22; the source of the fourth NMOS transistor 22 is grounded. The other end of the third resistor 23 is connected to the source of the PMOS transistor 3; the drain of the PMOS transistor 3 is connected to the drain of the eighth NMOS transistor 23; the source of the eighth NMOS transistor 23 is connected to the power supply; the gate of the eighth NMOS transistor 23 is connected to the output of the inverter 24. Thus, when HVPOS starts to release from a higher voltage, for example, HVPOS is 10V and VCC is 2V, if the voltage divider signal DET of HVPOS is greater than the fifth preset value, the output of the first comparator is high, and the fourth NMOS transistor is turned on. The fifth preset value is equal to the value of the second resistor / the first resistor * VREF. HVPOS releases its voltage through the first release path according to a release current of N*IDC. At this time, the voltage drop of HVPOS is linear. When the voltage of HVPOS approaches VCC+VTH1, the first release path approaches turn-off, the gate signal of the PMOS transistor goes low, and the PMOS transistor turns on. Then, HVPOS rapidly releases its voltage through the second release path until the voltage of HVPOS equals the fifth preset value, at which point the second release path turns off. Here, VTH1 is the threshold voltage of the PMOS transistor. IDC is the current value of the current source. The sum of the number of first NMOS transistors and the number of seventh NMOS transistors is called the total number. N is the ratio of the total number to the number of sixth NMOS transistors. For example, in the case of one first NMOS transistor, three seventh NMOS transistors, and one sixth NMOS transistor, N equals 4.

[0049] In some embodiments, if the voltage of HVPOS is greater than VCC+VTH1, it is confirmed that the voltage of HVPOS is at a high value.

[0050] Optionally, the bias current circuit is used to provide a bias current to the first release circuit according to the control signal, including: when the control signal is high, the bias current circuit provides a bias current to the first release circuit.

[0051] Optionally, the bias current circuit is used to provide bias current to the first release circuit according to the control signal, and further includes: when the control signal is low, the bias current circuit stops providing bias current to the first release circuit.

[0052] Optionally, the first release circuit is used to release the positive high voltage value to a first preset value according to the control signal and a preset current, including: when the control signal is at a high level, the first release circuit releases the positive high voltage value to the first preset value according to the preset current.

[0053] Optionally, the first release circuit is used to release the positive high voltage value to a first preset value according to the control signal and a preset current, and further includes: when the control signal is low, the first release circuit stops releasing the positive high voltage value to the first preset value according to the preset current.

[0054] This disclosure provides a memory including the high-voltage release circuit described above.

[0055] The memory provided in this embodiment includes a high-voltage release circuit. The high-voltage release circuit includes a control circuit, a bias current circuit, a first release circuit, and a second release circuit. The control circuit is connected to the bias current circuit, the first release circuit, and the second release circuit. The control circuit receives the positive high voltage output from the memory's charge pump and outputs a control signal based on the positive high voltage. The bias current circuit is connected to the first release circuit and provides a bias current to the first release circuit according to the control signal. The first release circuit is connected to the second release circuit and releases the positive high voltage to a first preset value according to the control signal and a preset current. The second release circuit releases the positive high voltage to a second preset value when the positive high voltage reaches the first preset value. Thus, during the release of the positive high voltage to the first preset value, the positive high voltage is released according to a set preset current. That is, during the release of the positive high voltage to the first preset value, the voltage drop is linear. This improves the reliability of the memory.

[0056] This disclosure provides an electronic device including the memory described above.

[0057] The electronic device provided in this disclosure includes a memory. The memory includes a high-voltage release circuit. The high-voltage release circuit includes a control circuit, a bias current circuit, a first release circuit, and a second release circuit. The control circuit is connected to the bias current circuit, the first release circuit, and the second release circuit. The control circuit receives a positive high voltage output from the charge pump of the memory and outputs a control signal based on the positive high voltage. The bias current circuit is connected to the first release circuit and provides a bias current to the first release circuit according to the control signal. The first release circuit is connected to the second release circuit and releases the positive high voltage to a first preset value according to the control signal and a preset current. The second release circuit releases the positive high voltage to a second preset value when the positive high voltage reaches the first preset value. Thus, during the release of the positive high voltage to the first preset value, the positive high voltage is released according to a set preset current. That is, during the release of the positive high voltage to the first preset value, the voltage drop of the positive high voltage is linear. This improves the reliability of the memory, and consequently, the reliability of the electronic device including the memory.

[0058] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A high-voltage release circuit, characterized in that, include: The control circuit is connected to the bias current circuit, the first release circuit, and the second release circuit. The control circuit is used to receive the positive high voltage output from the charge pump of the memory and output a control signal according to the positive high voltage. The bias current circuit is connected to the first release circuit and the second release circuit. The bias current circuit is used to provide bias current to the first release circuit according to the control signal; The first release circuit is connected to the second release circuit; The first release circuit is used to release the positive high voltage value to a first preset value according to the control signal and the preset current. The second release circuit is used to release the positive high voltage value to the second preset value when the positive high voltage value reaches the first preset value.

2. The high-voltage release circuit according to claim 1, characterized in that, The control circuit includes: a first resistor, a second resistor, and a first comparator; one end of the first resistor is grounded, and the other end of the first resistor is connected to one end of the second resistor and the first input terminal of the first comparator; the other end of the second resistor is connected to a first release circuit and a second release circuit, and is used to receive the positive high voltage output by the charge pump of the memory; the second input terminal of the first comparator is used to receive a preset reference voltage; the output terminal of the first comparator is connected to the first release circuit, the bias current circuit, and the second release circuit.

3. The high-voltage release circuit according to claim 1, characterized in that, The bias current circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, and a current source; one end of the current source is connected to a power supply, and the other end of the current source is connected to the drain and gate of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to a first release circuit, and the source of the sixth NMOS transistor is connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to a control circuit, a first release circuit, and a second release circuit, and the source of the fifth NMOS transistor is grounded.

4. The high-voltage release circuit according to claim 1, characterized in that, The first release circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the drain and gate of the third NMOS transistor are connected to a control circuit and receive a positive high voltage output from the charge pump of the memory; the source of the third NMOS transistor is connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is connected to a power supply, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor and the second release circuit; the gate of the first NMOS transistor is connected to a bias current circuit; the source of the first NMOS transistor is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the control circuit, the bias current circuit, and the second release circuit, and the source of the fourth NMOS transistor is grounded.

5. The high-voltage release circuit according to claim 4, characterized in that, There are one or more seventh NMOS transistors connected in parallel with the first NMOS transistor.

6. The high-voltage release circuit according to claim 1, characterized in that, The second release circuit includes: a PMOS transistor, a third resistor, an eighth NMOS transistor, and an inverter; one end of the third resistor is connected to the control circuit and receives the positive high voltage output from the charge pump of the memory; the other end of the third resistor is connected to the source of the PMOS transistor; the gate of the PMOS transistor is connected to the first release circuit; the drain of the PMOS transistor is connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor is connected to the power supply; the gate of the eighth NMOS transistor is connected to the output terminal of the inverter; the input terminal of the inverter is connected to the control circuit, the bias current circuit, and the first release circuit.

7. The high-voltage release circuit according to any one of claims 1 to 6, characterized in that, The bias current circuit is used to provide bias current to the first release circuit according to the control signal, including: When the control signal is high, the bias current circuit provides bias current to the first release circuit.

8. The high-voltage release circuit according to any one of claims 1 to 6, characterized in that, The first release circuit is used to release the positive high voltage value to a first preset value according to a preset current based on a control signal, including: When the control signal is high, the first release circuit releases the positive high voltage value to the first preset value according to the preset current.

9. A memory, characterized in that, include: Includes the high-voltage release circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the memory as described in claim 9.

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