An integrated circuit daisy chain structure and failure location method

Abstract

The application discloses an integrated circuit daisy chain structure and a failure positioning method, and the circuit structure comprises a plastic package substrate, substrate wiring, a substrate via, a substrate test pad, a BGA pad, a chip, chip internal wiring, a TSV via, a chip pad and a flip chip solder joint. A plurality of substrate wirings and substrate test pads are arranged on the front surface of the plastic package substrate, the substrate wiring is connected with the substrate test pad and the flip chip solder joint, the substrate via is connected with the substrate wiring and the BGA pad; a plurality of internal wirings are arranged on the side of the chip facing the plastic package substrate, the internal wiring is connected with the flip chip solder joint, each flip chip solder joint is connected to the back surface of the chip through the TSV via, and the chip pad is manufactured, and the position and quantity of the chip pad are consistent with the quantity and position of the flip chip solder joint. The application solves the problem that the large quantity of flip chip solder joints in the plastic package flip chip daisy chain circuit causes the solder joint failure and the failure cannot be accurately positioned, and is helpful to the development of package failure analysis and the improvement of the plastic package flip chip process quality and the guarantee of the reliability of the plastic package flip chip circuit.

Description

TECHNICAL FIELD

[0001] The application relates to an integrated circuit daisy chain structure and a failure positioning method and belongs to the technical field of semiconductor packaging. BACKGROUND

[0002] At present, flip-chip technology is the most widely used interconnection technology in the field of high-performance, high-reliability and high-density packaging. The mechanical and electrical connection between the chip and the substrate is realized by preparing a two-dimensional array of bumps on the active surface of the chip. Flip-chip technology has a series of advantages such as high packaging density, fast signal processing speed and high reliability. According to the different types of substrates, flip-chip can be divided into ceramic flip-chip and plastic flip-chip. The plastic flip-chip technology mainly uses a multilayer organic substrate. Compared with the ceramic substrate, the plastic flip-chip technology has great advantages in wiring density, transmission speed, volume, mass, cost and other aspects. Therefore, the development of plastic flip-chip technology is the most rapid.

[0003] With the continuous improvement of the packaging density of plastic flip-chip, the size and spacing of the interconnection solder joints are sharply reduced, which brings severe challenges to the packaging process. In order to ensure the process quality and verify the product reliability, a daisy chain verification circuit is often used before the formal product packaging. The interconnection solder joints are connected through the wiring inside the chip and the substrate to form several complete links and carry out full verification from the packaging process and long-term reliability. The daisy chain circuit includes a daisy chain chip and a daisy chain substrate, and involves many complex structures such as chip pads, chip wiring, substrate pads and substrate wiring. It is the core of the daisy chain circuit design.

[0004] The conventional plastic flip-chip circuit is tested by electrically connecting the test pads of the substrate. Only the failure detection of the entire link can be realized. However, the entire link may contain hundreds of flip-chip joints, which cannot be accurately positioned. Therefore, after the failure of the plastic flip-chip circuit, it is difficult to carry out failure positioning analysis, which seriously affects the analysis of the failure mode and the failure mechanism and causes serious obstacles to the development and optimization of the plastic flip-chip process. SUMMARY

[0005] The technical problem to be solved by the application is to provide an integrated circuit daisy chain structure and a failure positioning method. The application is used for plastic flip-chip process quality verification and long-term reliability evaluation, is suitable for plastic flip-chip substrates of different sizes and structures, has the characteristics of simple design, wide application and accurate results, can effectively characterize the plastic flip-chip process quality, solves the problem of difficult failure positioning caused by the large number of flip-chip joints and the complex structure of the plastic flip-chip daisy chain circuit, and lays a foundation for the improvement of the plastic flip-chip process quality and reliability.

[0006] The technical scheme adopted by the application is as follows:

[0007] In a first aspect,

[0008] An integrated circuit daisy chain structure comprises a plastic package substrate, substrate wiring, substrate test pads, a chip, internal wiring, TSV through holes, chip pads, flip chip solder joints, substrate through holes and substrate BGA pads;

[0009] The plastic package substrate has a front surface and a back surface. The front surface is provided with a plurality of substrate wirings and substrate test pads. The back surface is provided with a plurality of substrate BGA pads.

[0010] The chip has a front surface and a back surface. The front surface is provided with a plurality of internal wirings. The back surface is provided with a plurality of chip pads.

[0011] The flip chip solder joints are located between the plastic package substrate and the chip.

[0012] The chip pads correspond to the positions of the flip chip solder joints. The chip pads and the flip chip solder joints are electrically connected through TSV through holes.

[0013] The plurality of flip chip solder joints are sequentially connected to form a chain. The flip chip solder joints at both ends of the chain are connected to the substrate test pads through the substrate wirings. The flip chip solder joints on the same chain are electrically connected through the internal wirings and the substrate wirings.

[0014] The substrate through holes are located inside the plastic package substrate. The substrate through holes connect the substrate wirings and the substrate BGA pads. The substrate BGA pads correspond to the positions of the flip chip solder joints.

[0015] Preferably, the plastic package substrate is a multi-layer composite structure. The surface size of the plastic package substrate is in the range of 5*5mm to 45*45mm. The thickness of the plastic package substrate is in the range of 1mm to 2mm.

[0016] Preferably, the plastic package substrate uses glass fiber cloth dipped in epoxy resin as a reinforcing structure. The thickness of the reinforcing structure is in the range of 400μm to 800μm. BT resin or ABF resin is used as a laminated structure and is attached to the upper and lower sides of the reinforcing structure. The number of layers of the laminated structure is in the range of 2 to 8. The thickness of each layer of the laminated structure is in the range of 15μm to 30μm.

[0017] Preferably, the chip is made of silicon-based material. The internal wiring is prepared on the front surface of the chip. The material of the internal wiring is copper. The shape of the internal wiring is a straight line or a broken line. The internal wiring is prepared by electroplating process. The width of the internal wiring is in the range of 10μm to 15μm.

[0018] The flip chip solder joints on each chain are sequentially numbered. The upper ends of the flip chip solder joints numbered 2n+1 and 2n+2 are connected through the internal wiring. n is 0, 1, 2, 3, ….

[0019] Preferably, the material of the substrate wiring is copper. The shape of the substrate wiring is a straight line or a broken line. The substrate wiring is prepared by electroplating process. The width of the substrate wiring is in the range of 15μm to 20μm.

[0020] The two ends of each flip chip on each link are connected by substrate wiring.

[0021] Preferably, the flip chip is made of tin-based material, prepared by ball placement or electroplating, and the interconnection between the chip and the plastic package substrate is achieved by reflow soldering, and the diameter of the flip chip is 80-120 μm.

[0022] Preferably, the total number of test pads on the plastic package substrate is even, the total number of flip chips on each link is even, and each two adjacent test pads form a group, and the two test pads in each group are connected to the first and last flip chips of each link, respectively.

[0023] Preferably, the shape of the test pad on the substrate is circular or square, the diameter of the circular test pad is 1-2 mm, and the side length of the square test pad is 1-2 mm; the test pad on the substrate is prepared by electroplating process and has a Ni-Au structure, the Au layer is above the Ni layer, the thickness of the Ni layer is more than 2.54 μm, and the thickness of the Au layer is 0.02-0.3 μm.

[0024] Preferably, the diameter of the chip pad is 90-150 μm, and the chip pad material is Cu-Ni structure, the thickness of Cu is 5 μm, and the thickness of Ni is 2-3 μm.

[0025] The second aspect,

[0026] A failure positioning method using the integrated circuit daisy chain structure of the first aspect, comprising the following steps:

[0027] Step one, adjust the multimeter to the ohm range, and make the red and black probes of the multimeter contact a group of substrate test pads respectively, until each group of test pads is traversed, if there is a case of infinite resistance value, it indicates that the link connected to the group of test pads is failed, and the substrate test pad number of the failed link is recorded;

[0028] Step two, use any one probe of the multimeter as probe A and the other as probe B; keep probe A contacting any one substrate test pad corresponding to the failed link unchanged, and sequentially contact the other probe B with the flip chips in the order of connection and the chip pads on the failed link, until each chip pad is traversed, if the resistance values of two adjacent chip pads suddenly become infinite, record the substrate test pad number of the infinite resistance value as the failure point.

[0029] Step three, using pen A to contact the first chip pad after the failure point, keep it still, and using another pen B to traverse the rest chip pads on the failure link from the second chip pad after the failure point, if the resistance of two adjacent chip pads changes from finite to infinite, record the substrate test pad number with infinite resistance as the failure point;

[0030] Step four, repeat step three for several times until all chip pads on the failure link are traversed, and multiple failure points are obtained;

[0031] Step five, contact pen A of the multimeter with any substrate test pad of the failure point, and contact the other pen with the substrate BGA pad corresponding to the substrate test pad, if there is infinite resistance, it is determined that the flip chip pad corresponding to the test pad is failed, otherwise, it is determined that the substrate wiring or chip internal wiring connected with the flip chip pad is failed;

[0032] Step six, repeat step five for several times until all failure points are traversed;

[0033] Step seven, repeat steps two to six until all substrate test pads of the failure link are traversed, and the failure positioning work is completed.

[0034] The beneficial effects of the present application compared with the prior art are:

[0035] (1) The circuit structure in the present application adopts substrate internal wiring, chip internal wiring and flip chip to form an electrical on-off test link, which can effectively detect the welding quality of all flip chips, and has wide coverage;

[0036] (2) The circuit structure in the present application guides the flip chip to the chip back and BGA pad through TSV via hole and substrate via hole, which can effectively solve the problem that the flip chip cannot be accurately positioned and detected in the conventional daisy chain circuit structure. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a side view of a plastic encapsulation daisy chain circuit structure;

[0038] Figure 2 is a top view of a plastic encapsulation daisy chain circuit structure;

[0039] Figure 3 is a plastic encapsulation substrate test pad on-off test diagram;

[0040] Figure 4 is a plastic encapsulation substrate test pad-chip pad on-off test diagram;

[0041] Figure 5 is a chip pad-BGA pad on-off test diagram. DETAILED DESCRIPTION

[0042] The application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, but is not limited thereto, and any modification or equivalent replacement of the application scheme without departing from the spirit and scope of the application shall be covered in the protection scope of the application.

[0043] The application is a daisy chain structure of integrated circuit, as shown in Figure 1 and Figure 2 The application comprises a plastic package substrate 1, substrate wiring 2, substrate test pad 3, chip 4, internal wiring 5, TSV through hole 6, chip pad 7, flip chip 8, substrate through hole 9 and substrate BGA pad 10. The plastic package substrate 1 is provided with a plurality of substrate wiring 2 and substrate test pad 3 on the front side; the plastic package substrate 1 is provided with a plurality of substrate BGA pad 10 on the back side;

[0044] The chip 4 is provided with a plurality of internal wiring 5 on the front side (close to the plastic package substrate 1); the chip 4 is provided with a plurality of chip pad 7 on the back side; the flip chip 8 is located between the plastic package substrate 1 and the chip 4; the chip pad 7 corresponds to the position of the flip chip 8; the electrical connection between the chip pad 7 and the flip chip 8 is realized through the TSV through hole 6; a plurality of flip chips 8 are sequentially connected to form a link, and the lower end of the flip chip 8 at both ends of the link is connected to the substrate test pad 3 through the substrate wiring 2; the flip chips 8 on the same link are electrically connected through the internal wiring 5 and the substrate wiring 2; the substrate through hole 9 is located in the interior of the plastic package substrate 1; the substrate through hole 9 connects the substrate wiring 2 and the substrate BGA pad 10; the substrate BGA pad 10 corresponds to the position of the flip chip 8.

[0045] The plastic package substrate 1 is a multi-layer composite structure, the surface size of the plastic package substrate 1 is in the range of 5*5mm to 45*45mm, and the thickness of the plastic package substrate 1 is 1-2mm, as shown in Figure 1 .

[0046] The plastic package substrate 1 uses glass fiber cloth dipped in epoxy resin as a reinforcing structure, and the thickness of the reinforcing structure is in the range of 400-800μm; BT resin or ABF resin is used as a laminated structure, which is attached to the upper and lower sides of the reinforcing structure, and the number of layers of the laminated structure is 2-8, and the thickness of each layer of the laminated structure is 15-30μm.

[0047] Chip 4 is silicon-based material, chip 4 front surface is prepared with chip internal wiring 5, internal wiring 5 material is copper, shape is straight line or broken line, prepared by electroplating process, internal wiring 5 width is 10-15μm; Flip chip solder joint 8 on each link is sequentially numbered, two two upper ends of flip chip solder joint 8 with number 2n+1 and 2n+2 are communicated through internal wiring 5, two two upper ends of flip chip solder joint 8 located at the head of the link are communicated through internal wiring 5; Two two upper ends of flip chip solder joint 8 located at the last of the link are communicated through internal wiring 5; N is a positive integer.

[0048] Substrate wiring 2 material is copper, shape is straight line or broken line, prepared by electroplating process, substrate wiring 2 width is 15-20μm; Two two lower ends of flip chip solder joint 8 with number 2n+2 and 2n+3 on each link are communicated through substrate wiring 2; Two two lower ends of flip chip solder joint 8 with number 2 and 3 on each link are communicated through substrate wiring 2. That is, the second and the third, the fourth and the fifth... (so on and so forth) every two flip chip solder joints 8 are communicated.

[0049] The composition of the flip chip solder joint 8 is tin-based material, prepared by ball placement method or electroplating method, the interconnection of the chip 4 and the plastic package substrate 1 is realized by reflow soldering method, and the diameter of the flip chip solder joint 8 is 80-120μm.

[0050] The total number of test pads 3 on the plastic package substrate 1 is even, the total number of flip chip solder joints 8 on each link is even, two adjacent test pads 3 form a group, and the two test pads 3 in each group are connected to the first and the last flip chip solder joints 8 of each link respectively; The shape of the test pad 3 on the substrate is circular or square, when the test pad 3 on the substrate is circular, the diameter is 1mm-2mm, when the test pad 3 on the substrate is square, the side length is 1mm-2mm; The test pad 3 on the substrate is prepared by electroplating process, which is Ni-Au structure, the upper layer of Ni layer is Au layer, the thickness of Ni layer is more than 2.54μm, and the thickness of Au layer is 0.02μm-0.3μm.

[0051] The internal filling material of the substrate via hole 9 is copper, and the diameter of the substrate via hole 9 is 200um.

[0052] The TSV via hole 6 is located in the interior of the chip 4, the filling material of the TSV via hole 6 is copper, the diameter is 10um, the position of the TSV via hole 6 is consistent with the position of the flip chip solder joint 8, and the TSV via hole 6 is communicated with the chip pad 7 on the back of the chip 4, the diameter of the chip pad 7 is 90-150um, the material of the chip pad 7 is Cu-Ni structure, the thickness of Cu is 5um, and the thickness of Ni is 2-3um.

[0053] A failure positioning method using the above integrated circuit daisy chain structure, comprising the following steps:

[0054] Step one, adjust the multimeter to the ohm range, and make the red and black probes of the multimeter contact a group of substrate test pads 3 respectively, until every group of test pads 3 is traversed. If there is a case of infinite resistance value, it indicates that the link connected to the group of test pads 3 is failed, and the substrate test pad 3 number of the failed link is recorded. See Figure 3 ;

[0055] Step two, use any one probe of the multimeter as probe A and the other as probe B; keep probe A contacting any one substrate test pad 3 corresponding to the failed link unchanged, and contact the chip pads 7 on the failed link in the order of the flip-chip pads 8 and the substrate test pads 7 in step one with probe B in turn, until every chip pad 7 is traversed. If the resistance values of two adjacent chip pads 7 suddenly become infinite, record the substrate test pad 7 number with infinite resistance value as the failure point.

[0056] Step three, keep probe A contacting the first chip pad 7 after the failure point unchanged, and continue to traverse the remaining chip pads 7 on the failed link from the second chip pad 7 after the failure point with probe B. If the resistance values of two adjacent chip pads 7 suddenly become infinite, record the substrate test pad 7 number with infinite resistance value as the failure point. See Figure 4 ;

[0057] Step four, repeat step three multiple times until all chip pads 7 on the failed link are traversed, and multiple failure points are obtained.

[0058] Step five, contact probe A of the multimeter with any one substrate test pad 7 of the failure point, and contact the substrate BGA pad 10 corresponding to the substrate test pad 7 with the other probe. If there is a case of infinite resistance value, it is determined that the flip-chip pad 8 corresponding to the substrate test pad 7 is failed, otherwise, it is determined that the substrate wiring 2 or the chip internal wiring 5 connected to the flip-chip pad 8 corresponding to the test pad 7 is failed. See Figure 5 ;

[0059] Step six, repeat step five multiple times until all failure points are traversed.

[0060] Step seven, repeat steps two to six until all substrate test pads 3 of the failed links are traversed, and the failure positioning work is completed.

[0061] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application to the preferred embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

[0062] The contents not described in detail in the specification of the present application are the known technologies of the person skilled in the art.

Claims

1. A method for failure localization using an integrated circuit daisy chain structure, comprising: Integrated circuit daisy chain structure, comprising: plastic package substrate (1), substrate wiring (2), substrate test pad (3), chip (4), chip internal wiring (5), TSV through hole (6), chip pad (7), flip chip solder joint (8), substrate through hole (9) and substrate BGA pad (10); The front of the plastic package substrate (1) is provided with a plurality of substrate wirings (2) and substrate test pads (3); the back of the plastic package substrate (1) is provided with a plurality of substrate BGA pads (10); The front of the chip (4) is provided with a plurality of internal wirings (5); the back of the chip (4) is provided with a plurality of chip pads (7); The flip chip solder joint (8) is located between the plastic package substrate (1) and the chip (4); The chip pad (7) corresponds to the position of the flip chip solder joint (8); the chip pad (7) and the flip chip solder joint (8) are electrically connected through the TSV through hole (6); A plurality of flip chip solder joints (8) are sequentially connected to form a link, and the flip chip solder joints (8) at both ends of the link are connected to the substrate test pads (3) through the substrate wirings (2); the flip chip solder joints (8) on the same link are electrically connected through the internal wirings (5) and the substrate wirings (2); The substrate through hole (9) is located inside the plastic package substrate (1); the substrate through hole (9) connects the substrate wiring (2) and the substrate BGA pad (10); the substrate BGA pad (10) corresponds to the position of the flip chip solder joint (8); The failure positioning method comprises the following steps: Step one, adjust the multimeter to the ohm range, and make the red and black probes of the multimeter contact a group of substrate test pads (3) respectively, until each group of test pads (3) is traversed, if there is a case of infinite resistance value, it indicates that the link connected to the test pad (3) of the group is failed, and the substrate test pad (3) of the failed link is recorded; Step two, use any one probe of the multimeter as probe A and the other as probe B; keep probe A contacting any one of the substrate test pads (3) corresponding to the failed link unchanged, and sequentially contact the chip pads (7) on the failed link with probe B in the order of the flip chip solder joint (8), until each chip pad (7) is traversed, if the resistance values of two adjacent chip pads (7) suddenly become infinite, record the substrate test pad (7) with infinite resistance value as the failure point; Step three, keep probe A contacting the first chip pad (7) after the failure point unchanged, and continue to traverse the remaining chip pads (7) on the failed link from the second chip pad (7) after the failure point with probe B, if the resistance values of two adjacent chip pads (7) suddenly become infinite, record the substrate test pad (7) with infinite resistance value as the failure point; Step four, repeat step three multiple times until all chip pads (7) on the failed link are traversed, and a plurality of failure points are obtained; Step five, the pen A of universal meter and any one of the substrate test pad (7) of invalid point contact, the other table pen contact the substrate BGA pad (10) corresponding to the substrate test pad (7), if there is resistance infinite case, it is judged that the flip welding point (8) corresponding to the substrate test pad (7) is invalid, otherwise, it is judged that the substrate wiring (2) or the wiring (5) in the chip connected with the flip welding point (8) corresponding to the test pad (7) is invalid; Step six, repeat step five several times, until all invalid points are traversed; Step seven, repeat steps two to six, until all substrate test pads (3) of invalid link are traversed, complete the invalid positioning work.

2. The method for failure localization using an integrated circuit daisy chain structure of claim 1, wherein, The plastic package substrate (1) is a multi-layer composite structure, the surface size of the plastic package substrate (1) is in the range of 5*5mm to 45*45mm, and the thickness of the plastic package substrate (1) is 1-2mm.

3. The method of claim 2, wherein: The plastic package substrate (1) uses glass fiber cloth dipped in epoxy resin as a reinforcing structure, the thickness of the reinforcing structure is in the range of 400-800μm; BT resin or ABF resin is used as a laminated structure, which is attached to the upper and lower sides of the reinforcing structure, the number of layers of the laminated structure is 2-8, and the thickness of each layer of the laminated structure is 15-30μm. ​ 4. The method for failure localization using an integrated circuit daisy chain structure of claim 1, wherein: The chip (4) is a silicon-based material, and the internal wiring (5) is prepared on the front surface of the chip (4), the material of the internal wiring (5) is copper, the shape of the internal wiring (5) is a straight line or a broken line, the internal wiring (5) is prepared by electroplating process, and the width of the internal wiring (5) is 10-15μm. The flip welding points (8) on each link are sequentially numbered, and the upper ends of the flip welding points (8) numbered 2n+1 and 2n+2 are connected by the internal wiring (5); n is 0, 1, 2, 3, ….

5. The method for failure localization using an integrated circuit daisy chain structure of claim 4, wherein: The material of the substrate wiring (2) is copper, the shape of the substrate wiring (2) is a straight line or a broken line, the substrate wiring (2) is prepared by electroplating process, and the width of the substrate wiring (2) is 15-20μm. The lower ends of the flip welding points (8) numbered 2n+2 and 2n+3 on each link are connected by the substrate wiring (2).

6. The method for failure localization using integrated circuit daisy chain structure according to any one of claims 1 to 5, characterized in that: The composition of the flip welding point (8) is tin-based material, which is prepared by ball placement method or electroplating method, the interconnection between the chip (4) and the plastic package substrate (1) is realized by reflow soldering, and the diameter of the flip welding point (8) is in the range of 80-120μm.

7. The method for failure localization using integrated circuit daisy chain structure according to any one of claims 1 to 5, characterized in that: The total number of test pads (3) on the plastic package substrate (1) is even, the total number of flip welding points (8) on each link is even, and two adjacent test pads (3) form a group, and the two test pads (3) in each group are connected to the first and last flip welding points (8) of each link respectively.

8. The method of claim 7, wherein: The shape of the substrate test pad (3) is circular or square, when the substrate test pad (3) is circular, the diameter is in the range of 1mm-2mm, when the substrate test pad (3) is square, the side length is in the range of 1mm-2mm; the substrate test pad (3) is prepared by electroplating process, which is Ni-Au structure, the upper layer of Ni layer is Au layer, the thickness of Ni layer is more than 2.54μm, and the thickness of Au layer is in the range of 0.02μm-0.3μm. ​ 9. The method for failure localization using integrated circuit daisy chain structure according to any one of claims 1-5, characterized in that: The diameter of the chip pad (7) is in the range of 90-150um.

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