A programmable CoI filter implementing shift-truncation division and its generation method
By designing a programmable CoI filter and employing a shift-truncation divider and Chisel script automatic generation technology, the flexibility and accuracy issues of the CoI decimation filter were solved, achieving efficient and low-cost division operations to meet the diverse needs of downconversion systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU VANGO TECH
- Filing Date
- 2022-12-27
- Publication Date
- 2026-06-30
Smart Images
Figure CN116248125B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital downconversion, and in particular to a programmable CoI filter that implements shift-truncation division and its generation method. Background Technology
[0002] With the accelerated construction of the ubiquitous power Internet of Things (IoT), an increasing number of sensing nodes are being deployed in the sensing layer to achieve electrical signal measurement and energy metering functions. How to achieve these functions using high-precision, low-cost, and high-speed analog-to-digital converters (ADCs) has become a hot topic in scientific research and product development. Currently, delta-Σ (Δ-Σ) ADCs are widely used in electrical signal measurement, but their conversion speed is relatively slow, and the CIC decimation filter, including the comb filter, has a large area overhead. Incremental ADCs, on the other hand, can significantly improve conversion speed while achieving more accurate low-frequency signal detection, and their CoI decimation filter is simpler and effectively reduces area occupation. Therefore, incremental ADCs and their matching CoI decimation filters have become a research hotspot.
[0003] However, in related technologies, there are two pressing technical problems that need to be solved for CoI decimation filters. First, CoI decimation filters with fixed downsampling rates and cascaded stages have limited output bandwidth, making them difficult to adapt to the diverse needs of downconverter systems. Second, CoI decimation filters involve division operations. To achieve division operations with high accuracy, low area overhead, and short computation cycle, it is necessary to convert division calculations into bitwise shift operations to reduce computational resource consumption. Unable to be converted precisely to 2 n In simple bitwise operations, the representation of division can introduce significant computational errors. To achieve high-precision division, there are typically two approaches: software implementation and hardware implementation. The former can be implemented in a DSP, increasing the computation cycle and requiring higher DSP computing power. The latter usually calls a division IP core, but this not only has a longer computation cycle but also significantly increases area overhead, raising chip costs.
[0004] Therefore, there is an urgent need to propose effective solutions to the aforementioned problems in existing CoI decimation filters. Summary of the Invention
[0005] This application provides a programmable CoI filter that implements shift-truncation division and its generation method, so as to at least solve the problems of low flexibility, low calculation accuracy, large area overhead and long calculation cycle of CoI decimation filters in related technologies.
[0006] In a first aspect, embodiments of this application provide a programmable CoI filter, the filter comprising: an encoder, an integrator, a decimator, and a shift truncation divider, wherein the shift truncation divider comprises a shift adder and a truncation compensator;
[0007] The encoder is used to encode the input analog-to-digital converter code streams of different bit widths;
[0008] The integrator is used to perform integral calculations on the encoded data;
[0009] The extractor is used to extract the calculation results of the integrator in each conversion cycle;
[0010] The shift-truncation divider is used to adjust the mapping relationship between the input / output port parameters and the hardware circuit, perform division operations on the extracted data, and obtain the final output result.
[0011] In some embodiments, adjusting the mapping relationship between the input / output port parameters and the hardware circuit, and performing division calculations on the extracted data to obtain the final output result includes:
[0012] The mapping relationship between input / output port parameters and hardware circuits is adjusted by a custom algorithm formula. The extracted data is then divided to obtain the final output result. The custom algorithm formula is as follows: Specific steps include:
[0013] The mapping relationship between input / output port parameters and hardware circuitry is adjusted by a custom algorithm formula. The extracted data is then divided to obtain the final output result. The custom algorithm formula is shown below:
[0014]
[0015] The algorithm performs shift addition and truncation compensation on the output ITGR of the decimator to finally obtain the output S of the CoI filter. out Specifically, ITGR is the output of the extractor. B is the shift value. H With B L These represent the high and low bits of the truncation range, respectively, SUM (B H B L ) refers to the truncation of SUM by B H To B L Data within the range, SUM(B) L-1 ) refers to the truncation of SUM at point B. L-1 Bit data; the truncation range is determined by the output data bit width B. out The value of B is calculated from the input and output port parameters. H B LThese represent the high and low bits of the truncation, respectively; N is the number of CoI filter cascades; M is the decimation factor; D is the delay factor; B... in For the input data bit width, B L-1 The most significant bit is the rounding bit, where the rounding bit is the ratio of B. L Lower data bits, SUM (B H B L This refers to truncating SUM.
[0016] In some of these embodiments, when the result SUM(B) is truncated... H B L The data bit width is less than the output data bit width B. out At that time, the truncated result SUM (B H B L ) Move to the left.
[0017] In some embodiments, corresponding shift values and truncation range values are set according to different extraction multiples.
[0018] In some embodiments, encoding the bit width of the input analog-to-digital converter bitstream includes:
[0019] The encoder encodes the input analog-to-digital converter bitstream data using an encoding algorithm to obtain the corresponding two's complement data. The encoding formula is as follows:
[0020] B temp =N log2 M D +B in
[0021] Where N is the number of CoI filter cascades, M is the decimation factor, D is the delay factor, Bin is the input data bit width, and B temp is the output data bit width of the Nth stage integrator.
[0022] In some embodiments, the input data bit width is set to match the quantizer bit width of the incremental analog-to-digital converter, and the CoI filter level N is set to match the order of the incremental analog-to-digital converter.
[0023] In some embodiments, the integrator includes a reset signal.
[0024] During each conversion cycle, the reset signal is activated once to zero out each integrator.
[0025] Secondly, embodiments of this application provide a method for the programmable CoI filter described in the first aspect, the method comprising:
[0026] Preset the input and output port parameters of the CoI filter;
[0027] Based on the mapping relationship between input / output port parameters and hardware circuits, the parameters of each sub-module in the filter are configured to automatically generate a CoI filter.
[0028] In some embodiments, the method further includes:
[0029] Set an excitation and verify the output of the CoI filter using the excitation.
[0030] In some embodiments, CoI filters are automatically generated via a chisel configuration script.
[0031] Compared to related technologies, this application provides a programmable CoI filter for implementing shift-truncation division. The filter includes an encoder, an integrator, a decimator, and a shift-truncation divider. The shift-truncation divider includes a shift adder and a truncation compensator. The encoder encodes input analog-to-digital converter (ADC) code streams of different bit widths. The integrator performs integration calculations on the encoded data. The decimator extracts the calculation result from the integrator in each conversion cycle. The shift-truncation divider adjusts the mapping relationship between the input / output port parameters and the hardware circuit, performs division operations on the extracted data, and obtains the final output result.
[0032] This application, on the one hand, automatically generates RTL code for the CoI decimation filter by configuring chisel script parameters, enabling flexible adjustment of signal bandwidth to meet diverse application needs in the downconversion field and improve design efficiency. On the other hand, through the design of shift-truncation division, this invention effectively reduces the computation cycle and area overhead in the division operation of the CoI decimation filter, achieving division operations with high computational accuracy, low area overhead, and short computation cycle, thus possessing comprehensive advantages. Attached Figure Description
[0033] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0034] Figure 1 This is a schematic diagram of a programmable CoI filter according to an embodiment of this application;
[0035] Figure 2 This is a schematic diagram of a shift truncation divider structure according to an embodiment of this application;
[0036] Figure 3 This is a flowchart of a method for generating a programmable CoI filter according to an embodiment of this application; Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.
[0038] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.
[0039] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.
[0040] This embodiment provides a programmable CoI filter for implementing shift-truncation division. Figure 1 This is a schematic diagram of a programmable CoI filter according to an embodiment of this application. Figure 2 This is a schematic diagram of a shift truncation divider structure according to an embodiment of this application, as shown below. Figure 1 As shown, the CoI filter includes: an encoder, an integrator, a decimator, and a shift / truncation divider, as follows: Figure 2 As shown, the shift-truncation divider includes a shift adder and a truncation compensator;
[0041] Specifically, the encoder is used to encode the input analog-to-digital converter code stream with different bit widths; the integrator is used to perform integral calculations on the encoded data; the decimator is used to decimate the calculation results of the integrator in each conversion cycle; and the shift truncation divider is used to adjust the mapping relationship between the input and output port parameters and the hardware circuit, perform division operations on the decimated data, and obtain the final output result.
[0042] This embodiment effectively reduces the computation cycle and area overhead in the division operation of the CoI decimation filter by using the above-mentioned filter, achieving a division operation with high computational accuracy, small area overhead, and short computation cycle.
[0043] In some embodiments, the encoder encodes the input analog-to-digital converter (ADC) bitstream width by: the encoder encodes the input ADC bitstream data using an encoding algorithm to obtain the corresponding two's complement data, wherein the encoding formula is shown in equation (1) below:
[0044] B temp =N log2 M D +B in (1)
[0045] Where N is the number of CoI filter cascades, M is the decimation factor, D is the delay factor, Bin is the input data bit width, and B temp is the output data bit width of the Nth stage integrator.
[0046] Preferably, in this embodiment, when setting the input parameters, the input data bit width B in It can be set to 1, 4, ..., which numerically matches the quantizer bit width of the incremental analog-to-digital converter. The CoI filter level N is set to match the order of the incremental analog-to-digital converter to improve the signal-to-noise ratio. The delay factor D is usually set to 1, and the downsampling rate M (i.e., the decimation factor) can be set to 32, 64, 128, 256, 512, 1024.
[0047] It should be noted that special care must be taken to prevent computational overflow in the integral calculation path. The B obtained by formula (1) temp This is the minimum data bit width required to prevent operational overflow in the Nth-order integrator, while the minimum data bit width required for integrators of orders 1, 2, ..., N-1 is all less than B. temp Therefore, adjusting the data bit width of the 1st, 2nd, ... N-1th order integrators can further reduce the circuit area overhead.
[0048] In some embodiments, the integrator also includes a reset signal that is active during each conversion cycle and sets each integrator to zero.
[0049] After the integrator completes the integration calculation, the decimator extracts the calculation result of the Nth stage integrator in each conversion cycle. If the divider in the existing technology is used, it will directly divide the extracted result by (M+1). The division operation is performed using M / 2 to obtain the output result. However, the IP core of a general-purpose divider requires multiple clock cycles and has a large area overhead. Therefore, it is not suitable for applications where high precision is not required or where the denominator can be approximated as 2. n When the form is , division is usually performed using an arithmetic right shift. However, in the application scenarios of CoI filters, the downsampling rate M ranges from 32 to 1024. Using the approximate shift division method in a general divider, the error can reach up to 3%, which is unacceptable in practical applications.
[0050] Therefore, this embodiment adopts the following... Figure 2 The shift-truncation divider shown can perform division operations with high computational accuracy, low area overhead, and short computation cycle. In this embodiment, the design of the shift-truncation divider fully considers the special characteristics of CoI filter division operations, namely, the output result ∈ [-1, 1], which means that when the analog value is at full scale, the integration result of the second-level integrator is M. (M+1) / 2. Assume the input bitstream width is B. in =1, integration delay D=1, filter cascade number N=2, downsampling rate M=128, output data bit width B out Taking 16-bit as an example, when the analog value is at full scale in both positive and negative directions, the calculation result of the second-stage integrator is ±M. (M+1) / 2 = ±8256, at this time the data bit width of the second-stage integrator is B. temp =2 log2 M +1 = 15 bits. Calculation shows that a 15-bit data width can be represented as 2... 15=32768 distinct numbers, which can be represented as all numbers in the range [-8256, 8256]. That is, when the bit width of the integrator output data is less than or equal to the bit width of the divider output ([-1, 1]), all the integrator output results can be mapped to the divider output results and the divider output still has some redundant bits. This means that it is feasible to perform division operations through the combinational logic of the shift and truncation divider in this embodiment.
[0051] Preferably, the shift-truncation divider in this embodiment is used to adjust the mapping relationship between the input / output port parameters and the hardware circuit, perform division operations on the extracted data, and obtain the final output result. Specific steps include:
[0052] The mapping relationship between the input / output port parameters and the hardware circuit is adjusted by a custom algorithm formula, and the extracted data is divided to obtain the final output result; the custom algorithm formula is shown in equations (2)-(5) below:
[0053]
[0054] The algorithm performs shift addition and truncation compensation on the output ITGR of the decimator to finally obtain the output S of the CoI filter. out Specifically, ITGR is the output of the extractor. B is the shift value. H With B L These represent the high and low bits of the truncation range, respectively, SUM (B H B L ) refers to the truncation of SUM by B H To B L The range of data, SUM(B L-1 ) refers to the truncation of SUM at point B. L-1 Bit data; the truncation range is determined by the output data bit width B. out The value of B is calculated from the input and output port parameters. H B L These represent the high and low bits of the truncation, respectively; N is the number of CoI filter cascades; M is the decimation factor; D is the delay factor; B... in For the input data bit width, B L-1 The most significant bit is the rounding bit, where the rounding bit is the ratio of B. L Lower data bits, SUM (B H B L This refers to truncating SUM.
[0055] The following specific example illustrates the calculation process of the shift truncation divider in this embodiment:
[0056] Input bit width B in=1, integration delay D=1, filter cascade number N=2, downsampling rate M=128, output data bit width B out =16 bits, shift value The values are 1, 6, and 13 respectively; when the analog input value is half of the full scale (i.e., 0.5V), the integrator output ITGR = 8256 / 2 = 4128, and the shifted summation result is SUM = ITGR. 2 1 – ITGR / 2 6 + ITGR / 2 13 =8192, for SUM (B H B L The lower 16 bits of the above operator are truncated to obtain the binary number 0100 0000 0000 0000, which is represented as 0.5V. The above operator combines the special characteristics of the division operation of the CoI filter, that is, the output result is ∈ [-1,1].
[0057] In some of these embodiments, when the result SUM(B) is truncated... H B L The data bit width is less than the output data bit width B. out At that time, it is necessary to truncate the result SUM (B) H B L ) Shift left to make its data width equal to B out .
[0058] In some embodiments, depending on the different sampling multiples, i.e. downsampling rate M, it is necessary to set corresponding shift values and truncation ranges. Table 1 shows the data bit correspondence of shift, truncation and compensation under different downsampling rates according to the embodiments of this application.
[0059] Table 1
[0060]
[0061] Considering that the output range of the CoI decimation filter after dividing the integrator's output needs to be within [-1, 1], this embodiment maps the integrator's output to the range of [-1, 1] by using shift summation and truncation compensation. That is, the division operation is implemented through the combinational logic of the shift and truncation divider. This divider makes the CoI filter have high calculation accuracy, small area overhead, and short calculation cycle, which has comprehensive advantages.
[0062] This embodiment also provides a method for automatically generating the above-mentioned programmable CoI filter. Figure 3 This is a flowchart of a method for generating a programmable CoI filter according to an embodiment of this application, such as... Figure 3 As shown, the process includes the following steps:
[0063] Step S301: Preset the input and output port parameters of the CoI filter;
[0064] Preferably, in this embodiment, the input and output port parameters of the CoI filter are configured using a chisel script, wherein the input and output port parameters include the input bit width B. in The filter order N, the decimation factor M (downsampling rate), the delay factor D, and the output data bit width B are all factors to consider. out .
[0065] It should be noted that, in addition to the chisel language mentioned in this embodiment, other scripting languages can also be used to generate CoI filters.
[0066] Step S302: Configure the parameters of each sub-module in the filter according to the mapping relationship between the input and output port parameters and the hardware circuit, and automatically generate the CoI filter.
[0067] This embodiment determines the mapping relationship between input / output port parameters and hardware circuits based on the custom algorithm formula set in the shift truncation divider, and configures the parameters of each sub-module in the filter according to the mapping relationship, automatically generating the RTL code of the CoI filter hardware circuit. The sub-modules are encoder, integrator, decimator and shift truncation divider.
[0068] In some embodiments, an excitation is set, and the output of the CoI filter is verified by the excitation to determine whether the output is correct.
[0069] In some embodiments, during each M-clock transition cycle, the integrator's reset signal is active, causing the integrator to be set to zero. After the decimator extracts the integrator's calculation result for division, the completion flag is also active.
[0070] Through steps S301 to S302 above, this embodiment automatically generates the RTL code of the CoI filter by configuring the chisel script parameters. It can flexibly adjust the signal bandwidth, meet the diverse application requirements in the downconversion field, significantly improve module reusability, and reduce design time.
[0071] It should be noted that the steps shown in the above process or in the flowchart of the accompanying figures can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.
[0072] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.
[0073] Furthermore, it should be noted that the aforementioned modules can be either functional modules or program modules, and can be implemented through software or hardware. For modules implemented in hardware, these modules can reside in the same processor; alternatively, they can be located in different processors in any combination.
[0074] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0075] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A programmable CoI filter, characterized in that, The filter includes an encoder, an integrator, a decimator, and a shift truncation divider, wherein the shift truncation divider includes a shift adder and a truncation compensator. The encoder is used to encode the input analog-to-digital converter code streams of different bit widths; The integrator is used to perform integral calculations on the encoded data; The extractor is used to extract the calculation results of the integrator in each conversion cycle; The shift-truncation divider is used to adjust the mapping relationship between the input / output port parameters and the hardware circuit, perform division operations on the extracted data, and obtain the final output result. The specific steps include: The mapping relationship between input / output port parameters and hardware circuitry is adjusted by a custom algorithm formula. The extracted data is then divided to obtain the final output result. The custom algorithm formula is shown below: The algorithm performs shift addition and truncation compensation on the output ITGR of the decimator to finally obtain the output S of the CoI filter. out Specifically, ITGR is the output of the extractor. B is the shift value. H With B L These represent the high and low bits of the truncation range, respectively, SUM (B H B L ) refers to the truncation of SUM by B H To B L Data within the range, SUM(B) L-1 ) refers to the truncation of SUM at point B. L-1 Bit data; the truncation range is determined by the output data bit width B. out The value of B is calculated from the input and output port parameters. H B L These represent the high and low bits of the truncation, respectively; N is the number of CoI filter cascades; M is the decimation factor; D is the delay factor; B... in For the input data bit width, B L-1 The most significant bit is the rounding bit, where the rounding bit is the ratio of B. L Lower data bits, SUM (B H B L This refers to truncating SUM.
2. The filter according to claim 1, characterized in that, When the result SUM(B) is truncated H B L The data bit width is less than the output data bit width B. out At that time, the truncated result SUM (B H B L ) Move to the left.
3. The filter according to claim 1, characterized in that, Set the corresponding shift value and truncation range value according to different extraction multiples.
4. The filter according to claim 1, characterized in that, Encoding the bit width of the input analog-to-digital converter bitstream includes: The encoder encodes the input analog-to-digital converter bitstream data using an encoding algorithm to obtain the corresponding two's complement data. The encoding formula is as follows: B temp =N log2 M D +B in Where N is the number of CoI filter cascades, M is the decimation factor, D is the delay factor, Bin is the input data bit width, and B temp is the output data bit width of the Nth stage integrator.
5. The filter according to claim 4, characterized in that, Set the input data bit width to match the quantizer bit width of the incremental analog-to-digital converter, and set the CoI filter level N to match the order of the incremental analog-to-digital converter.
6. The filter according to claim 1, characterized in that, The integrator includes a reset signal. During each conversion cycle, the reset signal is activated once to zero out each integrator.
7. A method for generating a programmable CoI filter according to any one of claims 1-6, characterized in that, The method includes: Preset the input and output port parameters of the CoI filter; Based on the mapping relationship between input / output port parameters and hardware circuits, the parameters of each sub-module in the filter are configured to automatically generate a CoI filter.
8. The method according to claim 7, characterized in that, The method further includes: Set an excitation and verify the output of the CoI filter using the excitation.
9. The method according to claim 7, characterized in that, The CoI filter is automatically generated using a chisel configuration script.