Time synchronization operation method, module and data transmission device

Abstract

Embodiments of the present application provide a time synchronization operation method, a module and a data transmission device, wherein in the time synchronization operation method, the following steps are included: obtaining to-be-operated data, and storing the to-be-operated data into a preset storage device; wherein the address bit width of the preset storage device is smaller than the bit width of the to-be-operated data; determining an operation instruction corresponding to the to-be-operated data based on the operation mode of the to-be-operated data; wherein the operation instruction at least includes an effective storage address of the to-be-operated data, the effective storage address is a preset bit address of the storage address of the preset storage device, and the bit width of the operation instruction is smaller than the bit width of the to-be-operated data; and performing corresponding operation on the to-be-operated data stored in the preset storage device according to the indication of the operation instruction. The embodiments of the present application can reduce the requirement for hardware.

Description

Technical Field

[0001] This invention relates to the field of computer technology, specifically to a time synchronization operation method, module, and data transmission device. Background Technology

[0002] Time synchronization refers to the process of providing a unified time scale for independent modules in a data transmission link. In distributed systems or scenarios where data transmission is based on distributed protocols, time synchronization clarifies the sequence of events occurring in different modules, preventing confusion in the data processing flow. In the field of data transmission, such as in USB4 systems that support video data transmission, in a time synchronization process based on a distributed protocol, the slave router needs to calculate information such as the master router's time, time offset, and frequency offset according to the time synchronization protocol to achieve time synchronization.

[0003] However, existing time synchronization solutions have excessively high hardware requirements. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a time synchronization operation method, module, and data transmission device, which can reduce the hardware requirements.

[0005] To address the above problems, embodiments of the present invention provide the following technical solutions:

[0006] In a first aspect, embodiments of the present invention provide a time synchronization operation method, including:

[0007] Acquire the data to be processed and store the data to be processed in a preset storage device; wherein the address width of the preset storage device is smaller than the address width of the data to be processed;

[0008] Based on the operation method of the data to be operated, an operation instruction corresponding to the data to be operated is determined; wherein, the operation instruction includes at least the effective storage address of the data to be operated, the effective storage address is a preset bit address of the storage address of the preset storage device, and the bit width of the operation instruction is smaller than the bit width of the data to be operated;

[0009] According to the valid storage address indicated by the operation instruction, the data to be operated on is processed in the preset storage device.

[0010] Optionally, the preset storage device includes a special register, in which N low-order bits are non-zero and the remaining high-order bits are zero. The effective storage address of the special register is the first N low-order bits of the special register, where N is less than the number of bits in the complete storage address of the special register.

[0011] Optionally, storing the data to be processed in a preset storage device includes storing the data to be processed in a special register whose effective storage address is the first N least significant bits of the special register.

[0012] Optionally, the step of performing corresponding operations on the data to be operated on stored in the preset storage device according to the valid storage address indicated by the operation instruction includes:

[0013] Based on the valid storage address indicated by the arithmetic instruction, determine the position of the valid storage address in the special register;

[0014] Retrieve the data to be processed stored in the special register;

[0015] The data to be processed is processed according to the processing method indicated by the processing instruction to obtain the corresponding processing result.

[0016] Optionally, the operation instruction further includes a valid storage address for the operation result, and the step of performing a corresponding operation on the data to be operated stored in the preset storage device according to the valid storage address indicated by the operation instruction further includes:

[0017] The calculation result is stored in the special register at the location corresponding to the effective storage address of the calculation result.

[0018] Optionally, the preset storage device includes a general-purpose register, the address width of which is smaller than the address width of the special register, and the effective storage address of the general-purpose register is the complete storage address of the general-purpose register;

[0019] The step of storing the data to be processed into a preset storage device includes:

[0020] The data to be processed is stored in a special register where the high-order address is non-zero.

[0021] The first load instruction is invoked to load the data to be processed stored in the special register into the general-purpose register;

[0022] The first load instruction contains the complete storage address of the data to be processed in the special register.

[0023] Optionally, the step of performing corresponding operations on the data to be operated on stored in the preset storage device according to the valid storage address indicated by the operation instruction includes:

[0024] Based on the valid storage address indicated by the arithmetic instruction, determine the location of the valid storage address in the general-purpose register;

[0025] Obtain the data to be processed stored in the general-purpose register;

[0026] The data to be processed is processed according to the processing method indicated by the processing instruction to obtain the corresponding processing result.

[0027] Optionally, the operation instruction further includes a valid storage address for the operation result, and the step of performing a corresponding operation on the data to be operated stored in the preset storage device according to the valid storage address indicated by the operation instruction further includes:

[0028] The calculation result is stored in the general-purpose register at the location corresponding to the effective storage address.

[0029] Optionally, after the step of performing corresponding operations on the data to be operated on stored in the preset storage device according to the valid storage address indicated by the operation instruction, the method further includes:

[0030] Invoke the first store instruction to store the operation result in the general-purpose register into the special register;

[0031] The first storage instruction contains the complete storage address of the operation result in the special register.

[0032] Optionally, when performing operations with immediate values, the operation instruction includes M low-order bits of the immediate value, where M is smaller than the bit width of the immediate value;

[0033] The step of performing corresponding operations on the data to be processed stored in the preset storage device according to the valid storage address indicated by the operation instruction includes:

[0034] The immediate value in the operation instruction is padded with zeros at the high bits to form an immediate value with the same bit width as the data to be operated on.

[0035] According to the operation method indicated by the operation instruction, the data to be operated on and the immediate value to be operated on are operated on to obtain the operation result;

[0036] Store the calculation result at the immediate result storage address;

[0037] The immediate value result is stored at a preset fixed storage address.

[0038] Optionally, when performing operations with immediate values, the following is also included:

[0039] The second store instruction is invoked to store the immediate value at the location of the special register corresponding to the effective storage address indicated by the second store instruction;

[0040] The immediate value in the special register is padded with zeros at the high bits.

[0041] Optionally, when performing operations with immediate values, the following is also included:

[0042] The second load instruction is invoked to store the immediate value at the location of the general-purpose register corresponding to the effective memory address indicated by the second load instruction;

[0043] The immediate value in the general-purpose register is padded with zeros at the high bits.

[0044] Secondly, embodiments of the present invention provide a time synchronization computing module, comprising:

[0045] A preset storage device is used to store data to be processed, wherein the address width of the preset storage device is smaller than the address width of the data to be processed;

[0046] A state machine is used to determine the operation instruction corresponding to the data to be operated based on the operation method of the data to be operated; wherein the operation instruction includes at least the valid storage address of the data to be operated, the valid storage address is a preset bit address of the storage address of the preset storage device, and the bit width of the operation instruction is smaller than the bit width of the data to be operated;

[0047] The arithmetic unit is used to perform corresponding operations on the data to be processed stored in the preset storage device according to the valid storage address of the arithmetic instruction.

[0048] Optionally, the preset storage device includes a special register, in which N low-order bits are non-zero and the remaining high-order bits are zero. The effective storage address of the special register is the first N low-order bits of the special register, where N is less than the number of bits in the complete storage address of the special register.

[0049] Optionally, the operation instruction further includes a valid storage address for the operation result, which is used to indicate the location in the special register corresponding to the valid storage address of the operation result.

[0050] Optionally, the preset storage device includes a general-purpose register, the address width of which is smaller than the address width of the special register, and the effective storage address of the general-purpose register is the complete storage address of the general-purpose register.

[0051] Optionally, the operation instruction further includes a valid storage address for the operation result, which is used to indicate the location in the general-purpose register corresponding to the valid storage address of the operation result.

[0052] Optionally, there are multiple state machines, and the time synchronization operation module further includes: instruction cache, memory access arbitration, and operation arbitration;

[0053] The instruction cache is used to cache the instructions required in the time synchronization operation process;

[0054] The memory access arbitration is used to determine the state machine that allows access to the instruction cache at the same time.

[0055] The computational arbitration is used to determine the arithmetic units that are allowed to be scheduled by the state machine at the same time;

[0056] The general-purpose registers are configured in correspondence with the state machine, and the special-purpose registers are configured in correspondence with the state machine.

[0057] Optionally, the time synchronization operation module executes the instruction processing flow based on a wake-up mechanism.

[0058] Optionally, in the special registers, the special registers at each address are used to store the corresponding preset parameters.

[0059] Optionally, in the preset storage device, the special registers and general-purpose registers have different data operation methods.

[0060] Thirdly, embodiments of the present invention provide a data transmission device, comprising:

[0061] The routing module is used for data transmission;

[0062] The time synchronization operation module described in this embodiment of the invention.

[0063] This invention provides a time synchronization operation method, module, and data transmission device. The time synchronization operation method includes: acquiring data to be operated on; storing the data to be operated on in a preset storage device; wherein the address width of the preset storage device is smaller than the address width of the data to be operated on; determining an operation instruction corresponding to the data to be operated on based on the operation method of the data to be operated on; wherein the operation instruction includes at least a valid storage address of the data to be operated on, the valid storage address being a preset bit address of the storage address of the preset storage device, and the address width of the operation instruction being smaller than the address width of the data to be operated on; and performing a corresponding operation on the data to be operated on stored in the preset storage device according to the operation instruction.

[0064] As can be seen, in this embodiment of the invention, the data to be processed is stored in a preset storage device with an address width smaller than the width of the data to be processed. Simultaneously, the width of the processing instructions is also smaller than the width of the data to be processed. This reduces the hardware bit width requirements of the processing from the perspective of instruction execution (i.e., system operation), thereby reducing the requirements on hardware complexity. Correspondingly, it reduces the chip area occupied and the power consumption, thus lowering the overall hardware requirements. For example, the method provided in this embodiment of the invention can be used to implement 64-bit or 80-bit data operations using a 16-bit system, thereby reducing the hardware requirements for time-synchronized operations. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0066] Figure 1 This is a schematic diagram of a USB4 data transmission architecture;

[0067] Figure 2 A schematic diagram of an optional structure for a time synchronization information processing architecture provided in an embodiment of the present invention;

[0068] Figure 3 A schematic diagram of an optional process for a time synchronization operation method provided in an embodiment of the present invention;

[0069] Figure 4 An optional flowchart of step S120 provided in an embodiment of the present invention;

[0070] Figure 5 A schematic diagram of an optional structure for an arithmetic instruction provided in an embodiment of the present invention;

[0071] Figure 6 An optional flowchart of step S100 provided in an embodiment of the present invention;

[0072] Figure 7 This is a schematic diagram of an optional structure for a first loading instruction provided in an embodiment of the present invention;

[0073] Figure 8 Another optional flowchart for step S120 provided in an embodiment of the present invention;

[0074] Figure 9 This is a schematic diagram of another optional structure of an arithmetic instruction provided in an embodiment of the present invention;

[0075] Figure 10A schematic diagram of an optional structure for a first storage instruction provided in an embodiment of the present invention;

[0076] Figure 11 This is another optional flowchart of step S120 provided in an embodiment of the present invention;

[0077] Figure 12 This is a schematic diagram of another optional structure of an arithmetic instruction provided in an embodiment of the present invention;

[0078] Figure 13 An optional flowchart for saving immediate values ​​provided in an embodiment of the present invention;

[0079] Figure 14 This is an optional structure diagram of the second storage instruction provided in an embodiment of the present invention;

[0080] Figure 15 This is an optional flowchart for loading immediate values ​​according to an embodiment of the present invention;

[0081] Figure 16 An optional structure diagram of the second loading instruction provided in an embodiment of the present invention;

[0082] Figure 17 This is an optional structural diagram of a time synchronization module provided in an embodiment of the present invention;

[0083] Figure 18 This is a schematic diagram of an optional structure of a general-purpose register provided in an embodiment of the present invention. Detailed Implementation

[0084] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0085] As described in the background section, existing time synchronization solutions have excessively high hardware requirements.

[0086] Taking the USB4 data transfer protocol, which uses a distributed protocol for time synchronization, as an example, refer to... Figure 1The diagram illustrates the USB4 data transmission architecture. Data is transmitted between the Downstream Facing Part (DFP) and the Upstream Facing Part (UFP). The DFP can be understood as a host, its key characteristic being that it acts as a power source, supplying power to VBUS and vcon. The UFP can be understood as a device, its key characteristic being that it acts as a powered port, drawing power from VBUS and providing data. Typical UFP devices include USB flash drives and external hard drives. In some transmission links, the upstream port can also be understood as a downstream port acting as an IDTI (InterDomain Time Initiator) time synchronization initiator.

[0087] The UFP can include a routing module (also known as a slave router) for data transmission and a time synchronization unit (TMU) for processing time synchronization protocols. The slave router performs protocol layer data processing, while the time synchronization unit performs computation layer data processing of time synchronization parameters, thereby synchronizing the device's time based on the time synchronization parameters. In some optional examples, the time synchronization unit can be a microcontroller unit (MCU).

[0088] However, the data to be processed for time synchronization is typically 64-bit or 80-bit, and correspondingly, the microcontroller unit used for time synchronization needs to support 64-bit or 80-bit data operations. In this case, the corresponding microcontroller unit is usually adaptively configured as a 64-bit or 80-bit system to support 64-bit or 80-bit data operations.

[0089] However, configuring a 64-bit or 80-bit system requires corresponding 64-bit or 80-bit hardware, which increases the complexity of the hardware, the area occupied by the chip, and the power consumption, resulting in higher overall hardware requirements.

[0090] In view of this, embodiments of the present invention provide a time synchronization operation method, a module, and a data transmission device. The time synchronization operation method includes: acquiring data to be operated on; storing the data to be operated on in a preset storage device; wherein the address width of the preset storage device is smaller than the address width of the data to be operated on; determining an operation instruction corresponding to the data to be operated on based on the operation method of the data to be operated on; wherein the operation instruction includes at least a valid storage address of the data to be operated on, the valid storage address being a preset bit address of the storage address of the preset storage device, and the address width of the operation instruction being smaller than the address width of the data to be operated on; and performing a corresponding operation on the data to be operated on stored in the preset storage device according to the instruction.

[0091] As can be seen, in this embodiment of the invention, the data to be processed is stored in a preset storage device with an address width smaller than the width of the data to be processed. Simultaneously, the width of the processing instructions is also smaller than the width of the data to be processed. This reduces the hardware bit width requirements of the processing from the perspective of instruction execution (i.e., system operation), thereby reducing the requirements on hardware complexity. Correspondingly, it reduces the chip area occupied and the power consumption, thus lowering the overall hardware requirements. For example, the method provided in this embodiment of the invention can be used to implement 64-bit or 80-bit data operations using a 16-bit system, thereby reducing the hardware requirements for time-synchronized operations.

[0092] As an optional implementation of the content disclosed in the embodiments of the present invention, Figure 2 The diagram illustrates an optional structure of a time synchronization information processing architecture provided by an embodiment of the present invention. This architecture may include a protocol layer, a synchronization storage device, and a computation layer. Specifically, after the protocol layer obtains the corresponding time synchronization information, it can store the data to be processed in the synchronization storage device, and the computation layer can then obtain the data to be processed based on the synchronization storage device and perform corresponding computations. In an optional example, the synchronization storage device may be, for example, a status / control register.

[0093] The computation layer, specifically the time synchronization computation module, is used to perform calculations on time synchronization parameters. The computation layer (i.e., the time synchronization computation module) may include a state machine 21, a preset storage device 22, and a computation unit 23. The state machine 21 is used to invoke instructions, thereby controlling the overall flow of the time synchronization computation. The preset storage device 22 stores the corresponding data to be computed and the computation results, such as time synchronization information and time synchronization parameters. The computation unit 23 performs calculations on the data to be computed based on corresponding instructions to obtain the computation results. In an optional example, the time synchronization computation module can be implemented based on an instruction set architecture (ISA), specifically, for example, a 16-bit instruction set architecture.

[0094] As an optional implementation of the content disclosed in the embodiments of the present invention, Figure 3 The diagram illustrates an optional flowchart of a time synchronization operation method provided by an embodiment of the present invention. The time synchronization operation method can be applied to the operation layer, i.e., the time synchronization operation module provided by the embodiment of the present invention. (Refer to...) Figure 3 The method includes:

[0095] Step S100: Obtain the data to be processed and store the data to be processed in a preset storage device; wherein the address width of the preset storage device is smaller than the address width of the data to be processed;

[0096] The data to be processed can be understood as data used for time synchronization calculation. The data to be processed may include timestamps used for time synchronization and time offset information corresponding to the timestamps. The time offset information may include one or more of the following: time offset of intra-domain host routers, frequency offset of intra-domain host routers, inter-domain timestamps, time offset of time source host routers, and frequency offset of time source host routers.

[0097] The timestamp is used to indicate the time corresponding to a specific object at a specific moment. For example, the timestamp can indicate the moment when the UFP inserts the Time Sync Notification Ordered Set (TSNOS) in the time synchronization process, recorded as t1 for the time of the UFP at that moment, or the moment when the UFP obtains the TSNOS request returned by the DFP, recorded as t4 for the time of the UFP at that moment; or the timestamp can indicate the moment when the DFP obtains the TSNOS request sent by the UFP in the time synchronization process, recorded as t2 for the time of the DFP at that moment, or the moment when the DFP returns the TSNOS request, recorded as t3 for the time of the DFP at that moment.

[0098] The time offset of an intra-domain host router (which can be denoted as TimeOffsetFromHR) can be understood as the time offset compared to other intra-domain host routers; the frequency offset of an intra-domain host router (which can be denoted as FreqOffsetFromHR) can be understood as the frequency offset compared to other intra-domain host routers; the inter-domain timestamp (which can be denoted as IDTimeStamp) can be understood as the timestamp between different time domains; the time offset of the time source host router (which can be denoted as TimeOffsetFromInterDomain) can be understood as the time offset compared to the time source host router; the frequency offset of the time source host router (which can be denoted as FreqOffsetFromInterDomain) can be understood as the frequency offset compared to the time source host router.

[0099] The preset storage device is a device for data storage. It can be used to store data to be processed or to store the results of processing the data. The address width of the preset storage device is smaller than the address width of the data to be processed. For example, when the data to be processed is 64 bits or 80 bits, the address width of the preset storage device can be 8 bits, or even 3 or 4 bits, thus enabling the processing of large-width data with a smaller address width.

[0100] In an optional example, the time synchronization operation module can acquire the data to be operated based on the synchronization storage device and store the data to be operated on the preset storage device, thereby realizing the operation of time synchronization parameters based on this data to be operated.

[0101] Step S110: Based on the operation method of the data to be operated, determine the operation instruction corresponding to the data to be operated; wherein, the operation instruction includes at least the effective storage address of the data to be operated, the effective storage address is the preset bit address of the storage address of the preset storage device, and the bit width of the operation instruction is smaller than the bit width of the data to be operated;

[0102] After acquiring the data to be processed, the processing method of the data to be processed can be determined based on its content, and then the processing instruction corresponding to the data to be processed can be determined based on the processing method of the data to be processed.

[0103] It is understandable that the time synchronization parameters can be calculated according to a preset formula. Correspondingly, after obtaining the data to be processed, the corresponding calculation method can be obtained based on the preset formula. The calculation method may include addition, subtraction, multiplication, division, left shift, right shift, etc., of the data.

[0104] The operation instruction includes a valid storage address for the data to be operated on, which serves as the source address to read the corresponding data for operation. In a further optional example, the operation instruction may also include a valid storage address for the operation result, which serves as the target address to store the operation result.

[0105] The effective storage address is the preset bit address of the storage address of the preset storage device. That is, in this embodiment of the invention, the operation instruction does not necessarily need to store the complete storage address of the preset storage device, so that the operation instruction can indicate the corresponding source address and target address with a lower bit width.

[0106] In this embodiment of the invention, the bit width of the operation instruction is further configured to be smaller than the bit width of the data to be operated on, thereby reducing the hardware bit width requirements of the operation process from the perspective of instruction execution (i.e. system operation).

[0107] In a specific example, the bit width of the data to be processed can be 64 bits or 80 bits, while the processing instruction described in this embodiment of the invention can be 16 bits, thereby achieving data processing with a higher bit width with a lower instruction bit width.

[0108] Step S110 can be implemented using a state machine. In the time synchronization operation module, this manifests as the state machine executing step S110 and calling the corresponding operation instruction.

[0109] Step S120: Perform corresponding operations on the data to be operated on stored in the preset storage device according to the valid storage address indicated by the operation instruction;

[0110] After determining the corresponding operation instructions, the corresponding operation process can be executed to obtain the corresponding operation result.

[0111] Step S120 can be implemented by a processing unit. In the time synchronization processing module, this manifests as the processing unit executing the corresponding processing instructions.

[0112] As can be seen, in this embodiment of the invention, the data to be processed is stored in a preset storage device with an address width smaller than the width of the data to be processed. At the same time, the width of the processing instruction is also smaller than the width of the data to be processed. This reduces the hardware width requirement of the processing process from the perspective of instruction execution (i.e. system operation), thereby reducing the requirements for hardware complexity. Correspondingly, it reduces the chip area occupied by the hardware and the power consumption, thus reducing the overall hardware requirements.

[0113] In a specific example, the time synchronization operation module may be configured with special registers, and the preset storage device may include these special registers. The special registers can be used to implement data interaction with the synchronization storage device. Specifically, to enable the time synchronization operation module in this embodiment to simultaneously adapt to operations on data of different bit widths (e.g., simultaneously adapting to 64-bit and 80-bit data operations), the special registers may include a first storage area and a second storage area, wherein the data storage bit width of the first storage area is different from that of the second storage area. For example, the first storage area may store 80-bit data, and the second storage area may store 64-bit data.

[0114] The address width of the special register is smaller than the width of the data to be processed, for example, it can be 8 bits. In an optional example, in the region where N low-order bits of the special register are non-zero and the remaining high-order bits are zero, the effective storage address of the special register is the first N low-order bits of the special register, where N is smaller than the number of bits in the complete storage address of the special register. For example, N can be 4, so when the first 4 low-order bits of the special register are non-zero and the remaining 4 high-order bits are 0, the corresponding first 4 low-order bits can be used as the effective storage address of the special register. For example, when the storage address of the special register is 00000110, its corresponding effective storage address is 0110.

[0115] It should be noted that the high-order address and low-order address of a storage address refer to the address bits on different sides of the storage address. The high-order address refers to the address bits on the left side of the storage address, and the low-order address refers to the address bits on the right side of the storage address. Further, in this embodiment of the invention, the number of bits occupied by the high-order address and the low-order address can be understood as at least one bit. When the high-order address is at least one bit, the remaining address bits can be considered as the low-order address; when the low-order address is at least one bit, the remaining address bits can be considered as the high-order address.

[0116] It is understandable that using a portion of the preset bit address of the storage address as the effective storage address can further reduce the number of bits in the storage address, thereby further reducing the number of bits in the arithmetic instructions used to indicate the storage address.

[0117] In this embodiment of the invention, the first storage area can be further configured as the area in the special register where the N low-order addresses are non-zero and the remaining high-order addresses are zero, and the second storage area is the remaining area in the special register.

[0118] Furthermore, in the optional flow of the time synchronization operation method, in step S100, the data to be operated on can be stored in a special register whose effective storage address is the first N least significant bits of the special register, i.e., the first storage area. In step S120, according to the effective storage address indicated by the operation instruction, the data to be operated on stored in the preset storage device is subjected to corresponding operations, referring to... Figure 4 The illustrated optional flowchart for step S120 shows that step S120 may include:

[0119] Step S121: Determine the position of the valid storage address in the special register according to the valid storage address indicated by the arithmetic instruction;

[0120] During data operations on the first storage area, the effective storage address indicated by the operation instruction is the first N least significant bits of the special register. The complete storage address of the corresponding special register is: the most significant bit is zero, and the N least significant bits are the effective storage address indicated by the operation instruction. Accordingly, based on the effective storage address, the position of the effective storage address within the special register can be determined.

[0121] refer to Figure 5 The diagram shows an optional structure of an arithmetic instruction, which includes the effective storage addresses of the source address SR1[3:0] (bits 0 to 3 in the diagram, labeled SR1) and SR2[3:0] (bits 4 to 7 in the diagram, labeled SR2), and the arithmetic mode CT1 (bits 12 to 15 in the diagram, labeled CT1).

[0122] Continue to refer to Figure 4 Step S122: Obtain the data to be processed stored in the special register;

[0123] After determining the address of the data to be processed in the special register, the data to be processed stored in the special register can be retrieved.

[0124] Step S123: Perform calculations on the data to be calculated based on the calculation method indicated by the calculation instruction to obtain the corresponding calculation result.

[0125] It is understandable that the operation instruction can indicate the operation method for the corresponding data to be operated on, so that the data to be operated on can be operated on based on the operation method indicated by the operation instruction to obtain the corresponding operation result.

[0126] In an embodiment of the present invention, reference is made to Figure 5The operation instruction may further include the effective storage address SR3[3:0] (bits 8 to 11 in the figure, marked as SR3) of the operation result. The effective storage address of the operation result is used to indicate the location in the special register corresponding to the effective storage address of the operation result. Accordingly, step S120 may further include:

[0127] Continue to refer to Figure 4 Step S124: Store the calculation result in the special register corresponding to the effective storage address of the calculation result.

[0128] Correspondingly, the effective storage address in the arithmetic instruction is the first N least significant bits of the special register, and the complete storage address of the special register is such that the most significant bits are zero, and the N least significant bits are the effective storage address indicated by the arithmetic instruction. Accordingly, the arithmetic result can be stored in the special register at the location corresponding to the effective storage address of the arithmetic result.

[0129] by Figure 5 Taking the 80-bit addition operation mode CT1 as an example, the special register indicated by SR3[3:0] is used to store the sum of the data in the special register indicated by SR1[3:0] and the data in the special register indicated by SR2[3:0].

[0130] In a further optional example, special registers at different addresses store fixed parameters; that is, each special register at a specific address stores a corresponding preset parameter. It should be noted that these parameters do not refer to specific data, but rather to data that plays a fixed role in the instruction processing flow. These parameters can be, for example, timestamps. For instance, special registers at addresses 0x00 to 0x0f can be used to cache timestamps to be processed (e.g., t1 to t4) and time synchronization parameters. When the bit width of the timestamp information and time synchronization parameters is 80 bits, 80-bit integer addition and subtraction operations can be performed based on this address. Special registers at addresses 0x10 to 0x1f can be used to cache calculated frequency ratios, frequency offsets, and time offsets, with a corresponding bit width of 64 bits. The results of formulas calculated in general-purpose registers can be cached here for use in subsequent calculations. Special registers at addresses 0x20 to 0x3f can be used for mapping with synchronization storage devices in the special register address space. These synchronization storage devices are the interface registers between the time synchronization operation module and the protocol layer.

[0131] In a further specific example, operations can also be performed on the data in the second storage area of ​​the special register. To meet the requirement that the operation instructions are always at a low bit width, this embodiment of the invention further configures a general-purpose register with a smaller address bit width in the time synchronization operation module, thereby transferring the data in the second storage area of ​​the special register (i.e., the area in the special register where the high-order address is non-zero) to the general-purpose register to adapt to the bit width requirements of the operation instructions.

[0132] The address width of the general-purpose register can be smaller than that of the special register. Since the address width of the general-purpose register is already small enough, the effective storage address of the general-purpose register is the complete storage address of the general-purpose register.

[0133] In a specific example, a general-purpose register can store 64-bit data, and the address width of the general-purpose register can be 3 bits.

[0134] In the optional flow of the time synchronization operation method, refer to Figure 6 The optional flowchart of step S100 shown includes the process of storing the data to be processed to a preset storage device, which may include:

[0135] Step S101: Store the data to be processed in the region of the special register where the high-order address is non-zero;

[0136] Here, the high-order address refers to the address bits remaining after the first N low-order bits in the special register. The region in the special register where the high-order address is non-zero corresponds to the second storage region. It is understood that because the high-order address is non-zero, this region is not suitable for schemes where the effective storage address is the first N low-order bits.

[0137] It is understandable that, in order to ensure that the data flow process is consistent with the aforementioned embodiments, the data to be processed can first be stored in a special register, and then the data flow can be further carried out based on the special register.

[0138] Step S102: Call the first load instruction to load the data to be processed stored in the special register into the general register.

[0139] After storing the data to be processed in a special register, the data to be processed stored in the special register can be loaded into the general-purpose register.

[0140] Based on the fact that the high-order address of the data to be processed is non-zero in the special register (the second storage area), the first load instruction can include the complete storage address of the data to be processed in the special register, thereby achieving accurate loading of the data.

[0141] refer to Figure 7 The diagram shows an optional structure of a first load instruction, which includes the complete storage address SR0 of the source address to be loaded (bits 0-7 in the diagram), the target address RS0 to be loaded (bits 8-10 in the diagram), and the instruction processing mode IT1.

[0142] It is understandable that the storage address based on the general-purpose register itself has a low bit width. Therefore, even if the first load instruction contains the complete storage address of the data to be processed, the data can still be transferred while ensuring a low bit width.

[0143] Corresponding to the general-purpose register described in the embodiments of the present invention, in the optional process of the time synchronization operation method, refer to Figure 8 Another optional flowchart of step S120 is shown, which may include:

[0144] Step S221: Determine the location of the valid storage address in the general-purpose register according to the valid storage address indicated by the arithmetic instruction;

[0145] In this embodiment, the effective storage address is the complete storage address of the general-purpose register. Correspondingly, the effective storage address indicated by the operation instruction is the storage address of the general-purpose register. Thus, based on the storage address of the general-purpose register, the location of the data to be operated on in the general-purpose register can be determined.

[0146] refer to Figure 9 The diagram shows another optional structure of an operation instruction, which includes the effective storage addresses RS1 (bits 0-2 in the diagram) and RS2 (bits 3-5 in the diagram) of the source address, as well as the operation mode CT2 (bits 9-15 in the diagram, labeled CT2).

[0147] Continue to refer to Figure 8 Step S222: Obtain the data to be processed stored in the general-purpose register;

[0148] After determining the location of the data to be processed in the general-purpose register, the data to be processed stored in the general-purpose register can be obtained.

[0149] Step S223: Perform calculations on the data to be calculated based on the calculation method indicated by the calculation instruction to obtain the corresponding calculation result.

[0150] It is understandable that the operation instruction can indicate the operation method for the corresponding data to be operated on, so that the data to be operated on can be operated on based on the operation method indicated by the operation instruction to obtain the corresponding operation result.

[0151] In an embodiment of the present invention, reference is made to Figure 9 The arithmetic instruction may further include the effective storage address RS3 (bits 6-8 in the figure) of the arithmetic result. This effective storage address indicates the location in the general-purpose register corresponding to the effective storage address of the arithmetic result. Accordingly, continue to refer to... Figure 8 Step S120 may further include:

[0152] Step S224: Store the calculation result at the location in the general-purpose register corresponding to the effective storage address of the calculation result.

[0153] Correspondingly, the effective storage address in the operation instruction is the complete storage address of the general-purpose register. Accordingly, the operation result can be stored at the location in the general-purpose register corresponding to the effective storage address of the operation result.

[0154] by Figure 9 Taking the CT2 instruction as a 64-bit addition operation as an example, the general-purpose register indicated by RS3 is used to store the sum of the data in the general-purpose register indicated by RS1 and the data in the general-purpose register indicated by RS2.

[0155] It is understandable that when the calculation result is a time synchronization parameter, the calculation result can be further stored in a special register, thereby transferring the calculation result to a synchronization storage device. Accordingly, please refer to [reference needed]. Figure 8 Step S120 may further include:

[0156] Step S225: Invoke the first storage instruction to store the operation result in the general-purpose register into the special register;

[0157] After storing the calculation result in a general-purpose register, the calculation result stored in the general-purpose register can be stored in the special register.

[0158] The data to be processed can be stored in the region where the high-order address is non-zero in the special register (the second storage region), or it can be stored in the region where the high-order address is zero and the N low-order addresses are non-zero in the special register (the first storage region). Therefore, the first storage instruction contains the complete storage address of the operation result in the special register, thereby achieving accurate loading of the data.

[0159] refer to Figure 10The diagram shows an optional structure of a first storage instruction, which includes the complete storage address RSn of the source address to be stored (bits 8-10 in the diagram), the target address SRn of the storage (bits 0-7 in the diagram), and the instruction processing mode IT2.

[0160] It is understandable that the storage address based on the general-purpose register itself has a low bit width. Therefore, even if the first load instruction contains the complete storage address of the operation result, the data can still be transferred while ensuring a low bit width.

[0161] It's important to note that to distinguish between special registers and general-purpose registers in arithmetic instructions, different data operation methods can be configured based on different registers. In other words, special registers and general-purpose registers correspond to different data operation methods. For example, calculation instructions can differentiate between different bit-width operation methods. For instance, 80-bit and 64-bit operation methods use different instruction data. When dealing with 80-bit operation methods, the address in the configuration instruction is fixed to the address of a special register; when dealing with 64-bit operation methods, the address in the configuration instruction is fixed to the address of a general-purpose register. Therefore, in 80-bit operation methods, the system automatically determines the effective storage address in the arithmetic instruction to be the address of a special register, identifies the location of that effective storage address in the special register, and then retrieves the corresponding data to be operated on. Similarly, in 64-bit operation methods, the system automatically determines the effective storage address in the arithmetic instruction to be the address of a general-purpose register, identifies the location of that effective storage address in the general-purpose register, and then retrieves the corresponding data to be operated on.

[0162] In a further example, embodiments of the present invention also provide a corresponding computational flow when performing operations with immediate values. Specifically, to meet the requirement that the computation instruction has a low bit width, the computation instruction may include an immediate value consisting of a portion of the data bits. In an optional example, the computation instruction includes M low-order bits of the immediate value. Here, M is less than the bit width of the immediate value, thereby achieving operations with immediate values ​​using a smaller bit width. For example, the bit width of the immediate value is 64 bits, and M is 6.

[0163] Accordingly, refer to Figure 11 Another optional flowchart of step S120 shown may include:

[0164] Step S321: Pad the immediate value in the operation instruction with zeros at the high bits to form an immediate value with the same bit width as the data to be operated on;

[0165] To ensure that the bit width of the immediate value to be computed is the same as the bit width of the data to be computed, the high-order bits of the immediate value in the computation instruction can be padded with zeros. For example, the 6-bit immediate value in the computation instruction can be padded with zeros to form a 64-bit immediate value to be computed.

[0166] Step S322: Perform calculations on the data to be calculated and the immediate value to be calculated according to the calculation method indicated by the calculation instruction to obtain the calculation result;

[0167] The operation method indicated by the operation instruction may include addition, subtraction, multiplication, division, left shift, right shift, etc., of the immediate value to be operated on and the data to be operated on, thereby performing operations on the data to be operated on and the immediate value to be operated on based on the operation method.

[0168] refer to Figure 12 The diagram shows another optional structure of the arithmetic instruction. This instruction includes the immediate value immediate1 (bits 0-5 in the diagram), the source address RS4 (bits 6-8 in the diagram), and the arithmetic mode CT3 (bits 9-15 in the diagram). In this example, taking 64-bit arithmetic as an example, firstly, the high-order bits of immediate1 are padded with zeros to form a 64-bit immediate value to be calculated. Then, the immediate value to be calculated is performed on the data to be calculated indicated by the source address RS4 to obtain the corresponding calculation result. Taking CT3 indicating immediate value addition as an example, this instruction instructs the arithmetic unit to add the immediate value to be calculated to the data to be calculated indicated by the source address RS4.

[0169] It should be noted that operations involving immediate values ​​can be categorized as a different type of operation compared to the aforementioned 64-bit and 80-bit operations, as they correspond to different instruction data. For example, 64-bit addition and 80-bit addition operations correspond to different instruction data, and addition with immediate values ​​also has different instruction data than the 64-bit and 80-bit addition operations. Therefore, different types of operations can be distinguished based on the instruction data.

[0170] Continue to refer to Figure 11 Execute step S323: Store the calculation result to the immediate result storage address;

[0171] To allow more bits of immediate value to be reserved in the operation instructions, a fixed storage address can be set as the storage address of the immediate value result. Thus, the target address of the corresponding operation does not need to be specified in the operation instructions, thereby freeing up more space to be allocated to the immediate value.

[0172] Accordingly, after obtaining the calculation result, the calculation result can be stored in a fixed immediate result storage address.

[0173] It should be further noted that when performing operations with immediate values, the immediate values ​​can also be saved. For details, please refer to [reference needed]. Figure 13 The flowchart shown illustrates an optional process for storing immediate values. The time synchronization calculation method may further include:

[0174] Step S200: Invoke the second store instruction to store the immediate value in the location of the special register corresponding to the effective storage address indicated by the second store instruction;

[0175] Specifically, by storing the immediate value to the location pointed to by the effective storage address of the special register, more bits of the immediate value are reserved in the second store instruction.

[0176] Understandably, in order to ensure that immediate values ​​occupy more bit width, the storage address indicated in the second storage instruction is the effective storage address of a special register, so as to reduce the bit width occupied by the storage address of the special register.

[0177] refer to Figure 14 The diagram shows an optional structure of the second storage instruction, which includes the immediate value immediate2 (bits 0-5 in the diagram), the target address SR5[3:0] (bits 6-9 in the diagram), and the instruction processing mode IT3 (bits 10-15 in the diagram).

[0178] Continue to refer to Figure 13 Step S201: Pad the immediate value in the special register with zeros at the high bits.

[0179] After storing the immediate value, it can be padded with zeros in the high bits to make the immediate value complete.

[0180] In this invention, steps S200 and S201 can be performed before or after the process provided in the foregoing embodiments, and no specific limitation is made here. It is understood that operations with immediate values ​​can be used to clear and set special registers. For example, an immediate value can be set to 0 or 1 and then saved to a special register.

[0181] It should be further noted that immediate values ​​can also be loaded when performing operations with immediate values. For details, please refer to [reference needed]. Figure 15 The optional flowchart shown illustrates loading immediate values. The time synchronization calculation method may further include:

[0182] Step S203: Invoke the second load instruction to store the immediate value at the location of the general-purpose register corresponding to the effective memory address indicated by the second load instruction;

[0183] Since the address width of the general-purpose register is relatively small, the effective storage address is the complete storage address of the general-purpose register.

[0184] refer to Figure 16 The diagram shows an optional structure of the second load instruction, which includes the immediate value immediate3 (bits 0-5 in the diagram), the target address RS5 (bits 6-8 in the diagram), and the instruction processing mode IT4 (bits 9-15 in the diagram).

[0185] Continue to refer to Figure 15 Step S204: Pad the immediate value in the general-purpose register with zeros at the high bits.

[0186] After loading the immediate value, it can be padded with zeros in the high bits to make the immediate value complete.

[0187] In this invention, steps S203 and S204 can be performed before or after the process provided in the foregoing embodiments, and no specific limitation is made here.

[0188] It is understood that the operation with immediate values ​​provided in the embodiments of the present invention is only applicable to requests where the lower M bits are non-zero and the remaining higher bits are zero, thereby enabling the operation of the corresponding immediate values ​​by padding the higher bits with zeros.

[0189] In a further embodiment of the present invention, a time synchronization operation module is further provided, with reference to... Figure 17 The diagram illustrates an optional structure of a time synchronization module. This time synchronization module includes multiple state machines (state machine 1, state machine 2, ..., state machine n are shown as examples), special registers, an arithmetic unit, an instruction cache, memory access arbitration, arithmetic arbitration, and memory access strobe. The instruction cache is used to cache the instructions required in the time synchronization operation process.

[0190] In this embodiment of the invention, multiple state machines operate in parallel, and the process can be controlled based on an arbitration mechanism. Specifically, when the multiple state machines access instructions, memory access arbitration can be used to determine the state machines allowed to access the instruction cache at the same time, thereby controlling instruction access. Taking a time synchronization operation module with four state machines as an example, at the same time, a maximum of four state machines can access the instruction cache. Therefore, memory access arbitration is performed when the state machines access the instruction cache. Memory access arbitration is implemented using round-robin scheduling arbitration. Initially, the memory access priority of the state machines can be configured as: State Machine 1 > State Machine 2 > State Machine 3 > State Machine 4. When the memory access request of State Machine 1 is responded to, its priority drops to the lowest. At this time, the priority of the state machines is: State Machine 2 > State Machine 3 > State Machine 4 > State Machine 1. In a specific example, the instruction address width can be 12 bits, supporting a maximum of 4096 instructions, the instruction bit width is 16 bits, and the instruction cache size can be 8KB.

[0191] When the state machine allows access to the instruction cache, the instruction address in the instruction cache can be sent to the instruction cache to obtain the instruction corresponding to the instruction address.

[0192] Furthermore, the scheduling process of the multiple state machines for the computational units can also be controlled based on an arbitration mechanism. Specifically, when the multiple state machines schedule the computational units, arbitration can be used to determine which arithmetic units are allowed to be scheduled by the state machines at the same time, thereby controlling the scheduling of the computational units. Specifically, the computational unit may include multiple arithmetic units, such as an 80-bit adder, a 64-bit adder, a 64-bit multiplier, a 64-bit divider, and a shifter, etc. Each arithmetic unit has independent inputs and results. Arbitration can record whether each arithmetic unit in the computational unit is idle; if idle, it can be scheduled by the state machine. In this embodiment, arbitration allows different state machines to schedule different arithmetic units at the same time; for example, state machine 1 calls the 64-bit adder, and state machine 2 calls the 64-bit multiplier.

[0193] When the state machine allows scheduling of the arithmetic unit, the data to be processed indicated by the instruction can be sent to the arithmetic unit as input to obtain the corresponding processing result.

[0194] In a further embodiment of the present invention, the state machine is configured with a corresponding set of special registers. Taking an 8-bit address width for the special registers of a single state machine as an example, a state machine can address 256 special registers. The synchronous storage device can be mapped to the address space of the special registers through address mapping, thereby enabling data interaction between the special registers and the synchronous storage device.

[0195] In the case of multiple state machines, the state machines can access special registers based on memory access strobes.

[0196] In a further embodiment of the present invention, the state machine may also be configured with a corresponding set of general-purpose registers. Optionally, the general-purpose registers can be accessed via a 3-bit address, see reference. Figure 18 The diagram shows an optional structure of general-purpose registers. There can be eight general-purpose registers, labeled r0 to r7. In instructions with immediate values, such as ADDI, the destination register can be fixed at r7 as the storage address for the immediate result. In a further optional example, the general-purpose registers can store fixed parameters at fixed locations. Similar to the aforementioned parameters, these fixed parameters are not fixed data, but rather parameters that play a fixed role in the instruction processing flow. These fixed parameters can be, for example, calculated frequency ratios, frequency offsets, and time offsets. For instance, r0 can fixedly store the calculated frequency ratio, and r1 can fixedly store the calculated frequency offset, etc.

[0197] In a specific example, the time synchronization operation module can also execute instruction processing flow based on a wake-up mechanism. That is, when a calculation request is received, the operation flow is executed, and after the operation flow is completed, the module enters a sleep state, thereby further reducing the power consumption of the device.

[0198] In a further specific example, the time synchronization operation module of the present invention may also include a reserved field (rsvd field) to further expand multiple types of operation methods, thereby supporting a wider range of operation accelerator structures through the extended field.

[0199] It should be noted that the embodiments of the present invention only show some of the operation instructions and control instructions (such as storage instructions, loading instructions, etc.). In the embodiments of the present invention, instruction jump instructions, data transfer instructions, etc. can be further configured, but will not be elaborated here.

[0200] The time synchronization calculation method and time synchronization calculation module described in this embodiment of the invention can be applied to devices that need to perform time synchronization. The devices based on the time synchronization calculation method and time synchronization calculation module can also be further applied to USB4 transmission systems and perform time synchronization based on the USB4 protocol.

[0201] In this embodiment of the invention, a data transmission device is also provided. The data transmission device may be, for example, a UFP device. Specifically, the data transmission device may include a routing module for data transmission, and the time synchronization operation module described in this embodiment of the invention.

[0202] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0203] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A time synchronization operation method, characterized in that, include: Acquire the data to be processed and store the data to be processed in a preset storage device; wherein the address width of the preset storage device is smaller than the address width of the data to be processed; Based on the operation method of the data to be operated, an operation instruction corresponding to the data to be operated is determined; wherein, the operation instruction includes at least the effective storage address of the data to be operated, the effective storage address is a preset bit address of the storage address of the preset storage device, and the bit width of the operation instruction is smaller than the bit width of the data to be operated; According to the valid storage address indicated by the operation instruction, the data to be operated on is processed in the preset storage device.

2. The time synchronization operation method according to claim 1, characterized in that, The preset storage device includes a special register, in which N low-order bits are non-zero and the remaining high-order bits are zero. The effective storage address of the special register is the first N low-order bits of the special register, where N is less than the number of bits in the complete storage address of the special register.

3. The time synchronization operation method according to claim 2, characterized in that, The step of storing the data to be processed into a preset storage device includes: storing the data to be processed into a special register whose effective storage address is the first N least significant bits of the special register.

4. The time synchronization operation method according to claim 3, characterized in that, The step of performing corresponding operations on the data to be processed stored in the preset storage device according to the valid storage address indicated by the operation instruction includes: Based on the valid storage address indicated by the arithmetic instruction, determine the position of the valid storage address in the special register; Retrieve the data to be processed stored in the special register; The data to be processed is processed according to the processing method indicated by the processing instruction to obtain the corresponding processing result.

5. The time synchronization operation method according to claim 4, characterized in that, The operation instruction further includes a valid storage address for the operation result. The step of performing a corresponding operation on the data to be operated stored in the preset storage device according to the valid storage address indicated by the operation instruction further includes: The calculation result is stored in the special register at the location corresponding to the effective storage address of the calculation result.

6. The time synchronization operation method according to claim 2, characterized in that, The preset storage device includes a general-purpose register, the address width of which is smaller than the address width of the special register, and the effective storage address of the general-purpose register is the complete storage address of the general-purpose register; The step of storing the data to be processed into a preset storage device includes: The data to be processed is stored in a special register where the high-order address is non-zero. The first load instruction is invoked to load the data to be processed stored in the special register into the general-purpose register; The first load instruction contains the complete storage address of the data to be processed in the special register.

7. The time synchronization operation method according to claim 6, characterized in that, The step of performing corresponding operations on the data to be processed stored in the preset storage device according to the valid storage address indicated by the operation instruction includes: Based on the valid storage address indicated by the arithmetic instruction, determine the location of the valid storage address in the general-purpose register; Obtain the data to be processed stored in the general-purpose register; The data to be processed is processed according to the processing method indicated by the processing instruction to obtain the corresponding processing result.

8. The time synchronization operation method according to claim 7, characterized in that, The operation instruction further includes a valid storage address for the operation result. The step of performing a corresponding operation on the data to be operated stored in the preset storage device according to the valid storage address indicated by the operation instruction further includes: The calculation result is stored in the general-purpose register at the location corresponding to the effective storage address.

9. The time synchronization operation method according to claim 7, characterized in that, After the step of performing corresponding operations on the data to be operated on stored in the preset storage device according to the valid storage address indicated by the operation instruction, the method further includes: Invoke the first store instruction to store the operation result in the general-purpose register into the special register; The first storage instruction contains the complete storage address of the operation result in the special register.

10. The time synchronization operation method according to claim 5, characterized in that, When performing operations with immediate values, the operation instruction includes M low-order bits of the immediate value, where M is less than the bit width of the immediate value; The step of performing corresponding operations on the data to be processed stored in the preset storage device according to the valid storage address indicated by the operation instruction includes: The immediate value in the operation instruction is padded with zeros at the high bits to form an immediate value with the same bit width as the data to be operated on. According to the operation method indicated by the operation instruction, the data to be operated on and the immediate value to be operated on are operated on to obtain the operation result; Store the calculation result at the immediate result storage address; The immediate value result is stored at a preset fixed storage address.

11. The time synchronization operation method according to claim 10, characterized in that, When performing operations with immediate values, it also includes: The second store instruction is invoked to store the immediate value at the location of the special register corresponding to the effective storage address indicated by the second store instruction; The immediate value in the special register is padded with zeros at the high bits.

12. The time synchronization operation method according to claim 10, characterized in that, When performing operations with immediate values, it also includes: The second load instruction is invoked to store the immediate value at the location of the general-purpose register corresponding to the effective memory address indicated by the second load instruction; The immediate value in the general-purpose register is padded with zeros at the high bits.

13. A time synchronization computing module, characterized in that, include: A preset storage device is used to store data to be processed, wherein the address width of the preset storage device is smaller than the address width of the data to be processed; A state machine is used to determine the operation instruction corresponding to the data to be operated based on the operation method of the data to be operated; wherein the operation instruction includes at least the valid storage address of the data to be operated, the valid storage address is a preset bit address of the storage address of the preset storage device, and the bit width of the operation instruction is smaller than the bit width of the data to be operated; The arithmetic unit is used to perform corresponding operations on the data to be processed stored in the preset storage device according to the valid storage address of the arithmetic instruction.

14. The time synchronization operation module according to claim 13, characterized in that, The preset storage device includes a special register, in which N low-order bits are non-zero and the remaining high-order bits are zero. The effective storage address of the special register is the first N low-order bits of the special register, where N is less than the number of bits in the complete storage address of the special register.

15. The time synchronization operation module according to claim 14, characterized in that, The operation instruction also includes a valid storage address for the operation result, which is used to indicate the location in the special register corresponding to the valid storage address of the operation result.

16. The time synchronization operation module according to claim 14, characterized in that, The preset storage device includes a general-purpose register, the address width of which is smaller than the address width of the special register, and the effective storage address of the general-purpose register is the complete storage address of the general-purpose register.

17. The time synchronization operation module according to claim 16, characterized in that, The operation instruction also includes a valid storage address for the operation result, which is used to indicate the location in the general-purpose register corresponding to the valid storage address of the operation result.

18. The time synchronization operation module according to claim 16, characterized in that, The state machine is multiple, and the time synchronization operation module further includes: instruction cache, memory access arbitration, and operation arbitration; The instruction cache is used to cache the instructions required in the time synchronization operation process; The memory access arbitration is used to determine the state machine that allows access to the instruction cache at the same time. The computational arbitration is used to determine the arithmetic units that are allowed to be scheduled by the state machine at the same time; The general-purpose registers are configured in correspondence with the state machine, and the special-purpose registers are configured in correspondence with the state machine.

19. The time synchronization operation module according to claim 13, characterized in that, The time synchronization operation module executes the instruction processing flow based on the wake-up mechanism.

20. The time synchronization operation module according to claim 14, characterized in that, In the special registers, each address's special register is used to store the corresponding preset parameters.

21. The time synchronization operation module according to claim 16, characterized in that, In the preset storage device, the data operation methods corresponding to special registers and general-purpose registers are different.

22. A data transmission device, characterized in that, include: The routing module is used for data transmission; The time synchronization computing module according to any one of claims 13 to 21.

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