A frequency calibration method for long-term self-keeping of chip atomic clock

Abstract

The embodiment of the present application is to provide a frequency calibration method for the long-term self-keeping of a chip atomic clock, which belongs to the field of atomic frequency calibration. The method is applied to a frequency calibration system, which is communicatively connected to the chip atomic clock; it includes the following steps: obtaining the first frequency drift rate and the first duration of the chip atomic clock, wherein the first frequency drift rate is the aging rate of the chip atomic clock, and the first duration is the first punctual duration of the chip atomic clock; based on the first frequency drift rate and the first duration, obtaining the time difference sequence of the chip atomic clock; the time difference sequence is used to characterize the frequency deviation law of the chip atomic clock; based on the time difference sequence, sending the punctual frequency drift rate to the chip atomic clock to calibrate the chip atomic clock. The present application has the effect of improving the punctuality accuracy of the chip atomic clock in the long-term punctuality process.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of atomic frequency standards, and more specifically, to a frequency calibration method for a chip atomic clock in the long term. Background Art

[0002] As one of the seven fundamental physical quantities, time plays a vital role in geophysical measurements. The accuracy of time affects the accuracy of measurements. For example, in earthquake observation, earthquake phase analysis and source location depend on the accuracy of the arrival time of seismic waves. The accuracy of the arrival time depends on the accuracy of the internal time of the seismic wave measurement equipment, and the accuracy of the time is closely related to the accuracy of the clock source.

[0003] Existing clock sources such as crystal oscillators or atomic clocks all have inaccurate initial frequencies and uncertain time phases. In some applications, the internal frequency source continuously uses the standard second output by the GPS / Beidou receiver to calibrate the frequency source and output time. The accuracy of chip atomic clocks is affected by environmental factors such as temperature and aging. In short-term timekeeping applications, the impact of temperature on frequency is the primary factor. In long-term timekeeping applications, frequency changes caused by aging are the primary factor.

[0004] However, in some application environments, such as when using a chip atomic clock underwater, it is difficult to receive GPS / Beidou signals. Usually, the internal frequency source of the instrument is calibrated with a standard source before use. The time accuracy depends on the performance of the frequency source itself, which can easily cause deviations in the accuracy of the chip atomic clock. Summary of the Invention

[0005] The embodiment of the present application provides a frequency calibration method for improving the long-term self-timekeeping accuracy of a chip atomic clock, aiming to improve the accuracy of the chip atomic clock's timekeeping process.

[0006] In a first aspect, an embodiment of the present application provides a method for frequency calibration of a chip atomic clock for long-term self-keeping. The method is applied to a frequency calibration system, wherein the frequency calibration system is communicatively connected to the chip atomic clock; the method comprises the following steps:

[0007] Obtaining a first frequency drift rate and a first duration of the chip atomic clock, wherein the first frequency drift rate is an aging rate of the chip atomic clock, and the first duration is a first punctual duration of the chip atomic clock;

[0008] Based on the first frequency drift rate and the first time length, a time difference sequence of the chip atomic clock is obtained; the time difference sequence is used to characterize the frequency deviation law of the chip atomic clock;

[0009] Based on the time difference sequence, the timekeeping frequency drift rate is sent to the chip atomic clock to calibrate the chip atomic clock.

[0010] Optionally, acquiring the time difference sequence of the chip atomic clock based on the first frequency drift rate and the first time length includes:

[0011] Acquire a first frequency offset of the chip atomic clock based on the first frequency drift rate and the first duration;

[0012] Performing first timekeeping on the chip atomic clock, and calibrating the chip atomic clock to a first frequency offset;

[0013] and obtaining a first phase, where the first phase is a phase difference between the reference second and the output second when the first timekeeping ends;

[0014] Acquire a second frequency offset, a second phase, and a second duration of the chip atomic clock through the frequency calibration system; the second duration is the actual total duration of the first time the chip atomic clock is punctual;

[0015] A time difference sequence of the chip atomic clock is acquired based on the first frequency offset, the second frequency offset, the second duration, the first phase and the second phase.

[0016] Optionally, acquiring the time difference sequence of the chip atomic clock based on the first frequency offset, the second frequency offset, the second duration, the first phase, and the second phase includes:

[0017] Acquire a second frequency drift rate based on the second duration, the first frequency offset, and the second frequency offset;

[0018] Acquire a third frequency drift rate based on the first phase, the second phase, the second duration, and the first frequency offset;

[0019] Acquire a fourth frequency drift rate based on the second frequency drift rate and the third frequency drift rate;

[0020] A time difference sequence of the chip atomic clock is acquired based on the first frequency offset, the first phase, and the fourth frequency drift rate.

[0021] Optionally, obtaining the second frequency offset of the chip atomic clock by the frequency calibration system includes:

[0022] Measuring the frequency deviation between the output frequency of the chip atomic clock and a high-precision frequency source; the high-precision frequency source is a frequency source inside the frequency calibration system;

[0023] The average value of the frequency deviations is the second frequency offset.

[0024] Optionally, acquiring the second phase of the chip atomic clock by using the frequency calibration system includes:

[0025] Measuring the phase difference between the output second and the reference second of the chip atomic clock; the reference second is the reference time input to the frequency calibration system;

[0026] Get the phase difference between the output second and the reference second within the expected value of time;

[0027] The average of the phase differences is the second phase.

[0028] Optionally, acquiring a first frequency offset of the chip atomic clock based on the first frequency drift rate and the first duration includes:

[0029] The first frequency offset is calculated using the following formula:

[0030] ;

[0031] Where, is the first frequency offset; is the first frequency drift rate; For the first duration.

[0032] Optionally, acquiring a second frequency drift rate based on the second duration, the first frequency offset, and the second frequency offset includes:

[0033] The second frequency drift rate is calculated using the following formula:

[0034] ;

[0035] Where, is the second frequency drift rate; is the second frequency offset; is the first frequency offset; For the second duration.

[0036] Optionally, acquiring a third frequency drift rate based on the first phase, the second phase, the second duration, and the first frequency offset includes:

[0037] The third frequency drift rate is calculated by the following formula:

[0038] ;

[0039] Where, is the third frequency drift rate; is the second phase; The first phase.

[0040] Optionally, acquiring the time difference sequence of the chip atomic clock based on the first frequency offset, the first phase, and the fourth frequency drift rate includes:

[0041] The time difference series is calculated using the following formula:

[0042] ;

[0043] Where, is the time difference series; is the first phase; The estimated time for punctuality; is the fourth frequency drift rate.

[0044] Optionally, calibrating a chip atomic clock based on the time difference sequence includes:

[0045] Obtaining an estimated punctuality duration, substituting the estimated punctuality duration into a time difference sequence to obtain an estimated punctuality time difference;

[0046] Obtaining a timekeeping frequency drift corresponding to the expected timekeeping time difference;

[0047] The timekeeping frequency drift is reversely preset in the chip atomic clock to calibrate the chip atomic clock according to the timekeeping frequency drift.

[0048] Beneficial effects: This application connects the frequency calibration system and the chip atomic clock through communication, and can obtain the internal information of the chip atomic clock and adjust the chip atomic clock through the frequency calibration system; then, through the first frequency drift rate and the first duration of the chip atomic clock, calculate and obtain the time difference sequence that can feedback the frequency deviation law of the chip atomic clock, and through the time difference sequence, obtain the timekeeping frequency drift amount, and preset the timekeeping frequency drift amount to the chip atomic clock; then, in various application environments, the chip atomic clock can be calibrated, and the calibration process does not require additional software and hardware design in the chip atomic clock, which has the effect of improving the timekeeping accuracy of the chip atomic clock in the long-term timekeeping process. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 This is a flowchart of the steps of the comparison method proposed in one embodiment of the present application;

[0051] Figure 2 This is a flowchart of the sub-steps of step S201 in the comparison method proposed in one embodiment of the present application;

[0052] Figure 3 It is a structural diagram of a frequency calibration system proposed in another embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0054] Example 1

[0055] Reference Figure 1 , shows a step flow chart of a frequency calibration method for the long-term self-time accuracy of a chip atomic clock in an embodiment of the present invention, wherein the calibration method is applied to a frequency calibration system, and the frequency calibration system is communicatively connected to the chip atomic clock.

[0056] like Figure 1 As shown, this comparison method may specifically include the following steps:

[0057] S101, obtaining a first frequency drift rate and a first duration of the chip atomic clock, wherein the first frequency drift rate is an aging rate of the chip atomic clock, and the first duration is a first punctual duration of the chip atomic clock;

[0058] The first frequency drift rate of the chip atomic clock is the aging rate of the chip atomic clock. The aging rate of the chip atomic clock is set when the chip atomic clock leaves the factory and can be obtained through the factory data of the chip atomic clock. In this embodiment, the first frequency drift rate and the first duration are used as basic data to support subsequent calibration of the chip atomic clock.

[0059] S201: Acquire a time difference sequence of the chip atomic clock based on the first frequency drift rate and the first duration; the time difference sequence is used to characterize a frequency deviation regularity of the chip atomic clock;

[0060] In this embodiment, a time difference sequence is obtained, which is used to characterize the frequency deviation law of the chip atomic clock. When calibrating the chip atomic clock, the time difference sequence is used as a basis.

[0061] S301, sending a timekeeping frequency drift rate to the chip atomic clock based on the time difference sequence to calibrate the chip atomic clock;

[0062] The time difference sequence is used as the frequency deviation sequence of the standard chip atomic clock. The frequency drift of the chip atomic clock within a predetermined time can be obtained through the time difference sequence, and the chip atomic clock can be calibrated by the frequency drift.

[0063] This embodiment connects the frequency calibration system and the chip atomic clock through communication, and can obtain the information inside the chip atomic clock and adjust the chip atomic clock through the frequency calibration system; then, through the first frequency drift rate and the first duration of the chip atomic clock, a time difference sequence that can feedback the frequency deviation law of the chip atomic clock is calculated and obtained, and the time difference sequence is used to obtain the timekeeping frequency drift amount, and the timekeeping frequency drift amount is preset to the chip atomic clock; the chip atomic clock can be calibrated in various application environments, and the calibration process does not require additional software and hardware design in the chip atomic clock, which has the effect of improving the timekeeping accuracy of the chip atomic clock in the long-term timekeeping process.

[0064] Example 2

[0065] like Figure 1 As shown, Figure 1 A flowchart of a method for frequency calibration of a chip atomic clock for long-term self-keeping is shown in an embodiment of the present application. The calibration method may specifically include the following steps:

[0066] S101, obtaining a first frequency drift rate and a first duration of the chip atomic clock, wherein the first frequency drift rate is an aging rate of the chip atomic clock, and the first duration is a first punctual duration of the chip atomic clock;

[0067] The first duration is the expected first punctuality duration, and the actual first punctuality duration may be inconsistent with this value; this value is input into the frequency calibration system.

[0068] In this embodiment, the first duration and the first frequency drift rate are used as basic data to perform subsequent method steps.

[0069] S201: Acquire a time difference sequence of the chip atomic clock based on the first frequency drift rate and the first duration; the time difference sequence is used to characterize a frequency deviation regularity of the chip atomic clock;

[0070] By obtaining the time difference sequence of the chip atomic clock, when performing frequency calibration on the chip atomic clock, there is no need to add additional software and hardware design to the chip atomic clock. The frequency deviation that needs to be corrected can be directly obtained through the time difference sequence to calibrate the chip atomic clock.

[0071] The step of acquiring the time difference sequence of the chip atomic clock based on the first frequency drift rate and the first time length includes the following sub-steps:

[0072] Sub-step S2011, acquiring a first frequency offset of the chip atomic clock based on the first frequency drift rate and the first duration;

[0073] In this embodiment, the estimated value of the first frequency offset can be expressed as:

[0074] ;

[0075] in, Indicates the time difference at the end of timekeeping, that is, the phase difference between the chip atomic clock and the frequency calibration system; Indicates the initial time difference between the chip atomic clock output second signal and the reference second signal; It represents the average frequency deviation of the chip atomic clock output frequency within a period of time after entering the punctual state; a represents the chip atomic clock frequency drift rate; and t represents the punctual duration.

[0076] In order to obtain the minimum output seconds deviation at the end of the first punctual period,

[0077] Let ; Then, substituting the first frequency offset and the first frequency drift rate, the calculation formula of the first frequency offset can be obtained as follows:

[0078] ;

[0079] When the synchronization accuracy is high, =0, then:

[0080] ;

[0081] Where, is the first frequency offset; is the first frequency drift rate; For the first duration;

[0082] Then, by substituting the first frequency drift rate and the first duration into the above formula, the first frequency offset can be calculated; the first frequency drift is the average frequency offset of the chip atomic clock during the timekeeping duration of the first duration.

[0083] Sub-step S2012: performing first timekeeping on the chip atomic clock, and calibrating the chip atomic clock to a first frequency offset.

[0084] After the chip atomic clock has been kept time, the frequency calibration system can send serial port commands through the serial port line to adjust the output frequency and output second phase of the chip atomic clock, and calibrate the chip atomic clock to the first frequency offset.

[0085] After the chip atomic clock calibration is completed, a first phase is obtained, where the first phase is the phase difference between the reference second and the output second at the end of the first timekeeping;

[0086] The first phase can be directly measured on the chip atomic clock using the time difference measurement module in the frequency calibration system. It is important to note that in this step, the chip atomic clock output second phase must be adjusted or synchronized via serial port commands. Typically, after synchronization or phase adjustment, the initial first phase can be ignored.

[0087] Sub-step S2013, obtaining a second frequency offset, a second phase, and a second duration of the chip atomic clock through the frequency calibration system; the second duration is the actual total duration of the first time the chip atomic clock is punctual;

[0088] Wherein, obtaining the second frequency offset of the chip atomic clock through the frequency calibration system includes:

[0089] The frequency deviation between the output frequency of the chip atomic clock and a high-precision frequency source is measured; the high-precision frequency source is a frequency source inside the frequency calibration system; the average value of the frequency deviation is the second frequency offset.

[0090] The second frequency offset is the average value of the frequency deviation of the chip atomic clock output frequency compared with the high-precision clock source in the frequency calibration system over a period of time when the timekeeping ends.

[0091] The method of obtaining the second phase of the chip atomic clock through the frequency calibration system includes: measuring the phase difference between the output second and the reference second of the chip atomic clock; the reference second is the reference time input to the frequency calibration system; obtaining the phase difference between the output second and the reference second within the expected time value; the average of the phase differences is the second phase.

[0092] Through the interaction between the frequency calibration system and the chip atomic clock, the second frequency offset, the second phase and the second duration can be obtained. In the following steps, the second frequency offset, the second phase and the second duration are used as basic data.

[0093] Sub-step S2014: acquiring a time difference sequence of the chip atomic clock based on the first frequency offset, the second frequency offset, the second duration, the first phase, and the second phase.

[0094] In this sub-step, the first frequency offset, the second frequency offset, the second duration, the first phase and the second phase are used as basic data to obtain the time difference sequence of the chip atomic clock. The time difference sequence of the chip atomic clock can characterize the change in the frequency drift rate of the chip atomic clock during a timekeeping process.

[0095] include:

[0096] First, obtaining a second frequency drift rate based on the second duration, the first frequency offset, and the second frequency offset;

[0097] When obtaining the second frequency drift rate, the second frequency drift rate is calculated using the following formula:

[0098] ;

[0099] Where, is the second frequency drift rate; is the second frequency offset; is the first frequency offset; is the second duration; in the calculation process, the frequency is continuously changed in the first timing process, and the frequency drift rate remains unchanged.

[0100] Secondly, obtaining a third frequency drift rate based on the first phase, the second phase and the second duration;

[0101] When obtaining the third frequency drift rate, the third frequency drift rate is calculated using the following formula:

[0102] ;

[0103] Where, is the third frequency drift rate; is the second phase; is the first phase; is the second duration; in the calculation process, the frequency is continuously changed in the first timing process, and the frequency drift rate remains unchanged.

[0104] Thirdly, obtaining a fourth frequency drift rate based on the second frequency drift rate and the third frequency drift rate;

[0105] Ideally, the frequency drift rate is fixed. However, in reality, the frequency drift rate changes slowly. Therefore, the second and third frequency drift rates obtained according to the above steps cannot accurately estimate the frequency drift rate. In this embodiment, the two are combined to improve the reliability of the frequency drift rate estimation. This is achieved through the following formula:

[0106] ;

[0107] Wherein, a4 is the fourth frequency drift rate; g() represents the comprehensive calculation method.

[0108] In this embodiment, the comprehensive method adopts a weighting method, and the specific weights are determined according to the results of multiple actual measurements.

[0109] The weight method can generally be expressed as ; where m+n=1. The values ​​of m and n should be adjusted based on the actual measured frequency drift rate and the estimated and To confirm, and finally consistent.

[0110] Finally, based on the first frequency offset, the first phase and the fourth frequency drift rate, a time difference sequence of the chip atomic clock is obtained.

[0111] When obtaining the time difference sequence of the chip atomic clock, the following formula is used to calculate the time difference sequence:

[0112] ;

[0113] Where, is the time difference series; is the first phase; The estimated time for punctuality; is the fourth frequency drift rate.

[0114] S301 : Based on the time difference sequence, send the timing frequency drift rate to the chip atomic clock to calibrate the chip atomic clock.

[0115] Obtaining an estimated punctuality duration, substituting the estimated punctuality duration into a time difference sequence to obtain an estimated punctuality time difference;

[0116] In this embodiment, when obtaining the expected punctuality time difference, the provided expected punctuality duration should be smaller than the second duration.

[0117] Obtaining a timekeeping frequency drift corresponding to the expected timekeeping time difference;

[0118] The timekeeping frequency drift is reversely preset in the chip atomic clock to calibrate the chip atomic clock according to the timekeeping frequency drift.

[0119] By reversely presetting the timekeeping frequency drift in the chip atomic clock, the chip atomic clock first calibrates the frequency of the chip atomic clock itself based on the timekeeping frequency drift during the timekeeping process. The output second signal of the chip atomic clock is the calibrated output second signal, thereby achieving the effect of calibrating the chip atomic clock.

[0120] Furthermore, since the frequency drift rate changes gradually with time, using the newly estimated drift rate correction is helpful to obtain higher data correction accuracy.

[0121] In this embodiment, the frequency calibration system and the chip atomic clock are connected by communication, so that the frequency calibration system can be used to obtain information inside the chip atomic clock and adjust the chip atomic clock; then, the first frequency drift rate and the first duration of the chip atomic clock are used to calculate and obtain a time difference sequence that can feedback the frequency deviation law of the chip atomic clock, and the time difference sequence is used to obtain the timekeeping frequency drift amount, and the timekeeping frequency drift amount is preset to the chip atomic clock; then, in various application environments, the chip atomic clock can be calibrated, and the calibration process does not require additional software and hardware design in the chip atomic clock, which has the effect of improving the timekeeping accuracy of the chip atomic clock in the long-term timekeeping process.

[0122] Example 3

[0123] like Figure 3 As shown, Figure 3 The structure of the frequency calibration system is shown; the frequency calibration system is connected to the chip atomic clock for communication; the frequency calibration system includes a high-precision frequency source, a frequency measurement module, a time difference measurement module and a processing and calculation module; wherein:

[0124] The high-precision frequency source is used to provide an accurate frequency source for the frequency calibration system;

[0125] The frequency measurement module is used to measure the frequency deviation between the output frequency of the chip atomic clock and the high-precision frequency source;

[0126] The time difference measurement module is used to measure the phase difference between the chip atomic clock output second and the reference second;

[0127] The processing and calculation module is used to calculate the frequency drift rate and send corresponding calibration instructions to the chip atomic clock.

[0128] During calibration, the reference second must first be input. This can be the second signal output by a BeiDou / GPS receiver or another second signal that maintains phase stability throughout the entire frequency calibration process. Inputting the reference second into the frequency calibration system calibrates the high-precision clock source within the system, enabling it to provide a more accurate reference frequency.

[0129] The frequency calibration system and the chip atomic clock are connected via a serial line communication, and the frequency calibration system can adjust the output frequency and output second phase of the chip atomic clock by sending serial port commands.

[0130] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0131] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0133] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0135] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0136] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0137] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for frequency calibration of a chip atomic clock for long-term self-keeping, characterized in that: The method is applied to a frequency calibration system, wherein the frequency calibration system is communicatively connected to a chip atomic clock and comprises the following steps: Obtaining a first frequency drift rate and a first duration of the chip atomic clock, wherein the first frequency drift rate is an aging rate of the chip atomic clock, and the first duration is a first punctual duration of the chip atomic clock; Based on the first frequency drift rate and the first time length, a time difference sequence of the chip atomic clock is obtained; the time difference sequence is used to characterize the frequency deviation law of the chip atomic clock; Based on the time difference sequence, sending the timekeeping frequency drift rate to the chip atomic clock to calibrate the chip atomic clock; Wherein, calibrating the chip atomic clock based on the time difference sequence includes: Obtaining an estimated punctuality duration, substituting the estimated punctuality duration into a time difference sequence to obtain an estimated punctuality time difference; Obtaining a timekeeping frequency drift corresponding to the expected timekeeping time difference; The timekeeping frequency drift is reversely preset in the chip atomic clock to calibrate the chip atomic clock according to the timekeeping frequency drift.

2. A calibration method according to claim 1, characterized in that: The acquiring the time difference sequence of the chip atomic clock based on the first frequency drift rate and the first time length includes: Acquire a first frequency offset of the chip atomic clock based on the first frequency drift rate and the first duration; Performing first timekeeping on the chip atomic clock, and calibrating the chip atomic clock to a first frequency offset; and obtaining a first phase, where the first phase is a phase difference between the reference second and the output second when the first timekeeping ends; Acquire a second frequency offset, a second phase, and a second duration of the chip atomic clock through the frequency calibration system; the second duration is the actual total duration of the first time the chip atomic clock is punctual; A time difference sequence of the chip atomic clock is acquired based on the first frequency offset, the second frequency offset, the second duration, the first phase and the second phase.

3. A calibration method according to claim 2, characterized in that: The acquiring the time difference sequence of the chip atomic clock based on the first frequency offset, the second frequency offset, the second duration, the first phase and the second phase includes: Acquire a second frequency drift rate based on the second duration, the first frequency offset, and the second frequency offset; Acquire a third frequency drift rate based on the first phase, the second phase, the second duration, and the first frequency offset; Acquire a fourth frequency drift rate based on the second frequency drift rate and the third frequency drift rate; A time difference sequence of the chip atomic clock is acquired based on the first frequency offset, the first phase, and the fourth frequency drift rate.

4. A calibration method according to claim 2, characterized in that: Acquiring a second frequency offset of the chip atomic clock by the frequency calibration system includes: Measuring the frequency deviation between the output frequency of the chip atomic clock and a high-precision frequency source; the high-precision frequency source is a frequency source inside the frequency calibration system; The average value of the frequency deviations is the second frequency offset.

5. A calibration method according to claim 2, characterized in that: The obtaining the second phase of the chip atomic clock by the frequency calibration system includes: Measuring the phase difference between the output second and the reference second of the chip atomic clock; the reference second is the reference time input to the frequency calibration system; Get the phase difference between the output second and the reference second within the expected value of time; The average of the phase differences is the second phase.

6. A calibration method according to claim 3, characterized in that: The acquiring, based on the first frequency drift rate and the first duration, a first frequency offset of the chip atomic clock includes: The first frequency offset is calculated using the following formula: ； Where, is the first frequency offset; is the first frequency drift rate; For the first duration.

7. A calibration method according to claim 6, characterized in that: The acquiring a second frequency drift rate based on the second duration, the first frequency offset, and the second frequency offset includes: The second frequency drift rate is calculated using the following formula: ； Where, is the second frequency drift rate; is the second frequency offset; is the first frequency offset; For the second duration.

8. A calibration method according to claim 7, characterized in that: The acquiring a third frequency drift rate based on the first phase, the second phase, the second duration, and the first frequency offset includes: The third frequency drift rate is calculated by the following formula: ； Where, is the third frequency drift rate; is the second phase; The first phase.

9. A calibration method according to claim 8, characterized in that: The acquiring the time difference sequence of the chip atomic clock based on the first frequency offset, the first phase, and the fourth frequency drift rate includes: The time difference series is calculated using the following formula: ； Where, is the time difference series; is the first phase; The estimated time for punctuality; is the fourth frequency drift rate.

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