Reconfigurable Model of an InP Terahertz Transistor and Its Parameter Extraction Method

Abstract

The present invention belongs to the field of semiconductor devices, and specifically provides a reconfigurable model of an InP terahertz transistor and a method for extracting its parameters, so as to solve the problems of the small applicable range of the existing model and the inability to model transistors with different structures. On the basis of the existing model, the present invention introduces variable elements, and through the variable elements, various types of transistors are classified into a unified model, making the physical meaning between various transistors clearer; at the same time, in the process of parameter extraction, the transistor is equivalent to a sub-model of 6 parasitic elements, and step-by-step modeling and simulation are carried out through a three-dimensional electromagnetic field simulation software, and then based on a new parameter extraction algorithm, the parameters of various transistors are extracted under the unified model and its equation expressions; based on this, the present invention can accurately model double-hole bridged transistors, single-hole bridged transistors, and double-hole non-bridged transistors, greatly improving the applicable range of the model, and having the advantages of saving modeling time and improving simulation accuracy.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices, relates to microelectronic device technologies, and further relates to a small-signal equivalent circuit model of HEMT transistors. Specifically, a reconfigurable model of InP terahertz transistors and a method for extracting its parameters are provided. Background Art

[0002] InP materials have characteristics such as high electron mobility and high saturation drift velocity. Compared with GaN-based HEMT transistors, InP material devices have better noise coefficients. Compared with GaAs-based HEMT transistors, InP materials have higher electron mobility and can be applied to higher frequency bands. Therefore, InP-based HEMT transistors are suitable for the design of low-noise amplifiers at terahertz frequencies and are of great significance for electronic warfare, phased array radars, satellite communications, radio astronomy, etc. at terahertz frequencies.

[0003] The small-signal equivalent circuit model (abbreviation: small-signal model) is the link between circuit design and device characteristics. After modeling the device, the model can be embedded in EDA software for circuit simulation and design. For HEMT transistor devices, the parasitic parameters of traditional small-signal models have no physical meaning, the simulation accuracy is not high, and different transistor structures cannot be modeled. To solve this problem, the inventor of the present invention disclosed a small-signal model of InP-based terahertz HEMT transistors in a patent document with the publication number of CN114970419A. The parasitic parameter extraction process of this model has clear physical meaning and greatly improved accuracy. However, during the chip design process, the passive structure of transistors is often changed, such as the common double-hole bridged transistors (double-hole structure transistors including air bridges), single-hole bridged transistors (single-hole structure transistors including air bridges), and double-hole non-bridged transistors (double-hole structure transistors without air bridges). In this patent document, three sets of models need to be established to describe these three types of transistors respectively. Summary of the Invention

[0004] The object of the present invention is to provide a reconfigurable InP-based terahertz HEMT transistor small-signal model and its parameter extraction method for the problems that the applicable range of the existing small-signal model is small and it is impossible to model transistors with different structures. On the basis of the existing model, the present invention introduces variable elements, and through the variable elements, various types of transistors after the passive structure is changed are classified into a unified model, making the physical meaning between transistors with different structures clearer; at the same time, in the parameter extraction process, the transistor geometry is divided into 6 groups, which are respectively equivalent to 6 parasitic element sub-models, and the 6 groups of geometries are step-by-step modeled and simulated through a three-dimensional electromagnetic field simulation software, and then based on the new parameter extraction algorithm, the parameters of transistors with different structures are extracted (including parasitic parameters and intrinsic parameters) under the unified model and its equation expression; based on this, the present invention can accurately model double-hole transistors with bridges (double-hole structure transistors including air bridges), single-hole transistors with bridges (single-hole structure transistors including air bridges), and double-hole transistors without bridges (double-hole structure transistors without air bridges), greatly improving the applicable range of the model, and having the advantages of saving modeling time and improving the simulation accuracy of the small-signal model.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] A reconfigurable model of an InP terahertz transistor, comprising: parasitic elements and intrinsic elements; characterized in that

[0007] The parasitic elements include: external gate parasitic impedance Z g 、external gate parasitic capacitance C g 、mid-gate parasitic capacitance C gs_in 、internal gate parasitic capacitance C gs_finger 、internal gate parasitic impedance Z grf 、internal gate parasitic inductance L g_finger 、gate-drain parasitic capacitance C gd_finger 、internal drain parasitic impedance Z drf 、internal drain parasitic inductance L d_finger 、internal drain parasitic capacitance C ds_finger 、mid-drain parasitic capacitance C ds_in 、external drain parasitic impedance Z d 、external drain parasitic capacitance C d 、source impedance Z srf 、source parasitic inductance L s 、variable mid-gate parasitic capacitance ΔC gs_in 、variable mid-drain parasitic capacitance ΔC ds_in 、variable internal gate parasitic capacitance ΔC gs_finger 、variable internal drain parasitic capacitance ΔC ds_finger 、variable source parasitic inductance ΔLs Variable source impedance ΔZ srf ; wherein

[0008] The parasitic impedance Z outside the gate g is connected in series with the parasitic capacitance C outside the gate g between the external gate node G and the external source node S. The parasitic impedance Z outside the drain d is connected in series with the parasitic capacitance C outside the drain d between the external drain node D and the external source node S. The source parasitic inductance L s is connected in series with the source impedance Z srf between the external source node S and the intrinsic source node S1. The parasitic capacitance C in the middle of the gate gs_in is connected in parallel with the variable parasitic capacitance ΔC in the middle of the gate gs_in between the external gate node G and the intrinsic source node S1. The parasitic capacitance C in the middle of the drain ds_in is connected in parallel with the variable parasitic capacitance ΔC in the middle of the drain ds_in between the external drain node D and the intrinsic source node S1. The parasitic impedance Z inside the gate grf is connected in series with the parasitic inductance L inside the gate g_finger between the external gate node G and the intrinsic gate node G1. The parasitic impedance Z inside the drain drf is connected in series with the parasitic inductance L inside the drain d_finger between the external drain node D and the intrinsic drain node D1. The parasitic capacitance C inside the gate gs_finger is connected in parallel with the variable parasitic capacitance ΔC inside the gate gs_finger between the intrinsic gate node G1 and the intrinsic source node S1. The parasitic capacitance C between the gate and the drain ds_finger is connected in parallel with the variable parasitic capacitance ΔC between the gate and the drain ds_finger between the intrinsic drain node D1 and the intrinsic source node S1. The gate-drain parasitic capacitance C gd_finger is connected between the intrinsic gate node G1 and the intrinsic drain node D1. The variable source parasitic inductance ΔL s is connected in series with the variable source impedance ΔZ srf between the external source node S and the intrinsic source node S1.

[0009] Furthermore, the intrinsic components include: the intrinsic capacitance C between the gate and the source gs , the intrinsic resistance R between the gate and the source i , the intrinsic capacitance C between the gate and the drain gd , the intrinsic resistance R between the gate and the drain gd , the intrinsic capacitance C between the drain and the source ds , the intrinsic resistance R between the drain and the source dsand a voltage-controlled current source VCCS, where the gate-source intrinsic capacitance C gs is connected in series with the gate-source intrinsic resistance R i between the intrinsic gate node G1 and the intrinsic source node S1. The gate-drain intrinsic capacitance C gd is connected in series with the gate-drain intrinsic resistance R gd between the intrinsic gate node G1 and the intrinsic drain node D1. The drain-source intrinsic capacitance C ds , the drain-source intrinsic resistance R ds are connected in parallel with the voltage-controlled current source VCCS between the intrinsic drain node D1 and the intrinsic source node S1.

[0010] The method for extracting the parameters of the reconfigurable model of the above InP terahertz transistor includes: parasitic parameter extraction and intrinsic parameter extraction; characterized in that the parasitic parameter extraction includes the following steps:

[0011] Step 1: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part and the drain transmission line part located on the upper surface of the dielectric layer; then perform two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculate the Y parameters and Z parameters, and then calculate the external gate parasitic impedance Z g , the external gate parasitic capacitance C g , the external drain parasitic impedance Z d , the external drain parasitic capacitance C d ;

[0012] Step 2: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, a single source part and source ground vias located on the upper surface of the dielectric layer; then perform single-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculate the Z parameters, and then calculate the source impedance Z srf , the source parasitic inductance L s , the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf ;

[0013] Step 3: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the gate finger part and its extended part located on the upper surface of the dielectric layer; then perform two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculate the Y parameters, and then calculate the internal gate parasitic inductance L g_finger, the parasitic impedance Z inside the gate grf ;

[0014] Step 4: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the drain transmission line part, the drain metal strip part and its extended part located on the upper surface of the dielectric layer; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters, and further calculate the parasitic inductance L inside the drain according to the Y parameters d_finger , the parasitic impedance Z inside the drain drf ;

[0015] Step 5: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the drain transmission line part, and two source parts located on the upper surface of the dielectric layer; for the double-hole transistor with a bridge, it also includes an air bridge connecting the two sources and two ground holes; for the double-hole transistor without a bridge, it also includes two ground holes; for the single-hole transistor with a bridge, it also includes an air bridge connecting the two sources and a single ground hole; then perform two-port three-dimensional electromagnetic simulation on the three types of transistors respectively within the full frequency band, calculate the Y parameters, and further calculate the parasitic capacitance C in the middle of the gate of the three types of transistors according to the Y parameters gs_in , the parasitic capacitance C in the middle of the drain ds_in , the variable parasitic capacitance ΔC in the middle of the gate gs_in , the variable parasitic capacitance ΔC in the middle of the drain ds_in ;

[0016] Step 6: In a three-dimensional electromagnetic simulation software, model the complete structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the gate finger part, the drain transmission line, the drain metal strip part, and two source parts; for the double-hole transistor with a bridge, it also includes an air bridge connecting the two sources and two ground holes; for the double-hole transistor without a bridge, it also includes two ground holes; for the single-hole transistor with a bridge, it also includes an air bridge connecting the two sources and a single ground hole; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters, and further calculate the gate-drain parasitic capacitance C gd_finger , the parasitic capacitance C inside the drain ds_finger , the parasitic capacitance C inside the gate gs_finger , the variable parasitic capacitance ΔC inside the gate gs_finger , the variable parasitic capacitance ΔC inside the drain ds_finger ;

[0017] Step 7: The external parasitic impedance Z of the gateg External parasitic capacitance C of the gate g Middle parasitic capacitance C of the gate gs_in Internal parasitic capacitance C of the gate gs_finger Internal parasitic impedance Z of the gate grf Internal parasitic inductance L of the gate g_finger Gate-drain parasitic capacitance C gd_finger Internal parasitic impedance Z of the drain drf Internal parasitic inductance L of the drain d_finger Internal parasitic capacitance C of the drain ds_finger Middle parasitic capacitance C of the drain ds_in External parasitic impedance Z of the drain d External parasitic capacitance C of the drain d Source impedance Z srf Source parasitic inductance L s Variable middle parasitic capacitance ΔC of the gate gs_in Variable middle parasitic capacitance ΔC of the drain ds_in Variable internal parasitic capacitance ΔC of the gate gs_finger Variable internal parasitic capacitance ΔC of the drain ds_finger Variable source parasitic inductance ΔL s Variable source impedance ΔZ srf Set to the parasitic parameters extracted in Steps 1 to 6, and optimize all parasitic parameters according to the parasitic cost function to obtain the final parasitic parameters.

[0018] Further, in Step 1, the external parasitic impedance Z of the gate g and the external parasitic capacitance C of the gate g and the external parasitic impedance Z of the drain d and the external parasitic capacitance C of the drain d satisfy the following equations:

[0019]

[0020]

[0021]

[0022]

[0023] where Z1(1,1) and Z1(2,2) represent the corresponding terms of the Z parameter in Step 1, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

[0024] Further, in Step 2, the source impedance Z srf and the source parasitic inductance L s satisfy the following equations:

[0025]

[0026]

[0027] For a two - hole bridged transistor, the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf satisfy the following equation:

[0028]

[0029]

[0030] For a two - hole non - bridged transistor, the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf satisfy the following equation:

[0031]

[0032]

[0033] For a single - hole bridged transistor, the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf satisfy: ΔL s = +∞, ΔZ srf = +∞;

[0034] where, Z2(1,1) represents the corresponding term of the Z - parameter in step 2, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

[0035] Furthermore, in step 3, the internal gate parasitic inductance L g_finger , the internal gate parasitic impedance Z grf satisfy the following equation:

[0036]

[0037]

[0038] where, Y3(2,1) represents the corresponding term of the Y - parameter in step 3, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

[0039] Furthermore, in step 4, the internal drain parasitic inductance L d_finger , the internal drain parasitic impedance Z drf satisfy the following equation:

[0040]

[0041]

[0042] Among them, Y4(2,1) represents the corresponding item in the Y parameter in Step 4, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

[0043] Furthermore, in Step 5, the parasitic capacitance C in the middle of the gate gs_in , the parasitic capacitance C in the middle of the drain ds_in satisfy the following equation:

[0044]

[0045]

[0046]

[0047]

[0048] Among them, Y 5a (1,1), Y 5a (1,2), Y 5a (2,1), Y 5a (2,2) successively represent the corresponding items of the Y parameter for the double-hole bridged transistor in Step 5, Y1(1,1) and Y1(2,2) respectively represent the corresponding items of the Y parameter in Step 1, Z2(1,1) represents the corresponding item of the Z parameter in Step 2, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively;

[0049] For the double-hole bridged transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in , the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy: ΔC gs_in = 0, ΔC ds_in = 0;

[0050] For the double-hole non-bridged transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in , the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy the following equation:

[0051]

[0052]

[0053]

[0054]

[0055] Among them, Y 5b (1,1), Y 5b (1,2), Y 5b (2,1), Y 5b (2,2) successively represent the corresponding items of the Y parameters for the double-hole non-bridge transistor in step 5;

[0056] For the single-hole bridge transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in and the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy the following equation:

[0057]

[0058]

[0059]

[0060]

[0061] Among them, Y 5c (1,1), Y 5c (1,2), Y 5c (2,1), Y 5c (2,2) successively represent the corresponding items of the Y parameters for the single-hole bridge transistor in step 5.

[0062] Furthermore, in step 6, the gate-drain parasitic capacitance C gd_finger and the internal parasitic capacitance C of the drain ds_finger and the internal parasitic capacitance C of the gate gs_finger satisfy the following equation:

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071]

[0072] Among them, Y 6a (1,1), Y 6a (1,2), Y 6a (2,1), Y 6a (2,2) successively represent the corresponding items of the Y-parameters for the double-hole bridged transistor in step 6, Y1(1,1) and Y1(2,2) respectively represent the corresponding items of the Y-parameters in step 1, Z2(1,1) represents the corresponding item of the Z-parameter in step 2, Y 52a (1,1), Y 52a (2,2) respectively represent the corresponding items of the Y-parameters in step 5, Y3(2,1) represents the corresponding item of the Y-parameters in step 3, Y4(2,1) represents the corresponding item of the Y-parameters in step 4, f represents frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit;

[0073] For the double-hole bridged transistor, the variable gate internal parasitic capacitance ΔC gs_finger , the variable drain internal parasitic capacitance ΔC ds_finger satisfy: ΔC gs_finger = 0, ΔC ds_finger = 0;

[0074] For the double-hole non-bridged transistor, the variable gate internal parasitic capacitance ΔC gs_finger , the variable drain internal parasitic capacitance ΔC ds_finger satisfy the following equation:

[0075]

[0076]

[0077]

[0078]

[0079]

[0080]

[0081]

[0082] Among them, Y 6b (1,1), Y 6b (1,2), Y 6b (2,1), Y 6b (2,2) successively represent the corresponding items of the Y-parameters for the double-hole non-bridged transistor in step 6; Y 52b (1,1), Y 52b(2, 2) respectively represent the corresponding items of the Y parameter in Step 5;

[0083] For a single-hole bridge transistor, the variable gate internal parasitic capacitance ΔC gs_finger , the variable drain internal parasitic capacitance ΔC ds_finger satisfy the following equation:

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091] where Y 6c (1, 1), Y 6c (1, 2), Y 6c (2, 1), Y 6c (2, 2) successively represent the corresponding items of the Y parameter for the single-hole bridge transistor in Step 6, and Y 52c (1, 1), Y 52c (2, 2) respectively represent the corresponding items of the Y parameter in Step 5.

[0092] Furthermore, the extraction of the intrinsic parameters includes the following steps:

[0093] Step 8: Measure the S parameters of the transistor under full bias in the full frequency band, and calculate the corresponding Y parameters and Z parameters from the S parameters;

[0094] Step 9: Based on the parasitic parameters obtained in Step 7, de-embed the full-frequency band test Y parameters of the transistor to obtain the intrinsic Y parameter Y int ; and then calculate the intrinsic parameters according to the intrinsic Y parameter Y int : gate-source intrinsic capacitance C gs , gate-source intrinsic resistance R i , gate-drain intrinsic capacitance C gd , gate-drain intrinsic resistance R gd , drain-source intrinsic capacitance C ds , drain-source intrinsic resistance R ds , voltage-controlled current source VCCS;

[0095] Step 10: Intrinsic parameter optimization of double-hole bridged transistors, double-hole non-bridged transistors, and single-hole bridged transistors;

[0096] Perform intrinsic parameter optimization on double-hole bridged transistors, double-hole non-bridged transistors, and single-hole bridged transistors respectively according to the intrinsic cost function;

[0097] Based on the optimized intrinsic parameters, perform decision fusion on the intrinsic parameters of double-hole bridged transistors, double-hole non-bridged transistors, and single-hole bridged transistors:

[0098] Calculate the average value of each intrinsic parameter respectively, and calculate the error function:

[0099]

[0100] Among them, M a 、M b 、M c are the intrinsic parameter values of double-hole bridged transistors, double-hole non-bridged transistors, and single-hole bridged transistors respectively, is the average value corresponding to the intrinsic parameter;

[0101] If the error is greater than or equal to 10%, the intrinsic parameter remains unchanged. If the error is less than 10%, the intrinsic parameter is updated to the corresponding average value.

[0102] Compared with the prior art, the beneficial results of the present invention are as follows:

[0103] The present invention provides a reconfigurable InP-based terahertz HEMT transistor small-signal model and its parameter extraction method for different structures. Specifically: The present invention improves the existing small-signal model, solves the problem that the existing small-signal model cannot model different transistor structures, and can accurately model three types of double-hole bridged transistors (double-hole structure transistors with air bridges), single-hole bridged transistors (single-hole structure transistors with air bridges), and double-hole non-bridged transistors (double-hole structure transistors without air bridges) under a unified model, and can determine the initial values of each parasitic parameter in the model. Compared with the existing small-signal model, the present invention greatly improves the applicable range of the model, can save modeling time, and improve the simulation accuracy of the small-signal model. Brief Description of the Drawings

[0104] Figure 1 is a schematic diagram of the topological structure of the InP-based terahertz HEMT transistor small-signal model in the present invention.

[0105] Figure 2 is Figure 1 a schematic diagram of the structure of the first parasitic element sub-model in the small-signal model shown.

[0106] Figure 3 is Figure 1 a schematic diagram of the structure of the second parasitic element sub-model in the small-signal model shown

[0107] Figure 4 is Figure 1 a schematic diagram of the structure of the third parasitic element sub-model in the small-signal model shown

[0108] Figure 5 is Figure 1 a schematic diagram of the structure of the fourth parasitic element sub-model in the small-signal model shown

[0109] Figure 6 is Figure 1 a schematic diagram of the structure of the fifth parasitic element sub-model in the small-signal model shown

[0110] Figure 7 is Figure 1 a schematic diagram of the structure of the sixth parasitic element sub-model in the small-signal model shown

[0111] Figure 8 is Figure 2 a three-dimensional electromagnetic simulation model corresponding to the first parasitic element sub-model shown

[0112] Figure 9 is Figure 3 a three-dimensional electromagnetic simulation model corresponding to the second parasitic element sub-model shown

[0113] Figure 10 is Figure 4 a three-dimensional electromagnetic simulation model corresponding to the third parasitic element sub-model shown

[0114] Figure 11 is Figure 5 a three-dimensional electromagnetic simulation model corresponding to the fourth parasitic element sub-model shown

[0115] Figure 12 is Figure 6 a three-dimensional electromagnetic simulation model corresponding to the fifth parasitic element sub-model for a double-hole transistor with a bridge

[0116] Figure 13 is Figure 6 a three-dimensional electromagnetic simulation model corresponding to the fifth parasitic element sub-model for a double-hole transistor without a bridge

[0117] Figure 14 is Figure 6 a three-dimensional electromagnetic simulation model corresponding to the fifth parasitic element sub-model for a single-hole transistor with a bridge

[0118] Figure 15 is Figure 7The sixth parasitic element sub-model shown corresponds to the three-dimensional electromagnetic simulation model of a double-hole transistor with a bridge.

[0119] Figure 16 For Figure 7 The sixth parasitic element sub-model shown corresponds to the three-dimensional electromagnetic simulation model of a double-hole transistor without a bridge.

[0120] Figure 17 For Figure 7 The sixth parasitic element sub-model shown corresponds to the three-dimensional electromagnetic simulation model of a single-hole transistor with a bridge.

[0121] Figure 18 This is the comparison graph of the S11 parameters between the circuit simulation result and the test result of the small-signal model of the double-hole transistor with a bridge in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0122] Figure 19 This is the comparison graph of the S12 parameters between the circuit simulation result and the test result of the small-signal model of the double-hole transistor with a bridge in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0123] Figure 20 This is the comparison graph of the S21 parameters between the circuit simulation result and the test result of the small-signal model of the double-hole transistor with a bridge in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0124] Figure 21 This is the comparison graph of the S22 parameters between the circuit simulation result and the test result of the small-signal model of the double-hole transistor with a bridge in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0125] Figure 22 This is the comparison graph of the S11 parameters between the circuit simulation result and the test result of the small-signal model of the double-hole transistor without a bridge in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0126] Figure 23 This is the comparison graph of the S12 parameters between the circuit simulation result and the test result of the small-signal model of the double-hole transistor without a bridge in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0127] Figure 24 The comparison diagram of S21 parameters between the circuit simulation results and the test results of the small-signal model of the double-hole bridge-less transistor in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0128] Figure 25 The comparison diagram of S22 parameters between the circuit simulation results and the test results of the small-signal model of the double-hole bridge-less transistor in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0129] Figure 26 The comparison diagram of S11 parameters between the circuit simulation results and the test results of the small-signal model of the single-hole bridge transistor in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0130] Figure 27 The comparison diagram of S12 parameters between the circuit simulation results and the test results of the small-signal model of the single-hole bridge transistor in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0131] Figure 28 The comparison diagram of S21 parameters between the circuit simulation results and the test results of the small-signal model of the single-hole bridge transistor in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0132] Figure 29 The comparison diagram of S22 parameters between the circuit simulation results and the test results of the small-signal model of the single-hole bridge transistor in the common amplification state (V gs = 0.2V, V ds = 0.6V) in the embodiment of the present invention.

[0133] Figure 30 The comparison diagram of the amplitudes of S21 parameters between the circuit simulation results and the test results of the small-signal models of three types of transistors in the common amplification state in the embodiment of the present invention.

[0134] Figure 31 The comparison diagram of the amplitudes of S11 parameters between the circuit simulation results and the test results of the small-signal models of three types of transistors in the common amplification state in the embodiment of the present invention. Detailed implementation manners

[0135] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the drawings and embodiments.

[0136] This embodiment provides a reconfigurable InP-based terahertz HEMT transistor small-signal model for different structures and a method for extracting its parameters. The topological structure of the small-signal model is as Figure 1 shown, including parasitic elements and intrinsic elements, having the following nodes: an external gate node G, an intrinsic gate node G1, an external drain node D, an intrinsic drain node D1, an external source node S, and an intrinsic source node S1.

[0137] More specifically:

[0138] The intrinsic elements include: a gate-source intrinsic capacitance C gs , a gate-source intrinsic resistance R i , a gate-drain intrinsic capacitance C gd , a gate-drain intrinsic resistance R gd , a drain-source intrinsic capacitance C ds , a drain-source intrinsic resistance R ds , and a voltage-controlled current source VCCS. Among them, the gate-source intrinsic capacitance C gs and the gate-source intrinsic resistance R i are connected in series between the intrinsic gate node G1 and the intrinsic source node S1. The gate-drain intrinsic capacitance C gd and the gate-drain intrinsic resistance R gd are connected in series between the intrinsic gate node G1 and the intrinsic drain node D1. The drain-source intrinsic capacitance C ds , the drain-source intrinsic resistance R ds , and the voltage-controlled current source VCCS are connected in parallel between the intrinsic drain node D1 and the intrinsic source node S1.

[0139] The parasitic elements include: an external gate parasitic impedance Z g , an external gate parasitic capacitance C g , a middle gate parasitic capacitance C gs_in , an internal gate parasitic capacitance C gs_finger , an internal gate parasitic impedance Z grf , an internal gate parasitic inductance L g_finger , a gate-drain parasitic capacitance C gd_finger , an internal drain parasitic impedance Z drf , an internal drain parasitic inductance L d_finger , an internal drain parasitic capacitance C ds_finger , a middle drain parasitic capacitance C ds_in , an external drain parasitic impedance Z d , an external drain parasitic capacitance C d , a source impedance Z srf, source parasitic inductance L s , variable gate middle parasitic capacitance ΔC gs_in , variable drain middle parasitic capacitance ΔC ds_in , variable gate internal parasitic capacitance ΔC gs_finger , variable drain internal parasitic capacitance ΔC ds_finger , variable source parasitic inductance ΔL s , variable source impedance ΔZ srf ; among them, the variable gate middle parasitic capacitance ΔC gs_in , variable drain middle parasitic capacitance ΔC ds_in , variable gate internal parasitic capacitance ΔC gs_finger , variable drain internal parasitic capacitance ΔC ds_finger , variable source parasitic inductance ΔL s , variable source impedance ΔZ srf are variable elements, whose values change according to different transistor structures, reflecting the changes of transistor parameters under different structures;

[0140] Among the parasitic elements, the external gate parasitic impedance Z g is connected in series with the external gate parasitic capacitance C g between the external gate node G and the external source node S. The external drain parasitic impedance Z d is connected in series with the external drain parasitic capacitance C d between the external drain node D and the external source node S. The source parasitic inductance L s is connected in series with the source impedance Z srf between the external source node S and the intrinsic source node S1. The gate middle parasitic capacitance C gs_in is connected in parallel with the variable gate middle parasitic capacitance ΔC gs_in between the external gate node G and the intrinsic source node S1. The drain middle parasitic capacitance C ds_in is connected in parallel with the variable drain middle parasitic capacitance ΔC ds_in between the external drain node D and the intrinsic source node S1. The gate internal parasitic impedance Z grf is connected in series with the gate internal parasitic inductance L g_finger between the external gate node G and the intrinsic gate node G1. The drain internal parasitic impedance Z drf is connected in series with the drain internal parasitic inductance L d_finger between the external drain node D and the intrinsic drain node D1. The gate internal parasitic capacitance C gs_finger is connected in parallel with the variable gate internal parasitic capacitance ΔC gs_finger between the intrinsic gate node G1 and the intrinsic source node S1. The drain internal parasitic capacitance C ds_fingerWith the variable drain internal parasitic capacitance ΔC ds_finger Connected in parallel and then connected between the intrinsic drain node D1 and the intrinsic source node S1. The gate-drain parasitic capacitance C gd_finger Is connected between the intrinsic gate node G1 and the intrinsic drain node D1. The variable source parasitic inductance ΔL s And the variable source impedance ΔZ srf Are connected in series and then connected between the external source node S and the intrinsic source node S1.

[0141] The core creation of the present invention lies in: the present invention introduces variable elements into the model to simulate different structure transistors and corresponding parameter extraction methods, and then classifies various transistors after the passive structure is changed under a unified model and parameter extraction method, making the physical meaning between different structure transistors clearer.

[0142] On this basis, this embodiment also provides a parameter extraction method for the above small-signal model; during the parameter extraction process, the transistor geometry is divided into 6 groups, which are respectively equivalent to 6 parasitic element sub-models, and the 6 groups of geometries are stepwise modeled and simulated through a three-dimensional electromagnetic field simulation software, and then a new method is used to achieve parameter extraction based on the simulation results; the present invention can accurately model double-hole with-bridge transistors (double-hole structure transistors including air bridges), single-hole with-bridge transistors (single-hole structure transistors including air bridges), and double-hole without-bridge transistors (double-hole structure transistors not including air bridges), greatly improving the applicable range of the model, and having the advantages of saving modeling time and improving the simulation accuracy of the small-signal model.

[0143] More specifically:

[0144] The first parasitic element sub-model: the external parasitic parameters of the gate and drain, and its structure is as Figure 2 Shown, including: the external parasitic impedance Z g Of the gate, the external parasitic capacitance C g Of the gate, the external parasitic impedance Z d Of the drain, the external parasitic capacitance C d Of the drain, and the included nodes are the external gate node G, the external drain node D, and the external source node S; the external parasitic impedance Z g Of the gate and the external parasitic impedance Z d Of the drain jointly simulate the parasitic effect of the gate transmission line; the external parasitic impedance Z d Of the drain and the external parasitic capacitance C d Of the drain jointly simulate the parasitic effect of the drain transmission line;

[0145] The second parasitic element sub-model: the external parasitic parameters of the source, and its structure is as Figure 3 Shown, including: the source impedance Z srf Of the source, the source parasitic inductance Ls , and variable source impedance ΔZ srf and variable source parasitic inductance ΔL s , including nodes such as external source node S and intrinsic source node S1, source impedance Z srf , source parasitic inductance L s , variable source parasitic inductance ΔL s , variable source impedance ΔZ srf The inductance of the analog vias and the impedance introduced by the skin effect;

[0146] The third parasitic element sub-model: the parasitic parameters introduced by the gate fingers, the structure of which is as Figure 4 shown, including: the first parasitic element sub-model, internal gate parasitic inductance L g_finger , internal gate parasitic impedance Z grf ; including nodes such as external source node S, external gate node G, external drain node D; internal gate parasitic inductance L g_finger , internal gate parasitic impedance Z grf respectively simulate the inductance of the gate fingers and the impedance introduced by the skin effect;

[0147] The fourth parasitic element sub-model: the parasitic parameters introduced by the drain metal strip, the structure of which is as Figure 5 shown, including: the first parasitic element sub-model, internal drain parasitic inductance L d_finger , internal drain parasitic impedance Z drf ; including nodes such as external source node S, external gate node G, external drain node D; internal drain parasitic inductance L d_finger , internal gate parasitic impedance Z drf respectively simulate the inductance of the drain metal strip and the impedance introduced by the skin effect;

[0148] The fifth parasitic element sub-model: the external parasitic parameters of the gate, drain, and source, the structure of which is as Figure 6 shown, including: the first parasitic element sub-model, the second parasitic element sub-model, middle gate parasitic capacitance C gs_in , middle drain parasitic capacitance C ds_in , and variable middle drain parasitic capacitance ΔC ds_in and variable middle gate parasitic capacitance ΔC gs_in ; including nodes such as external source node S, intrinsic source node S1, external gate node G, external drain node D; middle gate parasitic capacitance C gs_in and variable middle gate parasitic capacitance ΔC gs_in simulate the coupling effect between the gate transmission line and the source, and middle drain parasitic capacitance C ds_in and variable middle drain parasitic capacitance ΔC ds_in simulate the coupling effect between the drain transmission line and the source;

[0149] The sixth parasitic element sub-model: the overall parasitic parameters, whose structure is as Figure 7 shown, including all parasitic elements and nodes;

[0150] Meanwhile, the above 6 parasitic element sub-models include all connection lines between the corresponding elements in the aforementioned small-signal model and all connection lines between the elements and nodes.

[0151] Furthermore, in this embodiment, a 35nm InP-based HEMT transistor is taken as an example for illustration. Its test frequency band is 10 - 110GHz. Specifically, the existing 10 - 66GHz test system and 75 - 110GHz test system are used to achieve the test in segments; specifically, it includes the following steps:

[0152] Step 1: In the three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part and the drain transmission line part located on the upper surface of the dielectric layer, as Figure 8 shown; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band (10 - 110GHz), and calculate its Y parameters and Z parameters. Among them, the first port is set as the edge of the gate transmission line and the edge of the back gold, and the second port is set as the edge of the drain transmission line and the edge of the back gold;

[0153] The above model corresponds to the first parasitic element sub-model. By performing circuit analysis on the first parasitic element sub-model, the external parasitic impedance Z of the gate g , the external parasitic capacitance C of the gate g , the external parasitic impedance Z of the drain d , and the external parasitic capacitance C of the drain d are calculated by the following equations:

[0154]

[0155]

[0156]

[0157]

[0158] Among them, Z1(1,1) and Z1(2,2) represent the corresponding terms in the Z parameters calculated in Step 1. The im() and re() functions respectively represent taking the imaginary part and the real part. f represents the frequency, and f l and f h respectively represent the lower limit and the upper limit of the frequency used in the parameter extraction process; according to the test conditions of this embodiment, select f l and f hThey are 30 GHz and 60 GHz respectively;

[0159] Step 2: In a three-dimensional electromagnetic simulation software, model the partial structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the single source part and the source ground hole located on the upper surface of the dielectric layer, as Figure 9 shown; then perform a single-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculate the Z parameters, and further calculate the source impedance Z srf , the source parasitic inductance L s , the variable source parasitic inductance ΔL s , and the variable source impedance ΔZ srf . Set the port as the source edge and the back gold edge;

[0160] The above model corresponds to the second parasitic element sub-model. By performing circuit analysis on the second parasitic element sub-model, the source impedance Z srf , and the source parasitic inductance L s satisfy the following equations:

[0161]

[0162]

[0163] 1) For the double-hole transistor with a bridge, the variable source parasitic inductance ΔL s , and the variable source impedance ΔZ srf satisfy the following equations:

[0164]

[0165]

[0166] where Z2(1,1) represents the corresponding term in the Z parameters calculated in Step 2, the im() and re() functions respectively represent taking the imaginary part and the real part, f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process; according to the test conditions of this embodiment, select f l and f h to be 30 GHz and 60 GHz respectively;

[0167] 2) For the double-hole transistor without a bridge, the variable source parasitic inductance ΔL s , and the variable source impedance ΔZ srf satisfy the following equations:

[0168]

[0169]

[0170] 3) For a single-hole bridge transistor, the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf satisfy: ΔL s = +∞, ΔZ srf = +∞;

[0171] Step 3: In the three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back metal part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the drain transmission line part located on the upper surface of the dielectric layer, the gate transmission line part, the gate finger part and its extended part located on the upper surface of the dielectric layer, as Figure 10 shown; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters, and then calculate the internal gate parasitic inductance L g_finger , the internal gate parasitic impedance Z grf according to the Y parameters, where the first port is set to the edge of the gate transmission line and the edge of the back metal, and the second port is set to the edge of the drain transmission line and the edge of the back metal;

[0172] The above model corresponds to the third parasitic element sub-model. By performing circuit analysis on the third parasitic element sub-model, the internal gate parasitic inductance L g_finger , the internal gate parasitic impedance Z grf satisfy the following equation:

[0173]

[0174]

[0175] where Y3(2,1) represents the corresponding term in the Y parameters calculated in Step 3, the im() and re() functions respectively represent taking the imaginary part and the real part, f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process; according to the test conditions of this embodiment, select f l and f h to be 30 GHz and 60 GHz respectively;

[0176] Step 4: In the three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back metal part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part located on the upper surface of the dielectric layer, the drain transmission line part, the drain metal strip part and its extended part located on the upper surface of the dielectric layer, as Figure 11 shown; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters, and then calculate the internal drain parasitic inductance Ld_finger , the internal parasitic impedance Z of the drain drf , where the first port is set to the edge of the gate transmission line and the edge of the back metal, and the second port is set to the edge of the drain transmission line and the edge of the back metal;

[0177] The above model corresponds to the fourth parasitic element sub-model. By performing circuit analysis on the fourth parasitic element sub-model, the internal parasitic inductance L of the drain can be obtained d_finger , the internal parasitic impedance Z of the drain drf satisfies the following equation:

[0178]

[0179]

[0180] where Y4(2,1) represents the corresponding term in the Y-parameters calculated in step 4, and the functions im() and re() represent taking the imaginary part and the real part respectively, f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process; according to the test conditions of this embodiment, f l and f h are 30 GHz and 60 GHz respectively;

[0181] Step 5, in the three-dimensional electromagnetic simulation software, model the partial structures of the double-hole with-bridge transistor, double-hole without-bridge transistor, and single-hole with-bridge transistor; including: the substrate part, the back metal part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the drain transmission line part, and two source parts located on the upper surface of the dielectric layer; in addition to the above parts, for the double-hole with-bridge transistor, it also includes an air bridge connecting the two sources and two grounding holes, as Figure 12 shown; for the double-hole without-bridge transistor, it includes two grounding holes, as Figure 13 shown; for the single-hole with-bridge transistor, it also includes an air bridge connecting the two sources and a single grounding hole, as Figure 14 shown; then perform two-port three-dimensional electromagnetic simulation on the three types of transistors in the full frequency band, calculate the Y-parameters, and then calculate the gate-middle parasitic capacitance C gs_in , the drain-middle parasitic capacitance C ds_in , the variable gate-middle parasitic capacitance ΔC gs_in , the variable drain-middle parasitic capacitance ΔC ds_in , where the first port is set to the edge of the gate transmission line and the edge of the back metal, and the second port is set to the edge of the drain transmission line and the edge of the back metal;

[0182] Step 5 above corresponds to the fifth parasitic element sub-model. By performing circuit analysis on the fifth parasitic element sub-model, the parasitic capacitance C in the middle of the gate can be obtained. gs_in and the parasitic capacitance C in the middle of the drain ds_in satisfy the following equations:

[0183]

[0184]

[0185]

[0186]

[0187] where Y 5a (1,1), Y 5a (1,2), Y 5a (2,1), Y 5a (2,2) successively represent the corresponding terms in the Y-parameters calculated for the double-hole bridged transistor in Step 5. The im() and re() functions respectively represent taking the imaginary part and the real part. Y1(1,1) and Y1(2,2) respectively represent the corresponding terms in the Y-parameters calculated in Step 1. Z2(1,1) represents the corresponding term in the Z-parameters calculated in Step 2. f represents the frequency, f l and f h respectively represent the lower limit and the upper limit of the frequency adopted in the parameter extraction process; according to the test conditions of this embodiment, f l and f h are 30 GHz and 60 GHz respectively;

[0188] 1) For the double-hole bridged transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in and the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy:

[0189] ΔC gs_in = 0, ΔC ds_in = 0;

[0190] 2) For the double-hole non-bridged transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in and the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy the following equations:

[0191]

[0192]

[0193]

[0194]

[0195] Among them, Y 5b (1,1), Y 5b (1,2), Y 5b (2,1), Y 5b (2,2) respectively represent the corresponding items in the Y parameters calculated for the double - hole non - bridge transistor in step 5. Y 51b and Z 51b are the Y parameters and Z parameters of the same set of characteristics and can be converted into each other. Y 52b and Z 52b are the Y parameters and Z parameters of the same set of characteristics and can be converted into each other. The im() and re() functions respectively represent taking the imaginary part and the real part. Y1(1,1) and Y1(2,2) respectively represent the corresponding items in the Y parameters calculated in step 1. Z2(1,1) represents the corresponding item in the Z parameters calculated in step 2. f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process;

[0196] 3) For the single - hole with - bridge transistor, the variable gate - middle parasitic capacitance ΔC gs_in and the variable drain - middle parasitic capacitance ΔC ds_in satisfy the following equation:

[0197]

[0198]

[0199]

[0200]

[0201] Among them, Y 5c (1,1), Y 5c (1,2), Y 5c (2,1), Y 5c (2,2) respectively represent the corresponding items in the Y parameters calculated for the single - hole with - bridge transistor in step 5. Y 51c and Z 51c are the Y parameters and Z parameters of the same set of characteristics and can be converted into each other. Y 52c and Z 52c are the Y parameters and Z parameters of the same set of characteristics and can be converted into each other. The im() and re() functions respectively represent taking the imaginary part and the real part. Y1(1,1) and Y1(2,2) respectively represent the corresponding items in the Y parameters calculated in step 1. Z2(1,1) represents the corresponding item in the Z parameters calculated in step 2. f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process;

[0202] Step 6: In the 3D electromagnetic simulation software, model the complete structures of the double-hole bridged transistor, double-hole non-bridged transistor, and single-hole bridged transistor, including: the substrate part, the back metal part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the gate finger part, the drain transmission line, the drain metal strip part, and the two source parts located on the upper surface of the dielectric layer; in addition to the above parts, for the double-hole bridged transistor, it also includes an air bridge connecting the two sources and two ground vias, as Figure 15 shown; for the double-hole non-bridged transistor, it includes two ground vias, as Figure 16 shown; for the single-hole bridged transistor, it also includes an air bridge connecting the two sources and a single ground via, as Figure 17 shown; then perform two-port 3D electromagnetic simulation on the transistor in the full frequency band, calculate the Y parameters, and further calculate the gate-drain parasitic capacitance C gd_finger , drain internal parasitic capacitance C ds_finger , gate internal parasitic capacitance C gs_finger , variable gate internal parasitic capacitance ΔC gs_finger , variable drain internal parasitic capacitance ΔC ds_finger , where the first port is set as the edge of the gate transmission line and the edge of the back metal, and the second port is set as the edge of the drain transmission line and the edge of the back metal;

[0203] The above Step 6 corresponds to the sixth parasitic element sub-model. Performing circuit analysis on the sixth parasitic element sub-model can obtain that the gate-drain parasitic capacitance C gd_finger , drain internal parasitic capacitance C ds_finger , gate internal parasitic capacitance C gs_finger satisfy the following equations:

[0204]

[0205]

[0206]

[0207]

[0208]

[0209]

[0210]

[0211] Among them, Y 6a (1,1), Y 6a (1,2), Y 6a (2,1), Y6a (2, 2) successively represent the corresponding terms in the Y-parameters for the double-hole bridged transistor calculated in step 6, Y 61a and Z 61a are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other. Y 62a and Z 62a are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other. Y 63a and Z 63a are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other. Y 64a and Z 64a are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other; the im() and re() functions respectively represent taking the imaginary part and the real part. Y1(1, 1) and Y1(2, 2) respectively represent the corresponding terms in the Y-parameters calculated in step 1, Z2(1, 1) represents the corresponding term in the Z-parameters calculated in step 2, f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process. Y ca represents the influence caused by C gs_in and C ds_in and its value can be obtained by calculating the double-hole bridged transistor in step 5, as shown in the following formula:

[0212]

[0213] where, Y 52a (1, 1) and Y 52a (2, 2) are obtained by calculation in step 5, and j represents the imaginary unit;

[0214] Z rl represents the influence caused by the internal parasitic inductance L g_finger of the gate, the internal parasitic impedance Z grf of the gate, the internal parasitic inductance L d_finger of the drain, and the internal parasitic impedance Z drf of the drain, as shown in the following formula:

[0215]

[0216] where, Y3(2, 1) represents the corresponding term in the Y-parameters calculated in step 3, and Y4(2, 1) represents the corresponding term in the Y-parameters calculated in step 4;

[0217] 1) For the double-hole bridged transistor, the variable internal parasitic capacitance ΔC gs_finger of the gate and the variable internal parasitic capacitance ΔC ds_finger of the drain satisfy:

[0218] ΔC gs_finger = 0, ΔCds_finger = 0;

[0219] 2) For a double - hole bridge - less transistor, the variable gate internal parasitic capacitance ΔC gs_finger and the variable drain internal parasitic capacitance ΔC ds_finger satisfy the following equation:

[0220]

[0221]

[0222]

[0223]

[0224]

[0225]

[0226] where Y 6b (1,1), Y 6b (1,2), Y 6b (2,1), Y 6b (2,2) successively represent the corresponding terms in the Y - parameters for the double - hole bridge - less transistor calculated in step 6. Y 61b and Z 61b are the Y - parameters and Z - parameters of the same set of characteristics and can be converted into each other. Y 62b and Z 62b are the Y - parameters and Z - parameters of the same set of characteristics and can be converted into each other. Y 63b and Z 63b are the Y - parameters and Z - parameters of the same set of characteristics and can be converted into each other. Y 64b and Z 64b are the Y - parameters and Z - parameters of the same set of characteristics and can be converted into each other; the im() and re() functions respectively represent taking the imaginary part and the real part. Y1(1,1) and Y1(2,2) respectively represent the corresponding terms in the Y - parameters calculated in step 1. Z2(1,1) represents the corresponding term in the Z - parameters calculated in step 2. f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit adopted in the parameter extraction process. Y cb represents the influence caused by C gs_in and C ds_in and its value can be obtained by calculating the double - hole bridge - less transistor in step 5, as shown in the following formula:

[0227]

[0228] where Y 52b (1,1) and Y52b (2,2) is calculated in step 5;

[0229] 3) For a single-hole bridge transistor, the variable gate internal parasitic capacitance ΔC gs_finger and the variable drain internal parasitic capacitance ΔC ds_finger satisfy the following equation:

[0230]

[0231]

[0232]

[0233]

[0234]

[0235]

[0236] where Y 6c (1,1), Y 6c (1,2), Y 6c (2,1), Y 6c (2,2) successively represent the corresponding terms in the Y-parameters for the single-hole bridge transistor calculated in step 6. Y 61c and Z 61c are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other. Y 62c and Z 62c are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other. Y 63c and Z 63c are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other. Y 64c and Z 64c are the Y-parameters and Z-parameters of the same set of characteristics and can be converted into each other; the im() and re() functions respectively represent taking the imaginary part and the real part. Y1(1,1) and Y1(2,2) respectively represent the corresponding terms in the Y-parameters calculated in step 1. Z2(1,1) represents the corresponding term in the Z-parameters calculated in step 2. f represents the frequency, f l and f h respectively represent the lower limit and the upper limit of the frequency adopted in the parameter extraction process. Y cc represents the influence caused by C gs_in and C ds_in and its value can be obtained by calculating for the single-hole bridge transistor in step 5, as shown in the following formula:

[0237]

[0238] where Y 52c(1,1) and Y 52c (2,2) is obtained by calculation in step 5;

[0239] Step 7: Solve all the equations described in steps 1 to 6 to obtain the external parasitic impedance Z of the gate of the double-hole transistor with a bridge, the double-hole transistor without a bridge, and the single-hole transistor with a bridge g , the external parasitic capacitance C of the gate g , the middle parasitic capacitance C of the gate gs_in , the internal parasitic capacitance C of the gate gs_finger , the internal parasitic impedance Z of the gate grf , the internal parasitic inductance L of the gate g_finger , the gate-drain parasitic capacitance C gd_finger , the internal parasitic impedance Z of the drain drf , the internal parasitic inductance L of the drain d_finger , the internal parasitic capacitance C of the drain ds_finger , the middle parasitic capacitance C of the drain ds_in , the external parasitic impedance Z of the drain d , the external parasitic capacitance C of the drain d , the source impedance Z srf , the source parasitic inductance L s , the variable middle parasitic capacitance ΔC of the gate gs_in , the variable middle parasitic capacitance ΔC of the drain ds_in , the variable internal parasitic capacitance ΔC of the gate gs_finger , the variable internal parasitic capacitance ΔC of the drain ds_finger , the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf ;

[0240] Therefore, the present invention sets the initial values of these parasitic parameters as the parasitic parameters extracted in steps 1 to 6, and optimizes all the parasitic parameters according to the parasitic cost function to obtain the final parasitic parameters;

[0241] The parasitic cost function is:

[0242]

[0243] Wherein, J i,j and K i,j are both preset weights, J i,j = 0.125, K i,j = 0.125; S a (i,j) represents the circuit simulation result (S parameter) of the parasitic element, and S b (i,j) represents the three-dimensional electromagnetic simulation result; in this cost function, the former term represents the amplitude error and the latter term represents the phase error; based on this cost function, it has been disclosed in reference patent 1 and will not be elaborated here.

[0244] Based on the above steps, the typical values of the parasitic parameters extracted for the bridged double-hole transistor in this embodiment are shown in Table 1 as follows:

[0245] Table 1

[0246]

[0247] The typical values of the parasitic parameters extracted for the non-bridged double-hole transistor are shown in Table 2 as follows:

[0248] Table 2

[0249]

[0250] The typical values of the parasitic parameters extracted for the bridged single-hole transistor are shown in Table 3 as follows:

[0251] Table 3

[0252]

[0253]

[0254] After the above process of extracting the parasitic parameters, the extraction of the intrinsic parameters is carried out as follows:

[0255] Step 8: Measure the S-parameters of the transistor under full bias within the full frequency band, and calculate the corresponding Y-parameters and Z-parameters from the S-parameters; it should be noted that the input, output, and ground reference planes are points G, D, and S respectively. Since there are 2 test ports, the Y-parameters and Z-parameters respectively include parameters Y 11 , Y 12 , Y 21 , Y 22 and parameter Z 11 , Z 12 , Z 21 , Z 22 . The specific meaning of each parameter is common knowledge in the art and will not be elaborated here. The calculation processes of the S-parameters, Y-parameters, and Z-parameters also need not be elaborated;

[0256] Step 9: Based on the parasitic parameters of the parasitic elements extracted in Steps 1 to 7, perform de-embedding on the Y-parameters of the transistor measured in the full frequency band to obtain the intrinsic Y-parameter Y int ;

[0257] After de-embedding, the input, output, and ground reference planes become G1, D1, and S1 respectively, and only intrinsic elements are included; the intrinsic gate-source capacitance C gs , the intrinsic gate-source resistance R i , the intrinsic gate-drain capacitance C gd , the intrinsic gate-drain resistance R gd , the intrinsic drain-source capacitance C ds, Drain-source intrinsic resistance R ds , Voltage-controlled current source VCCS, with intrinsic parameters satisfying the following equations:

[0258]

[0259] where, g m represents the transconductance of the voltage-controlled current source VCCS, ω represents the angular frequency, and τ represents the delay of the voltage-controlled current source VCCS;

[0260] Step 10, Optimization of the intrinsic parameters of double-hole bridge transistors, double-hole non-bridge transistors, and single-hole bridge transistors;

[0261] Optimize the intrinsic parameters of double-hole bridge transistors, double-hole non-bridge transistors, and single-hole bridge transistors respectively according to the intrinsic cost function, and optimize all intrinsic parameters: gate-source intrinsic capacitance C gs , gate-source intrinsic resistance R i , gate-drain intrinsic capacitance C gd , gate-drain intrinsic resistance R gd , drain-source intrinsic capacitance C ds , drain-source intrinsic resistance R ds and the voltage-controlled current source VCCS to obtain the intrinsic parameter values;

[0262] The intrinsic cost function is:

[0263]

[0264] where, J i,j and K i,j are also preset weights, S c (i,j) represents the circuit simulation result of the small-signal model, and S d (i,j) represents the test result;

[0265] Fusion of the intrinsic parameters of the three types of transistors:

[0266] Calculate the average value of each intrinsic parameter of the three types of transistors after optimization, and use the following error function to evaluate the degree to which the respective intrinsic parameters of the double-hole bridge transistor, double-hole non-bridge transistor, and single-hole bridge transistor deviate from the average value; if the error is greater than or equal to 10%, then the intrinsic parameter remains unchanged (retain the optimized original value), if the error is less than 10%, then update the intrinsic parameter to the corresponding average value;

[0267] The error functions for the double-hole bridge transistor, double-hole non-bridge transistor, and single-hole bridge transistor are as follows:

[0268]

[0269] where, M a , Mb , M c are the intrinsic parameter values of the double-hole bridged transistor, double-hole non-bridged transistor, and single-hole bridged transistor, respectively. is the average value corresponding to the intrinsic parameter.

[0270] The intrinsic parameters finally extracted for the double-hole bridged transistor are shown in Table 4, the intrinsic parameters finally extracted for the double-hole non-bridged transistor are shown in Table 5, and the typical values of the intrinsic parameters finally extracted for the single-hole bridged transistor are shown in Table 6; by comparing Tables 4, 5, and 6, it can be found that C gd , C gs , C ds , R gd , g m , τ elements remain unchanged, while R i , R ds have certain changes, which are caused by the influence of the passive structure on the active layer; therefore, in the model, C gd , C gs , C ds , R gd , g m , τ elements are shared by the three transistors, and R i , R ds elements are assigned values respectively.

[0271] Table 4

[0272] <![CDATA[C gd (fF)]]> <![CDATA[C gs (fF)]]> <![CDATA[C ds (fF)]]> <![CDATA[R gd (Ω)]]> 5 25 2 50 <![CDATA[R i (Ω)]]> <![CDATA[R ds (Ω)]]> <![CDATA[g m (mS)]]> τ (ps) 2 170 69 0

[0273] Table 5

[0274] <![CDATA[C gd (fF)]]> <![CDATA[C gs (fF)]]> <![CDATA[C ds (fF)]]> <![CDATA[R gd (Ω)]]> 5 25 2 50 <![CDATA[R i (Ohm)]]> <![CDATA[R ds (Ohm)]]> <![CDATA[g m (mS)]]> τ (ps) 2 140 69 0

[0275] Table 6

[0276] <![CDATA[C gd (fF)]]> <![CDATA[C gs (fF)]]> <![CDATA[C ds (fF)]]> <![CDATA[R gd (ohm) <!-- 20 -->]]> 5 25 2 50 <![CDATA[R i (Ω)]]> <![CDATA[R ds (Ohm)]]> <![CDATA[g m (mS)]]> τ (ps) 22 160 69 0

[0277] Furthermore, for the 35nm InP HEMT transistor in this embodiment, under the common amplification state (bias points: V gs = 0.2V, V ds = 0.6V) for verification, based on the parasitic parameters in Table 1 and the intrinsic parameters in Table 4, the comparison between the circuit simulation results and the test results of the double-hole bridged transistor model is as Figures 18 to 21 shown; based on the parasitic parameters in Table 2 and the intrinsic parameters in Table 5, the comparison between the circuit simulation results and the test results of the double-hole non-bridged transistor model is as Figures 22 to 25 shown; based on the parasitic parameters in Table 3 and the intrinsic parameters in Table 6, the comparison between the circuit simulation results and the test results of the single-hole bridged transistor model is as Figures 26 to 29As shown; it can be seen from the figure that for the double-hole bridge-less transistor, the small-signal model of the present invention also achieves high accuracy and can better simulate the device performance in the amplification state; the amplitude comparison of the S21 and S11 parameters between the circuit simulation results and the test results of the transistors with three structures is as Figure 30 and Figure 31 shown. It can be seen from the figure that in terms of the S21 gain and the S11 input port reflection coefficient, the single-hole bridge transistor shows a decrease compared with the other transistors, while the reconfigurable model proposed by the present invention can accurately simulate the three models respectively.

[0278] In summary, the present invention proposes a small-signal model of an InP-based terahertz HMET transistor and its parameter extraction method, which can extend the modeling scope to common types of double-hole bridge transistors, single-hole bridge transistors, and double-hole bridge-less transistors, effectively saving the modeling time and significantly improving the simulation accuracy of the small-signal model.

[0279] The above is only the specific implementation manner of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similar-purpose alternative features; all the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A reconfigurable model of an InP terahertz transistor, comprising: Parasitic elements and intrinsic elements; characterized in that The parasitic elements include: the external gate parasitic impedance Z g , the external gate parasitic capacitance C g , the middle gate parasitic capacitance C gs_in , the internal gate parasitic capacitance C gs_finger , the internal gate parasitic impedance Z grf , the internal gate parasitic inductance L g_finger , the gate-drain parasitic capacitance C gd_finger , the internal drain parasitic impedance Z drf , the internal drain parasitic inductance L d_finger , the internal drain parasitic capacitance C ds_finger , the middle drain parasitic capacitance C ds_in , the external drain parasitic impedance Z d , the external drain parasitic capacitance C d , the source impedance Z srf , the source parasitic inductance L s , the variable middle gate parasitic capacitance ΔC gs_in , the variable middle drain parasitic capacitance ΔC ds_in , the variable internal gate parasitic capacitance ΔC gs_finger , the variable internal drain parasitic capacitance ΔC ds_finger , the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf ; where The external parasitic impedance Z of the gate g is connected in series with the external parasitic capacitance C of the gate g between the external gate node G and the external source node S. The external parasitic impedance Z of the drain d is connected in series with the external parasitic capacitance C of the drain d between the external drain node D and the external source node S. The source parasitic inductance L s is connected in series with the source impedance Z srf between the external source node S and the intrinsic source node S1. The parasitic capacitance C in the middle of the gate gs_in is connected in parallel with the variable parasitic capacitance ΔC in the middle of the gate gs_in between the external gate node G and the intrinsic source node S1. The parasitic capacitance C in the middle of the drain ds_in is connected in parallel with the variable parasitic capacitance ΔC in the middle of the drain ds_in between the external drain node D and the intrinsic source node S1. The internal parasitic impedance Z of the gate grf is connected in series with the internal parasitic inductance L of the gate g_finger between the external gate node G and the intrinsic gate node G1. The internal parasitic impedance Z of the drain drf is connected in series with the internal parasitic inductance L of the drain d_finger between the external drain node D and the intrinsic drain node D1. The internal parasitic capacitance C of the gate gs_finger is connected in parallel with the variable internal parasitic capacitance ΔC of the gate gs_finger between the intrinsic gate node G1 and the intrinsic source node S1. The internal parasitic capacitance C of the drain ds_finger is connected in parallel with the variable internal parasitic capacitance ΔC of the drain ds_finger between the intrinsic drain node D1 and the intrinsic source node S1. The gate-drain parasitic capacitance C gd_finger is connected between the intrinsic gate node G1 and the intrinsic drain node D1. The variable source parasitic inductance ΔL s is connected in series with the variable source impedance ΔZ srf between the external source node S and the intrinsic source node S1.

2. The reconfigurable model of the InP terahertz transistor according to claim 1, characterized in that, The intrinsic element includes: gate-source intrinsic capacitance C gs , gate-source intrinsic resistance R i , gate-drain intrinsic capacitance C gd , gate-drain intrinsic resistance R gd , drain-source intrinsic capacitance C ds , drain-source intrinsic resistance R ds and a voltage-controlled current source VCCS. Among them, the gate-source intrinsic capacitance C gs is connected in series with the gate-source intrinsic resistance R i between the intrinsic gate node G1 and the intrinsic source node S1. The gate-drain intrinsic capacitance C gd is connected in series with the gate-drain intrinsic resistance R gd between the intrinsic gate node G1 and the intrinsic drain node D1. The drain-source intrinsic capacitance C ds , the drain-source intrinsic resistance R ds are connected in parallel with the voltage-controlled current source VCCS between the intrinsic drain node D1 and the intrinsic source node S1.

3. The parameter extraction method for the reconfigurable model of the InP terahertz transistor according to claim 1 includes: Parasitic parameter extraction and intrinsic parameter extraction; characterized in that the parasitic parameter extraction includes the following steps: Step 1: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part and the drain transmission line part located on the upper surface of the dielectric layer; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters and Z parameters, and further calculate the external parasitic impedance Z of the gate according to the Z parameters g , the external parasitic capacitance C of the gate g , the external parasitic impedance Z of the drain d , the external parasitic capacitance C of the drain d ; Step 2: In the 3D electromagnetic simulation software, model the partial structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the single source part and the source ground via located on the upper surface of the dielectric layer; then perform a single-port 3D electromagnetic simulation on the transistor in the full frequency band, calculate the Z parameters, and further calculate the source impedance Z srf , the source parasitic inductance L s , the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf ; Step 3: In the three-dimensional electromagnetic simulation software, model some structures of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the gate finger part and its extended part located on the upper surface of the dielectric layer; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters, and further calculate the internal gate parasitic inductance L g_finger , the internal gate parasitic impedance Z grf ; Step 4: In a three-dimensional electromagnetic simulation software, model part of the structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the drain transmission line part, the drain metal strip part and its extended part located on the upper surface of the dielectric layer; then perform two-port three-dimensional electromagnetic simulation on the transistor within the full frequency band, calculate the Y parameters, and further calculate the internal parasitic inductance L of the drain according to the Y parameters d_finger , the internal parasitic impedance Z of the drain drf ; Step 5: In the three-dimensional electromagnetic simulation software, model some structures of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the drain transmission line part, and two source parts located on the upper surface of the dielectric layer; for the double-hole transistor with a bridge, it also includes an air bridge connecting the two sources and two ground holes; for the double-hole transistor without a bridge, it also includes two ground holes; for the single-hole transistor with a bridge, it also includes an air bridge connecting the two sources and a single ground hole; then perform two-port three-dimensional electromagnetic simulations on the three types of transistors respectively in the full frequency band, calculate the Y parameters, and further calculate the parasitic capacitance C at the middle of the gate of the three types of transistors according to the Y parameters gs_in , the parasitic capacitance C at the middle of the drain ds_in , the variable parasitic capacitance ΔC at the middle of the gate gs_in , the variable parasitic capacitance ΔC at the middle of the drain ds_in ; Step 6: In a three-dimensional electromagnetic simulation software, model the complete structure of the transistor, including: the substrate part, the back gold part located on the lower surface of the substrate, the dielectric layer part located on the upper surface of the substrate, the gate transmission line part, the gate finger part, the drain transmission line, the drain metal bar part, and two source parts located on the upper surface of the dielectric layer; for a double-hole transistor with a bridge, it also includes an air bridge connecting the two sources and two ground vias; for a double-hole transistor without a bridge, it also includes two ground vias; for a single-hole transistor with a bridge, it also includes an air bridge connecting the two sources and a single ground via; then perform two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculate the Y parameters, and further calculate the gate-drain parasitic capacitance C gd_finger , the internal parasitic capacitance C ds_finger of the drain, the internal parasitic capacitance C gs_finger of the gate, the variable internal parasitic capacitance ΔC gs_finger of the gate, and the variable internal parasitic capacitance ΔC ds_finger of the drain; Step 7: Set the external parasitic impedance Z of the gate g , the external parasitic capacitance C of the gate g , the middle parasitic capacitance C of the gate gs_in , the internal parasitic capacitance C of the gate gs_finger , the internal parasitic impedance Z of the gate grf , the internal parasitic inductance L of the gate g_finger , the gate-drain parasitic capacitance C gd_finger , the internal parasitic impedance Z of the drain drf , the internal parasitic inductance L of the drain d_finger , the internal parasitic capacitance C of the drain ds_finger , the middle parasitic capacitance C of the drain ds_in , the external parasitic impedance Z of the drain d , the external parasitic capacitance C of the drain d , the source impedance Z srf , the source parasitic inductance L s , the variable middle parasitic capacitance ΔC of the gate gs_in , the variable middle parasitic capacitance ΔC of the drain ds_in , the variable internal parasitic capacitance ΔC of the gate gs_finger , the variable internal parasitic capacitance ΔC of the drain ds_finger , the variable source parasitic inductance ΔL s , the variable source impedance ΔZ srf to the parasitic parameters extracted in Steps 1 - 6, and optimize all the parasitic parameters according to the parasitic cost function to obtain the final parasitic parameters.

4. The parameter extraction method of the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that, In Step 1, the external parasitic impedance Z of the gate g , the external parasitic capacitance C of the gate g , the external parasitic impedance Z of the drain d , the external parasitic capacitance C of the drain d satisfy the following equation: Among them, Z1(1,1) and Z1(2,2) represent the corresponding items of the Z parameter in step 1, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

5. The method for parameter extraction of the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that In step 2, the source impedance Z srf and the source parasitic inductance L s satisfy the following equation: For a two-hole bridged transistor, the variable source parasitic inductance ΔL s and the variable source impedance ΔZ srf satisfy the following equation: For a dual-gate bridge-less transistor, the variable source parasitic inductance ΔL s and the variable source impedance ΔZ srf satisfy the following equation: For a single-hole bridge transistor, the variable source parasitic inductance ΔL s and the variable source impedance ΔZ srf satisfy: ΔL s = +∞, ΔZ srf = +∞; Among them, Z2(1,1) represents the corresponding item of the Z parameter in step 2, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

6. The parameter extraction method for the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that, In step 3, the internal parasitic inductance L of the gate g_finger and the internal parasitic impedance Z of the gate grf satisfy the following equation: Among them, Y3(2,1) represents the corresponding item of the Y parameter in step 3, f represents the frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

7. The parameter extraction method of the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that, In step 4, the internal parasitic inductance L of the drain d_finger and the internal parasitic impedance Z of the drain drf satisfy the following equation: Among them, Y4(2,1) represents the corresponding item in the Y parameter in step 4, f represents frequency, f l and f h represent the lower frequency limit and the upper frequency limit respectively.

8. The method for parameter extraction of the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that In step 5, the parasitic capacitance C in the middle of the gate gs_in , and the parasitic capacitance C in the middle of the drain ds_in satisfy the following equation: Among them, Y 5a (1,1), Y 5a (1,2), Y 5a (2,1), Y 5a (2,2) successively represent the corresponding terms of the Y-parameters for the double-hole bridge transistor in step 5, Y1(1,1) and Y1(2,2) respectively represent the corresponding terms of the Y-parameters in step 1, Z2(1,1) represents the corresponding term of the Z-parameters in step 2, f represents the frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit; For a two-hole bridge transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in and the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy: ΔC gs_in = 0, ΔC ds_in = 0; For a double-hole bridge-less transistor, the variable parasitic capacitance ΔC in the middle of the gate gs_in and the variable parasitic capacitance ΔC in the middle of the drain ds_in satisfy the following equation: Among them, Y 5b (1,1), Y 5b (1,2), Y 5b (2,1), Y 5b (2,2) successively represent the corresponding items of the Y-parameters for the double-hole non-bridge transistor in step 5; For a single-hole bridge transistor, the variable gate middle parasitic capacitance ΔC gs_in and the variable drain middle parasitic capacitance ΔC ds_in satisfy the following equation: Among them, Y 5c (1,1), Y 5c (1,2), Y 5c (2,1), Y 5c (2,2) successively represent the corresponding items of the Y parameters of the single-hole bridge transistor in step 5.

9. The parameter extraction method for the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that In step 6, the gate-drain parasitic capacitance C gd_finger , the internal drain parasitic capacitance C ds_finger , and the internal gate parasitic capacitance C gs_finger satisfy the following equation: Among them, Y 6a (1,1), Y 6a (1,2), Y 6a (2,1), Y 6a (2,2) successively represent the corresponding terms of the Y parameter for the double-hole bridge transistor in step 6. Y1(1,1) and Y1(2,2) respectively represent the corresponding terms of the Y parameter in step 1. Z2(1,1) represents the corresponding term of the Z parameter in step 2. Y 52a (1,1), Y 52a (2,2) respectively represent the corresponding terms of the Y parameter in step 5. Y3(2,1) represents the corresponding term of the Y parameter in step 3. Y4(2,1) represents the corresponding term of the Y parameter in step 4. f represents frequency, f l and f h respectively represent the lower frequency limit and the upper frequency limit; For a double - hole bridge transistor, the variable gate internal parasitic capacitance ΔC gs_finger and the variable drain internal parasitic capacitance ΔC ds_finger satisfy: ΔC gs_finger = 0, ΔC ds_finger = 0; For a dual-gate bridge-less transistor, the variable gate internal parasitic capacitance ΔC gs_finger and the variable drain internal parasitic capacitance ΔC ds_finger satisfy the following equation: Among them, Y 6b (1,1), Y 6b (1,2), Y 6b (2,1), Y 6b (2,2) successively represent the corresponding items of the Y-parameters for the double-hole non-bridge transistor in step 6; Y 52b (1,1), Y 52b (2,2) respectively represent the corresponding items of the Y-parameters in step 5; For a single-hole bridge transistor, the variable gate internal parasitic capacitance ΔC gs_finger and the variable drain internal parasitic capacitance ΔC ds_finger satisfy the following equation: Among them, Y 6c (1,1), Y 6c (1,2), Y 6c (2,1), Y 6c (2,2) successively represent the corresponding items of the Y-parameters for the single-hole bridge transistor in step 6. Y 52c (1,1), Y 52c (2,2) respectively represent the corresponding items of the Y-parameters in step 5.

10. The parameter extraction method for the reconfigurable model of the InP terahertz transistor according to claim 3, characterized in that, The intrinsic parameter extraction includes the following steps: Step 8, measure the S-parameters of the transistor under full bias in the full frequency band, and calculate the corresponding Y-parameters and Z-parameters from the S-parameters; Step 9: Based on the parasitic parameters obtained in Step 7, de-embed the full-band test Y-parameters of the transistor to obtain the intrinsic Y-parameters Y int ; and then, based on the intrinsic Y-parameters Y int calculate the intrinsic parameters: intrinsic gate-source capacitance C gs , intrinsic gate-source resistance R i , intrinsic gate-drain capacitance C gd , intrinsic gate-drain resistance R gd , intrinsic drain-source capacitance C ds , intrinsic drain-source resistance R ds , and voltage-controlled current source VCCS; Step 10, optimization of the intrinsic parameters of the double-hole transistor with a bridge, the double-hole transistor without a bridge, and the single-hole transistor with a bridge; Optimize the intrinsic parameters of the double-hole transistor with a bridge, the double-hole transistor without a bridge, and the single-hole transistor with a bridge respectively according to the intrinsic cost function; Then, according to the optimized intrinsic parameters, perform decision fusion on the intrinsic parameters of the double-hole transistor with a bridge, the double-hole transistor without a bridge, and the single-hole transistor with a bridge: Calculate the average value of each intrinsic parameter respectively, and calculate the error function respectively: Among them, M a , M b , M c are the intrinsic parameter values of the double-hole transistor with a bridge, the double-hole transistor without a bridge, and the single-hole transistor with a bridge respectively, is the average value corresponding to the intrinsic parameter; If the error is greater than or equal to 10%, the intrinsic parameter remains unchanged; if the error is less than 10%, the intrinsic parameter is updated to the corresponding average value.

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