Circuit, method and liquid crystal display device for attenuating noise
By distributing the filter capacitors on each sub-line in the LCD panel circuit system, the problem of high vibration and noise of MLCC capacitors is solved, achieving noise reduction without increasing costs.
Patent Information
- Application Number
- CN202310187718.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-20
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2043-02-20
AI Technical Summary
The vibration noise generated by MLCC capacitors in the LCD panel circuit system is relatively large, which causes the product noise index to fail to meet the standard, affecting production and increasing costs.
In the LCD panel circuit system, filter capacitors are distributed on each sub-line, and the number of filter capacitors on each sub-line is determined by calculation using a formula to reduce vibration concentration and noise.
By optimizing the circuit layout, the concentrated effect of capacitor vibration was reduced, the noise level was lowered, and the product delivery requirements were met without increasing costs.
Smart Images
Figure CN116259283B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of liquid crystal panel, and particularly relates to a circuit and method for reducing noise and a liquid crystal display device. BACKGROUND
[0002] At present, a plurality of chip multilayer ceramic capacitors (MLCC capacitors for short) are arranged on a step control voltage branch of a liquid crystal panel circuit system to filter a ripple. The plurality of capacitors vibrate to cause large noise. The noise requirement of the liquid crystal panel product is quite strict. If the noise index of the product does not meet the specified requirement, the product cannot be shipped, the production and manufacturing of the enterprise are affected, and serious consequences are caused.
[0003] For this problem, the enterprise cannot reduce the number of MLCC capacitors. If the number of MLCC capacitors is insufficient, the ripple specification cannot be met. The enterprise cannot directly use tantalum capacitors, which increases the manufacturing cost and is not beneficial to the market planning and positioning of the product. Therefore, the enterprise is currently in a dilemma. SUMMARY
[0004] To solve the technical problem of large vibration noise of the MLCC capacitor of the current liquid crystal panel product, an embodiment of the present application provides a circuit and method for reducing noise and a liquid crystal display device.
[0005] The technical scheme of the embodiment of the present application is implemented as follows:
[0006] The embodiment of the present application provides a circuit for reducing noise. The circuit comprises an integrated power management circuit, an output bus of the integrated power management circuit, a plurality of sub-circuits connected with an output port of the output bus, and a filter capacitor arranged on each sub-circuit, the filter capacitor being used for filtering a current on each sub-circuit.
[0007] In an embodiment, the filter capacitor comprises a chip multilayer ceramic capacitor.
[0008] In an embodiment, a plurality of sub-circuits directly connected with the output port of the output bus are defined as first-level sub-circuits.
[0009] The filter capacitor is arranged on the first-level sub-circuit.
[0010] In an embodiment, the number of the filter capacitors on the first-level sub-circuit is determined by using the following formula:
[0011] P=N / M*Q
[0012] Wherein, P represents the number of filter capacitors on the first level sub-circuit, N represents the current value on the first level sub-circuit, M represents the current value on the output bus, and Q represents the number of filter capacitors originally arranged on the bus.
[0013] In an embodiment, a plurality of sub-circuits indirectly connected with the output port of the output bus are defined as N level sub-circuits, wherein N is greater than 1.
[0014] The filter capacitors are arranged on the N level sub-circuits.
[0015] In an embodiment, the number of filter capacitors on the N level sub-circuits is determined by the following formula:
[0016] P' = N' / M'*Q'
[0017] Wherein, P' represents the number of filter capacitors on the N level sub-circuit, N' represents the current value on the N level sub-circuit, M' represents the current value on the output bus, and Q' represents the number of filter capacitors originally arranged on the bus.
[0018] In an embodiment, a plurality of sub-circuits directly connected with the output port of the output bus are defined as first level sub-circuits, and a plurality of sub-circuits indirectly connected with the output port of the output bus are defined as N level sub-circuits, wherein N is greater than 1.
[0019] The filter capacitors are arranged on part of the first level sub-circuits and the N level sub-circuits connected with another part of the first level sub-circuits.
[0020] In an embodiment, the number of filter capacitors on the first level sub-circuits and the N level sub-circuits is determined by the following formula:
[0021] P'' = N'' / M''*Q''
[0022] Wherein, P'' represents the number of filter capacitors on the first level or N level sub-circuit, N'' represents the current value on the first level or N level sub-circuit, M'' represents the current value on the output bus, and Q'' represents the number of filter capacitors originally arranged on the bus.
[0023] The embodiment of the present application also provides a noise reduction method, which comprises: dispersively arranging filter capacitors on a plurality of sub-circuits connected with the output port of the output bus of the integrated power management circuit, wherein the filter capacitors are used for filtering the current on each sub-circuit.
[0024] The embodiment of the present application also provides a liquid crystal display device, which comprises the circuit according to any one of the above embodiments.
[0025] The circuit, method and liquid crystal display device for reducing noise provided by the embodiment of the present application, the circuit comprises an integrated power management circuit, an output bus of the integrated power management circuit, a plurality of sub-circuits connected with the output port of the output bus, and a filter capacitor dispersedly arranged on each sub-circuit, the filter capacitor is used for filtering the current on each sub-circuit. The scheme provided by the present application can disperse the layout of the capacitor by dispersing the capacitor for filtering the current on each sub-circuit on each sub-circuit, filter the current on each sub-circuit, only generate vibration in the local area where the capacitor is arranged, and cannot concentrate vibration, thereby reducing noise. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 The structure schematic diagram of the circuit for reducing noise of the embodiment of the present application;
[0027] Figure 2 The placement position schematic diagram of the filter capacitor in the prior art;
[0028] Figure 3 The placement position schematic diagram of the filter capacitor in the first improvement scheme of the embodiment of the present application;
[0029] Figure 4 The placement position schematic diagram of the filter capacitor in the second improvement scheme of the embodiment of the present application;
[0030] Figure 5 The flowchart schematic diagram of the first method for reducing noise of the embodiment of the present application;
[0031] Figure 6 The flowchart schematic diagram of the second method for reducing noise of the embodiment of the present application;
[0032] Figure 7 The flowchart schematic diagram of the third method for reducing noise of the embodiment of the present application. DETAILED DESCRIPTION
[0033] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.
[0034] The embodiment of the present application provides a circuit for reducing noise, referring to Figure 1 The circuit comprises:
[0035] An integrated power management circuit PMIC, an output bus A of the integrated power management circuit, a plurality of sub-circuits B connected with the output port of the output bus, and a filter capacitor MLCC dispersedly arranged on each sub-circuit B, the filter capacitor MLCC is used for filtering the current on each sub-circuit B.
[0036] The embodiment analyzes the cause of noise generation, finds that due to the physical characteristics of the MLCC capacitor itself, it cannot block the vibration itself, and therefore can only reduce the influence of the vibration to reduce noise. Based on the vibration characteristics of the MLCC capacitor, the embodiment disperses the position of the capacitor, and the filter capacitor arranged on the bus is dispersed and arranged on each sub-circuit, so that the capacitor only vibrates in the local area and cannot concentrate vibration, thereby reducing the noise caused by the MLCC capacitor vibration. That is, the corresponding number of capacitors is placed in each branch, and the capacitors are not arranged together, so that the vibration caused by a single capacitor is reduced, only a certain vibration intensity is generated in the area where each capacitor is located, and the surrounding area is not affected, thereby reducing the influence of the MLCC capacitor vibration and reducing noise without increasing cost.
[0037] In actual application, the filter capacitor can be arranged on the sub-circuit in the following several ways.
[0038] The first kind:
[0039] In an embodiment, a plurality of sub-circuits directly connected with the output port of the output bus are defined as first-level sub-circuits; and the filter capacitor is arranged on the first-level sub-circuit.
[0040] Specifically, the number of filter capacitors on the first-level sub-circuit can be determined by the following formula:
[0041] P=N / M*Q
[0042] Wherein, P represents the number of filter capacitors on the first-level sub-circuit, N represents the current value on the first-level sub-circuit, M represents the current value on the output bus, and Q represents the number of filter capacitors originally arranged on the bus.
[0043] For example, the bus current is divided into 3 times. The bus current is 800mA, the filter capacitor on the original bus is 8, the bus current is divided into 2 first-level sub-circuits for the first time, and the current value on each first-level sub-circuit is 400mA; the current on each first-level sub-circuit is divided into 2 second-level sub-circuits for the second time, and the current value on each second-level sub-circuit is 200mA; the current on each second-level sub-circuit is divided into 2 final sub-circuits for the third time, and the current value on each final sub-circuit is 100mA. The filter capacitor can be dispersed and arranged on the first-level sub-circuit after the first time, and the number of filter capacitors arranged on each first-level sub-circuit can be 8 times 400mA divided by 800mA, which is 4.
[0044] The second kind:
[0045] In an embodiment, a plurality of sub-lines indirectly connected with the output port of the output bus are defined as N-level sub-lines; wherein N is greater than 1; the filter capacitor is arranged on the N-level sub-lines.
[0046] Specifically, the number of filter capacitors on the N-level sub-lines can be determined by the following formula:
[0047] P' = N' / M'*Q'
[0048] Wherein P' represents the number of filter capacitors on the N-level sub-lines, N' represents the current value on the N-level sub-lines, M' represents the current value on the output bus, and Q' represents the number of filter capacitors originally arranged on the bus.
[0049] For example, the bus current is divided into 3 times. The bus current is 800mA, the filter capacitors originally on the bus are 8, the bus current is divided into 2 first-level sub-lines in the first time, the current value on each first-level sub-line is 400mA; the current on each first-level sub-line is divided into 2 second-level sub-lines in the second time, the current value on each second-level sub-line is 200mA; the current on each second-level sub-line is divided into 2 final-level sub-lines in the third time, the current value on each final-level sub-line is 100mA. The filter capacitors can be arranged on the second-level sub-lines after the second time of division, and the number of filter capacitors arranged on each second-level sub-line can be 8 times 200mA divided by 800mA, which is 2.
[0050] The third:
[0051] In an embodiment, a plurality of sub-lines directly connected with the output port of the output bus are defined as first-level sub-lines; a plurality of sub-lines indirectly connected with the output port of the output bus are defined as N-level sub-lines; wherein N is greater than 1; the filter capacitors are arranged on part of the first-level sub-lines and the N-level sub-lines connected with another part of the first-level sub-lines.
[0052] Specifically, the number of filter capacitors on the first-level sub-lines and the N-level sub-lines can be determined by the following formula:
[0053] P" = N" / M"*Q"
[0054] Wherein P" represents the number of filter capacitors on the first-level or N-level sub-lines, N" represents the current value on the first-level or N-level sub-lines, M" represents the current value on the output bus, and Q" represents the number of filter capacitors originally arranged on the bus.
[0055] For example, the bus current is divided twice. The bus current is 800 mA, and the filter capacitor on the original bus is 8. The bus current is divided into two first-level sub-lines in the first division, and the current value of each first-level sub-line is 400 mA. Each first-level sub-line current is divided into two second-level sub-lines in the second division, and the current value of each second-level sub-line is 200 mA. The filter capacitor can be distributed on a first-level sub-line after the first division and two second-level sub-lines connected to the other first-level sub-line. The number of filter capacitors on a first-level sub-line can be 8 times 400 mA divided by 800 mA, which is 4. The number of filter capacitors on two second-level sub-lines can be 8 times 200 mA divided by 800 mA, which is 2.
[0056] That is, the embodiment changes the layout of the elements on the circuit board, so that the arrangement of the capacitors is relatively dispersed, the vibration amplitude of the capacitors in each branch is reduced, thereby weakening the overall vibration effect, and achieving the effect of reducing product noise.
[0057] The embodiment scheme does not increase any material cost, but only optimizes the circuit layout and changes the placement position of the MLCC capacitor, thereby improving the noise. The embodiment scheme does not increase the cost and product development cycle, and can be combined with other noise optimization methods to achieve a more ideal noise improvement effect. For example, the embodiment method can be combined with the following methods to achieve a better noise improvement effect: when the capacitor pads on the bus line are optimized in the layout, strip slotting and area slotting are performed on the circuit board to minimize the contact between the MLCC capacitor and the surrounding circuit board and device, so that it vibrates in a separate island area, which can avoid causing vibration around, thereby further reducing noise.
[0058] Further, to describe the embodiment in detail, a detailed embodiment will be described below.
[0059] The embodiment takes the AVDD line as an example for description. In actual application, the noise at AVDD is more obvious, which is easy to cause noise out of specification. The scheme in the prior art is described in Figure 2, integrated power management circuit (Power Management IC, PMIC for short) generates analog circuit power AVDD, AVDD will be through each 6 branches to the panel and other IC. The current on each branch is 100 mA, and the current on the bus is the sum of the currents on each branch, so the current value of the bus can be measured at J in the figure is 600 mA. The prior art is to place 6 capacitors on the AVDD bus (i.e. the positions of C1 to C6 in the figure). This placement method produces obvious vibration superposition due to the concentration of capacitors, and the noise is large, and the measured noise is 25.9 dBA, which exceeds the specified standard of 24 dBA, and cannot meet the requirements of product delivery.
[0060] Based on the above scenario, the following two improvement methods can be used in the embodiment scheme:
[0061] (1) Improvement scheme one
[0062] Referring to Figure 3 Since the AVDD line is divided into two directions of the upper and lower branches, the current on each branch is 300 mA. Therefore, the capacitor position can be moved to the upper and lower two sub-buses, i.e. 3 capacitors are placed on the upper bus, and 3 capacitors are placed on the lower bus. That is, 3 capacitors are placed at the positions of sub-buses C1 to C3 in the figure, and 3 capacitors are placed at the positions of sub-buses C4 to C6 in the figure.
[0063] Due to the dispersion of capacitors, the measured noise is 22.8 dBA, which does not exceed the specified standard of 24 dBA, and meets the requirements of product delivery, and the noise problem is improved.
[0064] (2) Improvement scheme two
[0065] Referring to Figure 4 On the basis of the improvement scheme one, the branch is further subdivided, and the capacitor position is moved to each branch, i.e. one capacitor is placed on each branch. Since the current values measured at JL1, JL2, JL3 and JR1, JR2, JR3 in the figure are 100 mA, one capacitor can be placed on each of the three subdivided branches C1 to C3 on the upper side, and one capacitor can be placed on each of the three subdivided branches C4 to C6 on the lower side.
[0066] Due to the further dispersion of capacitors, the measured noise is 18.8 dBA, which is much lower than the specified standard of 24 dBA, and further improves the noise problem.
[0067] The vibration of the MLCC capacitor is up and down vibration, which can drive the vibration of the surrounding board and device, and cause noise. If a large number of capacitors are placed on the PMIC output bus, the capacitors are placed together, the vibration is superimposed and interacts with each other, so that the vibration in the region is quite obvious, and the noise is large. The filter capacitors originally placed on the bus are distributed to each branch, and the vibration is weakened due to the dispersion of the capacitors, so that the noise is reduced. And since fewer capacitors are placed on each branch, the filter function on the branch can also be realized, and the actual effect is equivalent to placing a large number of capacitors on the bus. Compared with the bus, the current, signal and the like borne by each branch are distributed, and the corresponding pressure is reduced. Therefore, without placing so many filter capacitors on the bus, the corresponding effect can be achieved.
[0068] The embodiment optimizes the layout of the components on the circuit board, disperses the layout of the capacitors, does not concentrate vibration, reduces product noise without increasing material development cost, and improves the influence of MLCC capacitor vibration.
[0069] The circuit provided by the embodiment of the present application includes an integrated power management circuit, an output bus of the integrated power management circuit, a plurality of sub-circuits after the output bus is branched, and filter capacitors dispersedly arranged on each sub-circuit, the filter capacitors are used for filtering the current on each sub-circuit. The scheme provided by the present application disperses the capacitors for filtering on the bus to each sub-circuit, filters the current on each sub-circuit, disperses the layout of the capacitors, only generates vibration in the local area where the capacitors are located, does not concentrate vibration, and thus reduces noise.
[0070] The embodiment of the present application provides a noise reduction method, which comprises the following steps:
[0071] The filter capacitors are dispersedly arranged on a plurality of sub-circuits connected with the output port of the output bus of the integrated power management circuit, and the filter capacitors are used for filtering the current on each sub-circuit.
[0072] The embodiment can be applied to the step control voltage circuit (referred to as vaa circuit) of the liquid crystal panel circuit system or the analog power circuit (referred to as AVDD circuit).
[0073] The filter capacitors in the embodiment include MLCC capacitors.
[0074] In practical applications, the bus current can be branched multiple times. The filtering capacitors can be distributed on the first-stage sub-circuit after the first branching, or on the N-stage sub-circuit after the multiple branching. For example, the bus current is branched three times. After the first branching, the bus current is branched into two first-stage sub-circuit currents; after the second branching, each first-stage sub-circuit current is branched into three second-stage sub-circuit currents; and after the third branching, each second-stage sub-circuit current is branched into four third-stage sub-circuit currents. The filtering capacitors can be distributed on the first-stage sub-circuit after the first branching, on the second-stage sub-circuit after the second branching, or on the third-stage sub-circuit after the third branching. In addition, the filtering capacitors can be distributed on part of the first-stage sub-circuits and on the N-stage sub-circuit connected to another part of the first-stage sub-circuits. For example, the bus current is branched twice. The bus current is 800 mA, and the filtering capacitors on the bus are eight. After the first branching, the bus current is branched into two first-stage sub-circuit currents, each with a current value of 400 mA. After the second branching, each first-stage sub-circuit current is branched into two second-stage sub-circuit currents, each with a current value of 200 mA. The filtering capacitors can be distributed on one of the first-stage sub-circuits after the first branching and on the two second-stage sub-circuits connected to the other first-stage sub-circuit. The number of filtering capacitors distributed on one of the first-stage sub-circuits can be eight multiplied by 400 mA divided by 800 mA, i.e., four, and the number of filtering capacitors distributed on the two second-stage sub-circuits can be eight multiplied by 200 mA divided by 800 mA, i.e., two.
[0075] The following three ways of setting the filtering capacitors will be described in detail below based on the scenario of multiple branching of the bus current.
[0076] The first way of setting the filtering capacitors is as follows.
[0077] In an embodiment, referring to Figure 5 , the method comprises the following steps.
[0078] Step 101: When the bus current is branched multiple times, defining the sub-circuit after the first branching as a first-stage sub-circuit.
[0079] Step 102: Distributing the filtering capacitors on the bus on the first-stage sub-circuit.
[0080] Specifically, when setting the filtering capacitors, the first ratio of the current value on the first-stage sub-circuit to the current value on the bus can be obtained first. The first number of filtering capacitors distributed on the first-stage sub-circuit is determined by multiplying the number of filtering capacitors distributed on the bus by the first ratio. The first number of filtering capacitors is distributed on the first-stage sub-circuit.
[0081] For example, the bus current is divided into three times. The bus current is 800mA, and the filter capacitor on the original bus is 8. The bus current is divided into two first-level sub-lines in the first time, and the current value of each first-level sub-line is 400mA. The current of each first-level sub-line is divided into two second-level sub-lines in the second time, and the current value of each second-level sub-line is 200mA. The current of each second-level sub-line is divided into two final-level sub-lines in the third time, and the current value of each final-level sub-line is 100mA. The filter capacitor can be distributed on the first-level sub-line after the first time of division, and the number of filter capacitors set on each first-level sub-line can be 8 multiplied by 400mA divided by 800mA, which is 4.
[0082] The second filter capacitor setting mode is:
[0083] In an embodiment, referring to Figure 6 , the method comprises:
[0084] Step 201: When the bus current is divided into multiple times, the sub-line after the Nth time of division is defined as an N-level sub-line; wherein N is greater than 1;
[0085] Step 202: The filter capacitor set on the bus is distributed on the N-level sub-line.
[0086] Specifically, when setting the filter capacitor, the second ratio of the current value on the N-level sub-line to the current value on the bus can be obtained first. The number of filter capacitors set on the bus is multiplied by the second ratio to determine the second number of filter capacitors set on the N-level sub-line. The second number of filter capacitors is set on the N-level sub-line.
[0087] For example, the bus current is divided into three times. The bus current is 800mA, and the filter capacitor on the original bus is 8. The bus current is divided into two first-level sub-lines in the first time, and the current value of each first-level sub-line is 400mA. The current of each first-level sub-line is divided into two second-level sub-lines in the second time, and the current value of each second-level sub-line is 200mA. The current of each second-level sub-line is divided into two final-level sub-lines in the third time, and the current value of each final-level sub-line is 100mA. The filter capacitor can be distributed on the second-level sub-line after the second time of division, and the number of filter capacitors set on each second-level sub-line can be 8 multiplied by 200mA divided by 800mA, which is 2.
[0088] The third filter capacitor setting mode is:
[0089] In an embodiment, referring to Figure 7 , the method comprises:
[0090] Step 301: when the bus current is shunted for multiple times, a sub-circuit after the first shunting is defined as a first-level sub-circuit, and a sub-circuit after the Nth shunting is defined as an N-level sub-circuit; wherein N is greater than 1;
[0091] Step 302: the filter capacitors arranged on the bus are dispersedly arranged on part of the first-level sub-circuits and the N-level sub-circuits connected with another part of the first-level sub-circuits.
[0092] Specifically, when arranging the filter capacitors, a third ratio of the current value on the first-level sub-circuit to the current value on the bus can be obtained; a third number of filter capacitors arranged on the first-level sub-circuit is determined by multiplying the number of filter capacitors arranged on the bus by the third ratio; the third number of filter capacitors is arranged on the first-level sub-circuit; a fourth ratio of the current value on the N-level sub-circuit to the current value on the bus is obtained; a fourth number of filter capacitors arranged on the N-level sub-circuit is determined by multiplying the number of filter capacitors arranged on the bus by the fourth ratio; and the fourth number of filter capacitors is arranged on the N-level sub-circuit.
[0093] For example, the bus current is shunted for two times. The bus current is 800 mA, the filter capacitors on the original bus are 8, the bus current is shunted for the first time and is divided into two first-level sub-circuits, and the current value on each first-level sub-circuit is 400 mA; the current on each first-level sub-circuit is shunted for the second time and is further divided into two second-level sub-circuits, and the current value on each second-level sub-circuit is 200 mA. The filter capacitors can be dispersedly arranged on one first-level sub-circuit after the first shunting and two second-level sub-circuits connected with another first-level sub-circuit. The number of filter capacitors arranged on one first-level sub-circuit can be 8 multiplied by 400 mA divided by 800 mA, which is 4, and the number of filter capacitors arranged on two second-level sub-circuits can be 8 multiplied by 200 mA divided by 800 mA, which is 2.
[0094] The noise reduction method provided by the embodiment of the present application can disperse the filter capacitors arranged on the bus to each sub-circuit to filter the current on each sub-circuit, so that the layout of the capacitors is dispersed, vibration is generated only in the local area where the capacitors are arranged, and vibration is not concentrated, thereby reducing noise.
[0095] The embodiment of the present application further provides a liquid crystal display device, which comprises the circuit described in the above embodiment.
[0096] The circuit, the liquid crystal display device and the method provided in the embodiment belong to the same concept, and the specific implementation process is described in the circuit embodiment, which will not be described here.
[0097] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.
[0098] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.
Claims
1. A noise attenuating circuit, characterized by, The circuit comprises: The integrated power management circuit, the output bus of the integrated power management circuit, a plurality of sub-circuits connected with the output port of the output bus, and filter capacitors distributed on each sub-circuit for filtering the current on each sub-circuit; the total number of filter capacitors on each sub-circuit is consistent with the number of filter capacitors originally arranged on the bus.
2. The circuit of claim 1, wherein, The filter capacitors comprise chip multilayer ceramic capacitors.
3. The circuit of claim 1, wherein, The plurality of sub-circuits directly connected with the output port of the output bus are defined as first-level sub-circuits. The filter capacitors are arranged on the first-level sub-circuits.
4. The circuit of claim 3, wherein, The number of filter capacitors on the first-level sub-circuits is determined by the following formula: P=N / M*Q Wherein, P represents the number of filter capacitors on the first-level sub-circuits, N represents the current value on the first-level sub-circuits, M represents the current value on the output bus, and Q represents the number of filter capacitors originally arranged on the bus.
5. The circuit of claim 1, wherein, The plurality of sub-circuits indirectly connected with the output port of the output bus are defined as N-level sub-circuits; wherein, N is greater than 1. The filter capacitors are arranged on the N-level sub-circuits.
6. The circuit of claim 5, wherein, The number of filter capacitors on the N-level sub-circuits is determined by the following formula: P’=N’ / M’*Q’ Wherein, P’ represents the number of filter capacitors on the N-level sub-circuits, N’ represents the current value on the N-level sub-circuits, M’ represents the current value on the output bus, and Q’ represents the number of filter capacitors originally arranged on the bus.
7. The circuit of claim 1, wherein, The plurality of sub-circuits directly connected with the output port of the output bus are defined as first-level sub-circuits; the plurality of sub-circuits indirectly connected with the output port of the output bus are defined as N-level sub-circuits; wherein, N is greater than 1. The filter capacitors are arranged on part of the first-level sub-circuits and the N-level sub-circuits connected with another part of the first-level sub-circuits.
8. The circuit of claim 7, wherein, The number of filter capacitors on the first-level sub-circuits and the N-level sub-circuits is determined by the following formula: P”=N” / M”*Q” Wherein, P” represents the number of filter capacitors on the first-level or N-level sub-circuits, N” represents the current value on the first-level or N-level sub-circuits, M” represents the current value on the output bus, and Q” represents the number of filter capacitors originally arranged on the bus.
9. A method of attenuating noise, characterized by, The method comprises: Distributing filter capacitors on a plurality of sub-circuits connected with the output port of the output bus of the integrated power management circuit, the filter capacitors being used for filtering the current on each sub-circuit; the total number of filter capacitors on each sub-circuit is consistent with the number of filter capacitors originally arranged on the bus.
10. A liquid crystal display device, characterized by comprising: The liquid crystal display device comprises the circuit according to any one of claims 1-8.
Citation Information
Patent Citations
Power supplying unit and liquid crystal display device including the same
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