A method for fabricating SDB of fin field effect transistor

Abstract

The application provides a preparation method of SDB of fin field effect transistor, which comprises the following steps: forming parallel fins on the semiconductor substrate, the surface of the fins is provided with a hard mask layer, and a first silicon oxide layer covering the fins and the hard mask layer is formed on the semiconductor substrate; grinding the first silicon oxide layer to expose the surface of the hard mask layer; forming a photoresist layer on the surface of the first silicon oxide layer, and patterning the photoresist layer to define an SDB area; taking the patterned photoresist layer as a mask to etch the hard mask layer and the fins, forming an SDB groove, and removing the photoresist layer; depositing a second silicon oxide layer in the hard mask layer, the first silicon oxide layer and the SDB groove; and grinding the second silicon oxide layer to expose the surface of the hard mask layer and the first silicon oxide layer. The first silicon oxide layer is firstly subjected to a chemical mechanical grinding process for planarization, and then an etching process is performed to form the SDB groove, so that the depth difference caused by the load effect can be reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and particularly relates to a preparation method of SDB of a fin field effect transistor. BACKGROUND

[0002] With the semiconductor industry entering into the 16nm and below technology nodes, the design of three-dimensional structures such as fin field effect transistors (FinFET) has become a hot spot in the field.

[0003] In a FinFET, a double diffusion break (DDB) structure and a single diffusion break (SDB) structure are usually adopted to realize the isolation of an active region, and the width of the active region of a device unit such as a logic standard cell is calculated according to a contacted poly pitch (CPP). The DDB structure includes at least two dummy gate structures, while the SDB structure only needs to occupy the width of one dummy gate structure. Therefore, the DDB needs to additionally increase one CPP width, and the SDB can set the width of the active region to be minimum. The device density formed by the SDB process is higher, and the device area is smaller. The SDB process technology is usually adopted in the process nodes below 14nm.

[0004] As shown in FIG. 1, the preparation method of the SDB in the existing common FinFET mainly includes the following steps: Figures 1a-3c

[0005] Step one, as shown in FIG. 2, a plurality of fin bodies 2a arranged in parallel are formed on a semiconductor substrate 1a, then a photoresist layer 5a covering the fin bodies 2a is formed on the semiconductor substrate 1a, and the photoresist layer 5a is patterned along the longitudinal direction perpendicular to the length direction of the fin bodies 2a. Figure 1a The photoresist layer 5a is not shown in FIG. 3, and the dashed rectangular part is the SDB region to be etched. Figure 1b Figure 1c Step two, as shown in FIG. 4, the fin bodies 2a are etched with the patterned photoresist layer 5a as a mask to form SDB grooves 6a. Figure 1d Figure 1a Step three, as shown in FIG. 5, the photoresist layer 5a between and on the surface of the fin bodies 2a is removed.

[0006] Figure 2a Figure 2b Figure 2c

[0007] Figure 3a Figure 3b Figure 3c ​​​​​​​​​​​

[0008] Depend on Figures 1a-3c It can be seen that the different densities of the fins 2a at different locations result in different thicknesses of the photoresist layer 5a formed above the fins 2a with different pattern densities. That is, the photoresist exhibits a significant thickness loading effect: the denser the fins 2a, the thicker the resulting photoresist layer 5a, and vice versa. With a fixed etching amount, this causes differences in the depth of the SDB region. Where the photoresist is thicker, the etched SDB grooves are shallower (thickness D2); where the photoresist is thinner, the etched SDB grooves are deeper (thickness D1). This leads to differences in the insulation performance of the subsequently formed devices. Therefore, it is necessary to improve the SDB process. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating SDB of a fin field-effect transistor, which solves the problem of inconsistent SDB groove depth in the prior art.

[0010] To achieve the above and other related objectives, the present invention provides a method for fabricating a fin field-effect transistor (SDB), the method comprising at least:

[0011] 1) A semiconductor substrate is provided, on which parallel fins are formed, the surface of the fins having a hard mask layer, and a first silicon oxide layer covering the fins and the hard mask layer is formed on the semiconductor substrate;

[0012] 2) Grind the first silicon oxide layer until the surface of the hard mask layer is exposed;

[0013] 3) A photoresist layer is formed on the surface of the first silicon oxide layer, and the photoresist layer is patterned to define the SDB region;

[0014] 4) Using the patterned photoresist layer as a mask, etch the hard mask layer and the fin to form an SDB groove, and remove the photoresist layer;

[0015] 5) Deposit a second silicon oxide layer in the hard mask layer, the first silicon oxide layer, and the SDB trench;

[0016] 6) Polish the second silicon oxide layer until the surface of the hard mask layer and the first silicon oxide layer is exposed.

[0017] Preferably, in step 1), a first silicon oxide layer covering the fin and the hard mask layer is formed on the semiconductor substrate using a chemical vapor deposition process.

[0018] Preferably, the hard mask layer includes an oxide layer and a nitride layer formed on the surface of the oxide layer.

[0019] Preferably, in step 2), the grinding comprises chemical mechanical grinding.

[0020] Preferably, the photoresist layer comprises a multi-layer photoresist stack structure.

[0021] Preferably, in step 3), the direction of the SDB region is perpendicular to the length direction of the fin body.

[0022] Preferably, in step 4), a dry etching process is used to etch the hard mask layer and the fin body to form the SDB groove.

[0023] Preferably, in step 5), a chemical vapor deposition process is used to deposit a second silicon oxide layer in the hard mask layer, the first silicon oxide layer and the SDB groove.

[0024] Preferably, in step 6), the grinding comprises chemical mechanical grinding.

[0025] As described above, the SDB preparation method of the fin field effect transistor of the present application has the following beneficial effects:

[0026] 1. The first silicon oxide layer is used to replace the traditional photoresist material to fill the gap between the fins, which has good filling effect and can be directly used as the insulating material between the fins, thus simplifying the process.

[0027] 2. The first silicon oxide layer is first subjected to a chemical mechanical grinding process for planarization, and then subjected to an etching process to form the SDB groove, which can reduce the depth difference caused by the load effect. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figures 1a-1d It is a structural schematic diagram of step one of the SDB preparation method of the prior art fin field effect transistor.

[0029] Among them, Figure 1a is a top view, Figure 1b is a sectional view of Fig. 1 along the direction of BB', Figure 1c is a sectional view of Fig. 1 along the direction of CC', Figure 1d is a sectional view of Fig. 1 along the direction of AA'.

[0030] Figures 2a-2c It is a structural schematic diagram of step two of the SDB preparation method of the prior art fin field effect transistor.

[0031] Figures 3a-3c It is a structural schematic diagram of step three of the SDB preparation method of the prior art fin field effect transistor.

[0032] Figures 4a-4bStructure diagram of step 1) of the SDB preparation method of the fin field effect transistor of the present application.

[0033] Figures 5a-5b Structure diagram of step 2) of the SDB preparation method of the fin field effect transistor of the present application.

[0034] Figures 6a-6b Structure diagram of step 3) of the SDB preparation method of the fin field effect transistor of the present application.

[0035] Figures 7a-7b Structure diagram of step 4) of the SDB preparation method of the fin field effect transistor of the present application.

[0036] Figures 8a-8b Structure diagram of step 5) of the SDB preparation method of the fin field effect transistor of the present application.

[0037] Figures 9a-9b Structure diagram of step 6) of the SDB preparation method of the fin field effect transistor of the present application.

[0038] Figure 10 Flow chart of the SDB preparation method of the fin field effect transistor of the present application.

[0039] Element number explanation

[0040] 1, 1a semiconductor substrate

[0041] 2, 2a fin

[0042] 3 hard mask layer

[0043] 4 first silicon oxide layer

[0044] 5, 5a photoresist layer

[0045] 6, 6a SDB groove

[0046] 7 second silicon oxide layer DETAILED DESCRIPTION

[0047] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is construed that persons skilled in the art on the basis of the contents disclosed in the present specification can easily understand other advantages and effects of the present application. The present application can also be implemented or applied by other different embodiments, and each detail in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0048] Please refer to the drawings. It should be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the drawings, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component type, number and proportion can be a random change, and the component layout type can also be more complex.

[0049] The present application provides a fin field effect transistor SDB preparation method, as shown in Figure 10 Figure 10 The present application provides a fin field effect transistor SDB preparation method, as shown in

[0050] 1) Provide a semiconductor substrate, form parallel fins on the semiconductor substrate, the surface of the fin has a hard mask layer, and form a first silicon oxide layer on the semiconductor substrate covering the fin and the hard mask layer. As shown in Figure 4a and Figure 4b As shown in Figure 4a is a cross-sectional view perpendicular to the length direction of the fin, that is, a longitudinal cross-sectional view, Figure 4b is a cross-sectional view along the length direction of the fin, that is, a transverse cross-sectional view. In step 1), parallel fins 2 are formed on the semiconductor substrate 1, the surface of the fin 2 has a hard mask layer 3, and a first silicon oxide layer 4 is formed on the semiconductor substrate 1 covering the fin 2 and the hard mask layer 3.

[0051] Further, in step 1) of the present embodiment, a chemical vapor deposition process is used to form a first silicon oxide layer 4 on the semiconductor substrate 1 covering the fin 2 and the hard mask layer 3.

[0052] Further, the hard mask layer 3 can include an oxide layer and a nitride layer formed on the surface of the oxide layer. The oxide layer can be silicon dioxide, and the nitride layer can be silicon nitride.

[0053] This step uses silicon dioxide material (first silicon oxide layer) to replace the traditional photoresist material to fill the gap between the fin 2, which has good filling effect and can be directly used as insulation material between the fins 2, simplifying the process.

[0054] 2) Grind the first silicon oxide layer to expose the surface of the hard mask layer. As shown in Figure 5a and Figure 5b As shown in Figure 5a is a longitudinal cross-sectional view after grinding the first silicon oxide layer; Figure 5b is a transverse cross-sectional view after grinding the first silicon oxide layer. In step 2), the first silicon oxide layer 5 is ground to expose the surface of the hard mask layer 3.​

[0055] Further, in step 2) of the embodiment, the grinding includes chemical mechanical grinding.

[0056] In this step, a grinding and planarization process is performed with the hard mask layer 3 (such as the top silicon nitride in the hard mask layer) as a barrier layer. Through the grinding and planarization process, the problem of inconsistent thickness of the first silicon oxide layer 4 due to different densities of the fin 2 at different positions can be eliminated, and the thickness loading effect can be avoided.

[0057] 3) Forming a photoresist layer on the surface of the first silicon oxide layer, and patterning the photoresist layer to define an SDB region. As shown in Figure 6a and Figure 6b , wherein, Figure 6a is a longitudinal sectional view after the photoresist layer is patterned; Figure 6b is a transverse sectional view after the photoresist layer is patterned. In this step 3), a photoresist layer 5 is formed on the surface of the first silicon oxide layer 4, and the photoresist layer 5 is patterned to define an SDB region.

[0058] Further, the photoresist layer 5 includes a multilayer photoresist stack structure. For example, it can be a three-layer photoresist stack structure, the top layer of photoresist is used for patterning, and the bottom layer of photoresist has good adhesion and filling properties, which improves the resolution and accuracy of photoetching.

[0059] Further, in step 3) of the embodiment, the direction of the SDB region is perpendicular to the length direction of the fin 2.

[0060] 4) Using the patterned photoresist layer as a mask, etching the hard mask layer and the fin to form an SDB groove, and removing the photoresist layer. As shown in Figure 7a and Figure 7b , wherein, Figure 7a is a longitudinal sectional view after the SDB groove is formed; Figure 7b is a transverse sectional view after the SDB groove is formed. In this step 4), the patterned photoresist layer 5 is used as a mask to etch the hard mask layer 3 and the fin 2, to form an SDB groove 6, and the photoresist layer 5 is removed.

[0061] Further, in step 4) of the embodiment, a dry etching process is used to etch the hard mask layer 3 and the fin 2 to form the SDB groove 6.

[0062] 5) Depositing a second silicon oxide layer in the hard mask layer, the first silicon oxide layer, and the SDB groove. As shown in Figure 8a and Figure 8b , wherein, Figure 8a is a longitudinal sectional view after the SDB groove is formed;Figure 8b is a cross-sectional view after forming the SDB recess. In step 5), a second silicon oxide layer 7 is deposited in the hard mask layer 3, the first silicon oxide layer 4, and the SDB recess 6.

[0063] Further, in step 5) of the embodiment, a chemical vapor deposition process is used to deposit the second silicon oxide layer 7 in the hard mask layer 3, the first silicon oxide layer 4, and the SDB recess 6.

[0064] 6) Polishing the second silicon oxide layer to expose the surfaces of the hard mask layer and the first silicon oxide layer. As shown in FIG. 6, Figure 9a and Figure 9b wherein, Figure 9a is a longitudinal cross-sectional view after forming the SDB recess; Figure 9b is a cross-sectional view after forming the SDB recess. In step 6), the second silicon oxide layer 7 is polished to expose the surfaces of the hard mask layer 3 and the first silicon oxide layer 4.

[0065] Further, in step 6) of the embodiment, the polishing includes chemical mechanical polishing.

[0066] In summary, the first silicon oxide layer is used to replace the conventional photoresist material to fill the gap between the fins, and the filling effect is good. The first silicon oxide layer can be directly used as an insulating material between the fins, and the process is simplified. The first silicon oxide layer is first planarized by a chemical mechanical polishing process, and then etched to form the SDB recess, which can reduce the depth difference caused by the load effect.

[0067] Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0068] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a fin field-effect transistor (SF-SDB), characterized in that, The preparation method includes at least: 1) Provide a semiconductor substrate, on which parallel fins are formed, the density of the fins at different positions is different, the surface of the fins has a hard mask layer, and a first silicon oxide layer covering the fins and the hard mask layer is formed on the semiconductor substrate; 2) Grind the first silicon oxide layer until the surface of the hard mask layer is exposed; 3) A photoresist layer is formed on the surface of the first silicon oxide layer, and the photoresist layer is patterned to define the SDB region; 4) Using the patterned photoresist layer as a mask, etch the hard mask layer and the fin to form an SDB groove, and remove the photoresist layer; 5) Deposit a second silicon oxide layer in the hard mask layer, the first silicon oxide layer, and the SDB trench; 6) Polish the second silicon oxide layer until the surface of the hard mask layer and the first silicon oxide layer is exposed.

2. The SDB fabrication method of the fin field-effect transistor according to claim 1, characterized in that: In step 1), a first silicon oxide layer covering the fin and the hard mask layer is formed on the semiconductor substrate using a chemical vapor deposition process.

3. The SDB fabrication method of the fin field-effect transistor according to claim 1, characterized in that: The hard mask layer includes an oxide layer and a nitride layer formed on the surface of the oxide layer.

4. The SDB fabrication method of the fin field-effect transistor according to claim 1, characterized in that: In step 2), the grinding includes chemical mechanical grinding.

5. The method for fabricating a fin field-effect transistor (SDB) according to claim 1, characterized in that: The photoresist layer comprises a multilayer photoresist stack structure.

6. The SDB fabrication method of the fin field-effect transistor according to claim 1, characterized in that: In step 3), the direction of the SDB region is perpendicular to the length direction of the fin.

7. The method for fabricating a fin field-effect transistor (SDB) according to claim 1, characterized in that: In step 4), the hard mask layer and the fin are etched using a dry etching process to form an SDB groove.

8. The method for fabricating a fin field-effect transistor (SDB) according to claim 1, characterized in that: In step 5), a second silicon oxide layer is deposited in the hard mask layer, the first silicon oxide layer and the SDB groove using a chemical vapor deposition process.

9. The method for fabricating an SDB (Small Base Diode) of a fin field-effect transistor according to claim 1, characterized in that: In step 6), the grinding includes chemical mechanical grinding.

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