Semiconductor device and power conversion device

Abstract

A semiconductor device is provided which suppresses operation failure of a semiconductor switching element. The semiconductor device (20) includes: first circuits (3) to which semiconductor switching elements (11) are connected in parallel, the semiconductor switching elements (11) having a first electrode, a second electrode, and a third electrode, and controlling the second electrode and the third electrode to be conductive or non-conductive in accordance with a voltage between the first electrode and the third electrode; and a control unit (15) connected to the first electrode of each semiconductor switching element (11) and controlling the voltage between the first electrode and the third electrode, configured to ensure a first condition in which an impedance Zg in a first path between the first electrodes of the semiconductor switching elements (11) is set to be greater than an impedance Zs in a third path between the third electrodes of the semiconductor switching elements (11) by a predetermined value or more.

Description

Technical Field

[0001] This application relates to semiconductor devices and power conversion devices. Background Technology

[0002] In recent years, power conversion devices used in electric powertrains, such as hybrid vehicles and electric vehicles, that transmit power between the engine and drive wheels, have employed power modules that incorporate semiconductor switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). By connecting multiple such power modules in parallel and driving them to switch simultaneously, the power capacity processed is increased.

[0003] In this type of power conversion device, due to the difference in characteristics between power modules caused by the difference in characteristics of the semiconductor switching elements built into the multiple power modules connected in parallel, and the deviation of the inductance of the main circuit or control circuit in which the power modules are assembled, the timing of the switching of the semiconductor switching elements between power modules may sometimes be offset. Previously, due to timing deviations in the switching, current imbalances occurred between power modules. For example, current concentrated in the power module that turned on earliest, increasing losses and sometimes causing malfunctions in that power module. To address this issue, for example, a power conversion device has been disclosed that includes a semiconductor module with a semiconductor device structured as follows.

[0004] That is, in existing power conversion devices, the main circuit section consists of multiple semiconductor modules connected in parallel, and includes a gate drive circuit for turning on / off each semiconductor module, and a first gate wiring for the turn-off operation. This first gate wiring is provided in each semiconductor module and connects the semiconductor module to the gate drive circuit or other semiconductor modules. Furthermore, semiconductor modules with lower gate threshold voltages are connected to the gate drive circuit or other semiconductor modules through a first gate wiring with lower impedance, so that the gate current values ​​of each semiconductor module are the same during the turn-off operation (for example, see Patent Document 1). Existing technical documents Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-156304 Summary of the Invention The technical problem that the invention aims to solve

[0006] In the aforementioned existing power conversion device, in order to suppress the current imbalance caused by the timing offset of the switching between parallel connected semiconductor modules, the semiconductor module with the lower gate threshold voltage is connected to the gate drive circuit or other semiconductor modules through the first gate wiring with the lower impedance. By setting up such a structure, the gate current imbalance between each semiconductor module is suppressed. However, even when the structure shown in Patent Document 1 is used, the following problem exists: in the semiconductor switching element built into the parallel-connected semiconductor module, malfunctions such as false arcing sometimes occur. This application discloses a technology for solving the above-mentioned problems, the purpose of which is to provide a semiconductor device for suppressing operational faults generated between parallel-connected semiconductor switching elements, and a power conversion device having the semiconductor device. Technical means for solving technical problems

[0007] The semiconductor device disclosed in this application includes: A first circuit, wherein a semiconductor switching element is connected in parallel, the semiconductor switching element having a first electrode, a second electrode, and a third electrode, wherein the voltage between the first electrode and the third electrode is used to control the connection between the second electrode and the third electrode to be either on or off; and A control unit, connected to the first electrode of each of the semiconductor switching elements, controls the voltage between the first electrode and the third electrode in this semiconductor device. The condition is configured to ensure that the impedance Zg in the first path between the first electrodes of each semiconductor switching element is greater than the impedance Zs in the third path between the third electrodes of each semiconductor switching element by a set value. Furthermore, in the power conversion device disclosed in this application, Each phase of a power converter that performs power conversion between direct current and alternating current includes a semiconductor device configured as described above. The control unit controls the power converter to perform power conversion between DC and AC. Invention Effects

[0008] The semiconductor device and power conversion device disclosed in this application can suppress the malfunction of semiconductor switching elements. Attached Figure Description

[0009] Figure 1 This is a simplified structural diagram illustrating the semiconductor device involved in Embodiment 1. Figure 2 This is a simplified structural diagram showing the power conversion device according to Embodiment 1. Figure 3 This is a diagram showing in detail the structure of the semiconductor switching element group included in the semiconductor device according to Embodiment 1. Figure 4 This is a diagram illustrating the resonance between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 5 This is a diagram illustrating the resonance between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 6 This is a diagram illustrating the resonance between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 7 This is a diagram illustrating the resonance between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 8 This is a diagram illustrating the resonance between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 9 This is a diagram illustrating the resonance between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 10 It is a waveform diagram used to illustrate the resonance between semiconductor switching elements in the semiconductor device involved in Embodiment 1. Figure 11 This is a diagram illustrating the amount of gate floating suppression between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 12 This is a waveform diagram used to illustrate the amount of gate floating suppression between semiconductor switching elements in the semiconductor device according to Embodiment 1. Figure 13 This is a simplified structural diagram showing a variation of the semiconductor device according to Embodiment 1. Figure 14 This is a simplified structural diagram of the semiconductor device involved in Embodiment 2. Figure 15 This is a diagram used to illustrate the effects of the semiconductor device involved in Embodiment 2. Figure 16 This is a simplified structural diagram of the semiconductor device involved in Embodiment 3. Figure 17 This is a diagram used to illustrate the effects of the semiconductor device involved in Embodiment 3. Figure 18 This is a simplified structural diagram showing a modified example of the semiconductor device according to Embodiment 3. Figure 19 This is a simplified structural diagram of the semiconductor device involved in Embodiment 4. Figure 20This is a waveform diagram used to illustrate the effect of the semiconductor device involved in Embodiment 4. Figure 21 This is a simplified structural diagram showing the hardware structure of the control unit involved in embodiments 1 to 4. Detailed Implementation

[0010] Hereinafter, preferred embodiments of the semiconductor device and power conversion device disclosed in this application will be described with reference to the accompanying drawings. Identical or equivalent parts are labeled with the same reference numerals in the drawings, and repeated descriptions are omitted.

[0011] Implementation method 1. Figure 1 This is a simplified structural diagram showing the semiconductor device 20 according to Embodiment 1. Figure 2 It shows that it has Figure 1 A simplified structural diagram of the power conversion device 100 according to this embodiment 1 of the semiconductor device 20 shown.

[0012] First, use Figure 2 The power conversion device 100 of this embodiment will be described. The power conversion device 100 includes an inverter circuit 30 as the main circuit section and a control section 50 for controlling the inverter circuit 30. The DC energy storage unit 1, which is a DC circuit, is connected to the input side of the inverter circuit 30, and the motor 5, which is an AC circuit, is connected to the output side. The power conversion device 100 performs power conversion between AC and DC. Here, the voltage of the DC energy storage unit 1 is at least 100V or higher, and the inverter circuit 30 has a structure corresponding to the high voltage and high current described below.

[0013] The inverter circuit 30 is configured to include a group 3 (3U, 3D) of semiconductor switching elements as a first circuit, which has multiple semiconductor switching elements. The detailed structure of the group 3 (3U, 3D) of semiconductor switching elements is described later. The inverter circuit 30 has a three-phase structure, wherein a branch circuit 4, which is obtained by connecting the semiconductor switching element group 3U and the semiconductor switching element group 3D in series between the positive and negative terminals of the DC energy storage section 1, is provided in each of the u, v, and w phases. The semiconductor switching element group 3U of the upper arm and the semiconductor switching element group 3D of the lower arm of the branch circuit 4 are connected to the three-phase AC input and output terminals Vu, Vv, and Vw at their respective phase connection points. The phases of the motor 5 are connected to these AC input and output terminals Vu, Vv, and Vw.

[0014] In the input stage of the inverter circuit 30, a smoothing capacitor 2 for removing voltage ripple and noise from the DC voltage output of the DC energy storage unit 1 is connected in parallel with the DC energy storage unit 1. In addition, the voltage sensor circuit SV1 is connected in parallel with the smoothing capacitor 2. The voltage sensor circuit SV1 detects the voltage across the smoothing capacitor 2, which is the input voltage Vin of the inverter circuit 30, and inputs the detected input voltage Vin to the control unit 50 via the signal line 41.

[0015] Furthermore, current sensor circuits SC1, SC2, and SC3, used to detect the output currents Iu, Iv, and Iw of each phase of the inverter circuit 30, are provided in each phase of the output stage of the inverter circuit 30. The current sensor circuits SC1, SC2, and SC3 detect the output currents Iu, Iv, and Iw flowing between the three-phase input / output terminals Vu, Vv, and Vw and the motor 5, and input the detected output currents Iu, Iv, and Iw to the control unit 50 via signal lines 42u, 42v, and 42w.

[0016] In addition, a rotation angle sensor (not shown) Snsθm is provided for the motor 5 to detect the rotation angle θm of the motor 5. The rotation angle sensor Snsθm inputs the detected rotation angle θm of the motor 5 to the control unit 50 via signal line 43.

[0017] The torque command value Trq* of the motor 5 and the DC voltage command value Vin* of the input voltage Vin to the inverter circuit 30 are input to the control unit 50 by a higher-level control device not shown in the figure. Then, based on the input torque command value Trq*, DC voltage command value Vin*, input voltage Vin obtained from each sensor circuit, output current Iu, Iv, Iw, and rotation angle θm, the control unit 50 controls the switching of each semiconductor switching element group 3 of each phase via control lines 40 (40Uu, 40Du, 40Uv, 40Dv, 40Uw, 40Dw) at separately set dead time intervals.

[0018] Each control line 40 (40Uu, 40Du, 40Uv, 40Dv, 40Uw, 40Dw) is configured for each semiconductor switching element group 3. Specifically, the control unit 50 controls the switching of the semiconductor switching element group 3U of the upper arm of the u phase via the control line 40Uu, and controls the switching of the semiconductor switching element group 3D of the lower arm of the u phase via the control line 40Du. In addition, the control unit 50 controls the switching of the semiconductor switching element group 3U of the upper arm of phase V via control line 40Uv, and controls the switching of the semiconductor switching element group 3D of the lower arm of phase V via control line 40Dv. In addition, the control unit 50 controls the switching of the semiconductor switching element group 3U of the upper arm of phase w via control line 40Uw, and controls the switching of the semiconductor switching element group 3D of the lower arm of phase w via control line 40Dw.

[0019] Thus, under the control of the control unit 50, the inverter circuit 30 converts the DC voltage in the smoothing capacitor 2 into three-phase AC voltage, and supplies the three-phase AC voltage to the motor 5 via the three-phase output terminals Vu, Vv, and Vw.

[0020] In addition, the DC energy storage unit 1, which is a DC circuit, can use energy storage devices such as batteries. When the power conversion device 100 is applied to powertrains such as electric vehicles and hybrid vehicles, the DC energy storage unit 1 is typically composed of rechargeable batteries such as nickel-metal hydride or lithium-ion batteries. Furthermore, while the above description shows an AC circuit as a motor, it could also be a generator. In this case, electricity can be stored from the generator (AC circuit) via the inverter circuit 30 into the DC energy storage unit 1 (DC circuit).

[0021] Next, use Figure 1 The semiconductor switching element group 3 (3U, 3D) which is a parallel circuit will be described. Furthermore, the semiconductor switching element group 3U constituting the upper arm and the semiconductor switching element group 3D constituting the lower arm in the branch circuit 4 of the inverter circuit 30 have the same structure, but when describing the semiconductor switching element groups of the upper arm and the lower arm separately, the reference numerals are changed to describe the semiconductor switching element group 3U and the semiconductor switching element group 3D.

[0022] like Figure 1 As shown, the semiconductor device 20 of this embodiment includes a gate drive circuit 15 and a semiconductor switching element group 3 (3U, 3D). The semiconductor switching element group 3 (3U, 3D) is constructed by connecting multiple power modules 10 (10a, 10b) in parallel. In the semiconductor switching element group 3 (3U, 3D) of this embodiment, the two power modules 10, power module 10a and power module 10b, are connected in parallel. The connection point between the drain terminals of power modules 10a and 10b is designated as the PU connection point, which serves as the first connection point. Furthermore, the connection point between the source terminals of power modules 10a and 10b is designated as the three-phase output terminals Vu, Vv, and Vw, which serve as the second connection point. In addition, Figure 1 The arm of the power module 10a on the left is designated as phase A, and the arm of the power module 10b on the right is designated as phase B.

[0023] In addition, the power modules 10a and 10b are, for example, discrete packaged components that house MOSFETs 11 as semiconductor switching elements. Furthermore, the semiconductor switching element group 3 can be configured to have three or more power modules 10 connected in parallel. The number of power modules 10 connected in parallel corresponds to the power capacity being processed. Furthermore, a power module 10 (10a, 10b) is shown to house a single MOSFET 11, but it may also be configured to house multiple MOSFETs 11 or to house other semiconductor elements such as resistors in addition to MOSFETs 11.

[0024] The drain terminal of the second electrode of MOSFET 11 in power module 10a (phase A) is connected to the drain terminal of the second electrode of MOSFET 11 in power module 10b (phase B). Furthermore, the source terminal of the third electrode of MOSFET 11 in power module 10a (phase A) is connected to the source terminal of the third electrode of MOSFET 11 in power module 10b (phase B). The gate drive circuit 15 is connected to the gate terminal, which serves as the first terminal of each power module 10a and 10b, via gate resistors 10Ra and 10Rb, and controls the voltage between the gate terminal and the source terminal. Therefore, MOSFET11 is controlled to turn on or off between the drain terminal and the source terminal based on the voltage between the gate terminal and the source terminal controlled by the gate drive circuit 15.

[0025] Additionally, the gate drive circuit 15 is configured to be assembled into Figure 2 The control unit 50 shown is therefore located within... Figure 2 The image is not shown in the image. Furthermore, while a MOSFET has been shown as the semiconductor switching element used in the inverter circuit 30 in the above description, the circuit is not limited to this. For example, an IGBT and a diode Di connected in reverse parallel to the IGBT can also be used as the semiconductor switching element.

[0026] Here, the inventors of this application focus on the following situation: in a semiconductor device with multiple power modules connected in parallel, the semiconductor switching element (MOSFET) built into the power modules experiences operational malfunctions such as false arcing. To resolve this malfunction, the inventors, through thorough research, have come to understand that the cause of this malfunction, as explained below, is a resonance phenomenon between the power modules 10 caused by a timing misalignment during switching between the power modules 10.

[0027] The mechanism of operational faults such as false arcing in MOSFETs caused by the structure of multiple power modules 10 connected in parallel will be explained below, followed by an explanation of the countermeasures conceived by the inventors. Figure 3 This is a diagram showing in detail the structure of the semiconductor switching element group 3 (3U, 3D) in the u-phase branch circuit 4 of the inverter circuit 30 of the power conversion device 100 in this embodiment 1.

[0028] Furthermore, as mentioned above, the semiconductor switching element group 3U in the upper arm and the semiconductor switching element group 3D in the lower arm have the same structure. However, in the figures used in the following description, for ease of distinction, the power modules 10a and 10b in the semiconductor switching element group 3U in the upper arm are referred to as power modules 10aU and 10bU, and the power modules 10a and 10b in the semiconductor switching element group 3D in the lower arm are referred to as power modules 10aD and 10bD. Furthermore, the resistance and inductance components of each wiring are represented as follows.

[0029] 10Ra, 10Rb: Gate resistance of each MOSFET11 in power modules 10aU(10aD) and 10bU(10bD). 10Lga, 10Lgb: The inductive components of the gate line that connects the gate terminals of MOSFET 11 in power module 10aU (10aD) and MOSFET 11 in power module 10bU (10bD), serving as the first path. This gate line is connected to the gate drive circuit 15.

[0030] 10La1, 10Lb1: Inductance components of the drain line that connects the drain terminals of MOSFET11 in power module 10aU (10aD) and MOSFET11 in power module 10bU (10bD) as the second path.

[0031] 10Lsa, 10Lsb: Inductive components of the control source line, which serves as the third path, connecting the source terminals of MOSFET 11 in power module 10aU (10aD) and MOSFET 11 in power module 10bU (10bD). This control source line is connected to the gate drive circuit 15.

[0032] 10La2, 10Lb2, ACL_a, ACL_b: Inductance components of the main circuit source lines of power modules 10a and 10b, which are the third path, connecting the source terminals of MOSFET 11 in power module 10aU (10aD) and the source terminals of MOSFET 11 in power module 10bU (10bD). In addition, the main circuit source line of the upper arm is connected to the motor 5 via the AC input / output terminal Vu, and the main circuit source line of the lower arm is connected to the negative side of the smoothing capacitor 2 via the connection point PD, which serves as the second connection point.

[0033] In addition, the gate resistors 10Ra and 10Rb may include wiring resistors. In addition, each inductance component can include not only the inductance of components such as reactors, but also parasitic inductance components.

[0034] And, as Figure 3 As shown, parasitic capacitances exist between the drain and source, drain and gate, and gate and source of each power module 10. Hereinafter, using... Figures 4 to 9 An example of the mechanism by which resonance occurs between the power modules 10 within the semiconductor switching element group 3U of the upper arm when the lower arm semiconductor switching element group 3D is turned on is illustrated. Figures 4-9 This diagram illustrates the resonance generated between the power modules 10 in phase A and phase B of the semiconductor device 20 according to Embodiment 1.

[0035] Figure 4 The action pattern shown is (pattern a). Consider a state where both the upper and lower arms of the MOSFET 11 in the upper arm semiconductor switching element group 3U and the lower arm semiconductor switching element group 3D are turned off, and current flows into the motor 5 from the output stage of the inverter circuit 30. At this time, the current flowing in from the motor 5 side flows from the source terminal side to the drain terminal side through the internal diode of the MOSFET 11 in the upper arm semiconductor switching element group 3U.

[0036] Figure 5 The action pattern shown is (pattern b). MOSFET11 in the semiconductor switching element group 3D of the lower arm is turned on. Here, it is assumed that in the semiconductor switching element group 3D of the lower arm, due to the characteristic difference between power modules 10aD and 10bD, and the inductance deviation, the MOSFET 11 in the power module 10bD of phase B turns on with a delay relative to the power module 10aD of phase A. Therefore, the drain current of the MOSFET 11 in the power module 10aD of phase A is larger than the drain current of the MOSFET 11 in the power module 10bD of phase B. On the other hand, in the semiconductor switching element group 3U of the upper arm, the current flowing through the internal diode of the MOSFET 11 in the power module 10aU of phase A is smaller than the current flowing through the internal diode of the MOSFET 11 in the power module 10bU of phase B. Therefore, in the upper arm, the current flowing through the power module 10aU of phase A is initially 0, and recovery occurs.

[0037] Figure 6 The action pattern shown is (pattern c). In the semiconductor switching element group 3U of the upper arm, the diode in the power module 10aU of phase A recovers, and therefore, a recovery current flows through the phase A side. At this time, the diode in the power module 10bU of phase B does not recover, and the internal diode in the power module 10bU of phase B is in a conducting state.

[0038] Figure 7 The action pattern shown is (pattern d). After the diodes in the power module 10aU of phase A of the semiconductor switching element group 3U in the upper arm recover, the parasitic capacitance between the drain and source of the MOSFET 11 in the power module 10aU of phase A is charged, and the drain-source voltage Vds rises. On the other hand, the internal diodes in the power module 10bU of phase B of the semiconductor switching element group 3U in the upper arm are in the on state, so the drain-source voltage Vds is approximately 0V. At this time, a potential difference is generated between the power module 10aU of phase A and the power module 10bU of phase B. That is, the drain-source voltage Vds of the power module 10aU of phase A becomes greater than the drain-source voltage Vds of the power module 10bU of phase B.

[0039] Figure 8 The action pattern shown is (pattern e). In the semiconductor switching element group 3U in the upper arm, the drain-source voltage Vds of MOSFET11 in the power module 10aU of phase A increases, generating a potential difference with phase B. Therefore, the currents I1 and I2, which are resonant currents, flow from phase A through phase B. Current I1 flows from the drain terminal of MOSFET 11 in power module 10aU of phase A, through MOSFET 11 in power module 10bU of phase B, and through the common part of the gate line of each power module 10aU and 10bU. Current I2 flows from the drain terminal of MOSFET 11 in power module 10aU of phase A through MOSFET 11 in power module 10bU of phase B, and flows through the main circuit source line (through the path of AC input / output terminal Vu) and the control source line (through the path connected to the gate drive circuit 15). In addition, for the sake of simplicity, the on-current of MOSFET11 flowing through the semiconductor switching element group 3D in the lower arm is omitted from the illustration and explanation.

[0040] Figure 9 The action pattern shown is (pattern f). The recovery of the diode in the power module 10aU of phase A of the semiconductor switching element group 3U in the upper arm is completed, and the parasitic capacitance between the drain and source of the MOSFET 11 of the power module 10bU of phase B becomes visible. The current that has flowed before this point has charged the capacitor. Then, the drain-source voltage Vds of MOSFET11 in the power module 10bU of phase B increases, creating a potential difference with phase A, and currents I3 and I4 flow from phase B through phase A. Current I3 flows from the drain terminal of MOSFET 11 in power module 10bU of phase B through MOSFET 11 in power module 10aU of phase A, and flows through the common part of the gate line of each power module 10aU and 10bU. Current I4 flows from the drain terminal of MOSFET 11 in power module 10bU of phase B through MOSFET 11 in power module 10aU of phase A, and through the source line of the main circuit (via the path of AC input / output terminal Vu).

[0041] Subsequently, resonance occurs between the parasitic capacitances of power module 10aU in phase A and power module 10bU in phase B. Right now, Figure 9 In the power module 10aU of phase A, the drain-source capacitance of MOSFET 11 becomes discharge-to-charge, while in the power module 10bU of phase B, the drain-source capacitance of MOSFET 11 becomes charge-to-discharge. Furthermore, in the power module 10bU of phase B, the gate-source capacitance of MOSFET 11 becomes discharge-to-charge, while in the power module 10aU of phase A, the gate-source capacitance of MOSFET 11 becomes charge-to-discharge.

[0042] Furthermore, resonance occurs not only between the parasitic capacitances of phase A and phase B within the semiconductor switching element group 3U in the upper arm, but also between the semiconductor switching element group 3U in the upper arm and the smoothing capacitor 2. In addition, for the sake of simplicity, the conduction current flowing through the semiconductor switching element group 3D in the lower arm is also omitted from the illustration and explanation.

[0043] As described above, if the switching timing of MOSFET 11 in the parallel-connected power modules 10a and 10b is offset, a potential difference will be generated between the power modules 10a and 10b, and a resonance phenomenon will be generated due to the parasitic capacitance of MOSFET 11 in the power modules 10a and 10b and the inductive component between the power modules 10a and 10b.

[0044] The inventors of this application have discovered that, due to the resonant current, the gate voltage of MOSFET11 rises, thereby causing false arcing (false turn-on) in MOSFET11. This is a problem that becomes apparent when switching is performed at high di / dt (high-speed switching) specifically to reduce losses. The following uses a waveform diagram representing the voltage in MOSFET11 to illustrate the state that causes false arcing (false turn-on) of MOSFET11.

[0045] Figure 10 It is used to explain the above. Figure 8 The waveforms of the voltages in each parasitic capacitance of MOSFET11 in mode e are shown below. VgsUa: Gate-source voltage of MOSFET11 within the power module 10aU in the upper arm. VgsUb: Gate-source voltage of MOSFET11 within the power module 10bU in the upper arm. VgsDa: Gate-source voltage of MOSFET11 within the power module 10aD of the lower arm. VgsDb: Gate-source voltage of MOSFET11 within the power module 10bD of the lower arm.

[0046] VdsUa: Drain-source voltage of MOSFET11 within the power module 10aU in the upper arm. VdsUb: Drain-source voltage of MOSFET11 within the power module 10bU in the upper arm. VdsDa: Drain-source voltage of MOSFET11 within the power module 10aD in the lower arm. VdsDb: Drain-source voltage of MOSFET11 within the power module 10bD of the lower arm.

[0047] It can be seen that at t = 1.25 μs, the gate-source voltage VgsUa of MOSFET 11 in the upper arm of power module 10aU of phase A, which first recovers, increases. At this time, the gate-source voltage VgsUa of power module 10aU of phase A rises, causing gate floating. It can be seen that when the gate-source voltage VgsUa exceeds the threshold, false turn-on occurs.

[0048] The following describes countermeasures for the aforementioned problems in the semiconductor device 20 of Embodiment 1. exist Figures 4-9 In each operating mode described herein, in order to suppress gate floating of MOSFET11, suppress Figure 8 The current I1 generated in the gate line under the operating mode shown (mode e) is important. here, Figure 9In the operating mode shown (mode f), after the potential difference between phase A and phase B is generated, resonance occurs between parasitic capacitances (capacitors) due to inertia. Therefore, the cause is... Figure 8 The resonant current during the operating mode (mode e) shown.

[0049] In order to suppress Figure 8 The current I1 generated in the operating mode (mode e) that charges the gate capacitance of MOSFET 11 is configured in the semiconductor device 20 of this embodiment 1 to ensure a first condition, which makes the impedance Zg of the gate line of the resonant path between power modules 10a and 10b, which is the first path, greater than the impedance Zs of the source line (control source line and main circuit source line) of the third path by a preset value Sv or more.

[0050] Here, the gate line impedance Zg is represented by 10Ra+10Lga+10Rb+10Lgb. Furthermore, if the impedance of the main circuit source line is set to 10La2+10Lb2+ACL_a+ACL_b, and the impedance of the control source line is set to 10Lsa+10Lsb, then the impedance Zs of the source line is represented by 10Lsa+10Lsb / / 10La2+10Lb2+ACL_a+ACL_b.

[0051] That is, in Figure 8 In the operating mode (mode e), the amount of current shunted to the gate line side or source line side after the parasitic capacitance between the drain and source of MOSFET 11 in power module 10aU of phase A is determined by the impedance ratio after passing through power module 10bU of phase B. Here, it is assumed that the input capacitance Ciss of MOSFET 11 in power module 10bU is sufficiently large, and the impedance 1 / jωC is so small as to be negligible. Therefore, as described above, by configuring a first condition to ensure that the impedance Zg of the gate line is greater than the impedance Zs of the source line by a set value Sv or more, the amount of current flowing through the gate line side can be suppressed, and the amount of gate levitation caused by the charging of the gate capacitance can be reduced.

[0052] Figure 11 This diagram illustrates the relationship between the gate float suppression amount and the source line impedance Zs (Zg / Zs) when the gate line impedance Zg is increased under certain set conditions. The frequency at this point is defined as the resonant frequency. In Z = R + jωL, ω is the resonant angular frequency.

[0053] Depend on Figure 11 It can be seen that by setting the impedance Zg of the gate line to be more than 10 times greater than the impedance Zs of the source line, the gate floating effect can be suppressed. Therefore, in the power conversion device according to Embodiment 1, the impedance Zg of the gate line is more than 10 times greater than the impedance Zs of the source line. That is, the setting value Sv in the first condition above is represented by the multiple (Zg / Zs) of the impedance Zg in the gate line relative to the impedance Zs in the source line, and this multiple is set to 10.

[0054] Figure 12 This is a waveform diagram used to illustrate the suppression amount of gate floating between semiconductor switching elements in the semiconductor device 20 according to Embodiment 1. Each waveform is shown below. VgsUa: Gate-source voltage of MOSFET11 within the power module 10aU in the upper arm. VgsDa: Gate-source voltage of MOSFET11 within the power module 10aD of the lower arm. In addition, multiple waveforms are shown for VgsUa and VgsDa, because more than three power modules 10 are connected in parallel for the experiment. like Figure 12 As shown, the gate-source voltage of MOSFET11 in the power module 10aU of the upper arm is suppressed from the peak value of 12V to 10V, which means a suppression amount of 2V ΔV is obtained.

[0055] Furthermore, in the semiconductor device 20 according to this embodiment, based on Figure 8 The path of current I1 shown in the operating mode (mode e), namely the impedance at the resonant frequency f0 in the series resonant circuit including the inductance components 10La1, 10Lb1 in the drain line between the drain terminals of MOSFET 11 in power modules 10aU and 10bU of phases A and B, the inductance components 10Lga, 10Lgb in the gate line, the resistance components of the gate resistors 10Ra, 10Rb, and the capacitance component of MOSFET 11, is used to ensure the above-mentioned first condition.

[0056] That is, the impedance of the gate line and the impedance of the source line are adjusted so that when the resonant current, I1, flows, the first condition mentioned above can be ensured even at the resonant frequency f0 where the impedance is at its minimum. Thus, the first condition mentioned above can be ensured even under the condition of the lowest impedance. Therefore, regardless of the frequency of the resonant current, gate floating of MOSFET11 can always be suppressed, and operational failures can be suppressed. Furthermore, in the resonant path through which current I1 flows, the MOSFET 11 of the power module 10bU in phase B is turned on before the recovery begins. Therefore, the capacitance component of the MOSFET 11 constituting the above resonant circuit is only the capacitance of the MOSFET 11 of the power module 10bU in phase B.

[0057] In this embodiment, the impedance adjustment of the gate line and source line used to ensure the first condition described above can be performed, for example, by adjusting the wiring resistance caused by adjusting the length of the substrate pattern. Alternatively, it can be performed, for example, by setting components such as coils. Here, when the impedance of the gate line is increased to ensure the first condition mentioned above, for example, if the resistance values ​​of the gate resistors 10Ra and 10Rb are increased, the switching losses worsen and the chip size becomes larger. Therefore, as a unit to increase the impedance of the gate line, it can be configured to have a ferrite bead in the source line that has high impedance at the resonant frequency of the series resonant circuit, i.e., the path of current I1. By adjusting the impedance relationship between the gate line and the source line, the first condition is ensured in the impedance at the resonant frequency of the series resonant circuit containing the ferrite beads, thereby reliably ensuring the first condition and miniaturizing the device, regardless of the frequency of the resonant current. Furthermore, the above description primarily focused on the timing offset between phases A and B of the upper arm's semiconductor switching element group 3U. However, even if a timing offset occurs in the lower arm's semiconductor switching element group 3D, the same effect can be achieved by ensuring the first condition described above in the semiconductor device constituting the lower arm.

[0058] Hereinafter, as another variation for reliably ensuring the first condition, a semiconductor device 20ex, different from the semiconductor device 20 described above, will be described. Figure 13 This is a simplified structural diagram showing the semiconductor device 20ex according to Embodiment 1. like Figure 13 As shown, an LC series circuit having a capacitor 10C1 as the first capacitance component and an inductor 10L1 as the first inductance component is provided in parallel with the source line, and the source terminals of the MOSFET 11 between phase A and phase B are connected to each other via this LC series circuit. Here, inductor 10L1 can be a parasitic inductance of the wiring pattern on the substrate, or it can be a component such as a reactor.

[0059] Here, the resonant frequency (Z→0) of the LC series circuit is set as... Figure 8 The resonant frequency of the current I1 flowing between power modules 10aU and 10bU as described herein, thus, in this operating mode (mode e), as... Figure 13 As shown by the solid arrow, the resonant current flows through the LC series circuit. That is, at the set frequency, the impedance of the source line is reduced. Therefore, by adjusting capacitor 10C1 and inductor 10L1, the impedance in the LC series circuit is lower than the impedance of the source line at the resonant frequency of the series resonant circuit, thus ensuring the first condition mentioned above.

[0060] The semiconductor device of this embodiment configured as described above includes: A first circuit, wherein a semiconductor switching element is connected in parallel, the semiconductor switching element having a first electrode, a second electrode, and a third electrode, wherein the voltage between the first electrode and the third electrode is used to control the connection between the second electrode and the third electrode to be either on or off; and A control unit, connected to the first electrode of each of the semiconductor switching elements, controls the voltage between the first electrode and the third electrode in this semiconductor device. The condition is configured to ensure that the impedance Zg in the first path between the first electrodes of each semiconductor switching element is greater than the impedance Zs in the third path between the third electrodes of each semiconductor switching element by a set value.

[0061] Thus, the semiconductor device is configured to include: a first circuit in which a plurality of semiconductor switching elements are connected in parallel; and a control unit connected to the first terminal of the semiconductor switching elements in the first circuit and serving as a gate drive circuit, wherein the gate drive circuit is used to control each semiconductor switching element. In this semiconductor device, a first condition is configured to ensure that the impedance Zg in the first path, i.e., the gate line, between the first electrodes of each semiconductor switching element is greater than the impedance Zs in the source line, i.e., the third path, between the third electrodes of each semiconductor switching element by a set value.

[0062] Therefore, even if resonance occurs between the parallel-connected semiconductor switching elements due to timing deviations in the recovery of the individual semiconductor switches, the amount of resonant current flowing back to the gate line can be reduced. Thus, gate floating of the semiconductor switching elements can be suppressed, and false arcing can be prevented. Here, for example, if the configuration is to suppress the imbalance of the gate current and only reduce the offset of the switching timing among the parallel-connected semiconductor switching elements, then even if the switching timing is consistent, the timing of the recovery in each phase will be different if there is an impedance deviation between the semiconductor switching elements. In the semiconductor device of this embodiment, as described above, even when the timing of the recovery is different, the resonant current caused by the recovery can be suppressed from winding back to the gate line. Therefore, malfunction of the semiconductor switching element can be effectively suppressed.

[0063] In addition, for example, to match the timing of recovery, semiconductor switching elements can be selected to suppress element deviation of semiconductor switching elements, but in this case, the yield rate deteriorates and the cost increases. In the semiconductor device of this embodiment, the selection of components such as semiconductor switching elements for matching such recovery timing can be omitted, thereby reducing costs.

[0064] Furthermore, for example, if the semiconductor switching element is configured to reduce its switching speed to prevent resonance, losses will worsen. In this case, to ensure that the heat generated by the design, which allows for losses, is kept within permissible limits, the semiconductor switching element must be configured for low-speed switching rather than high-speed switching. This also necessitates the use of larger, more expensive, and higher-performance semiconductor switching elements, thus increasing costs. In the semiconductor device of this embodiment, even when a large resonant current is generated during high-speed switching, the resonant current can be suppressed from winding back to the gate line. Therefore, a high-efficiency and compact semiconductor device that suppresses the operation failure of semiconductor switching elements can be provided.

[0065] Furthermore, in the semiconductor device of this embodiment configured as described above, The first condition is ensured based on the impedance at the resonant frequency of a series resonant circuit, which includes the inductive component in the second path connecting the second electrodes of each of the semiconductor switching elements, the inductive and resistive components in the first path, and the capacitive component of the semiconductor switching elements.

[0066] Therefore, the first condition is ensured based on the impedance at the resonant frequency of the path through which the resonant current flows, i.e., the series resonant circuit, which includes the inductive component in the second path connecting the second electrodes of each semiconductor switching element, the inductive and resistive components in the first path, and the capacitive component of the semiconductor switching element. Therefore, impedance is adjusted so that the first condition mentioned above can be ensured even when the impedance is at its lowest. Thus, regardless of the frequency of the resonant current, gate floating of the semiconductor switching element can be stably suppressed, and operational failures can be suppressed.

[0067] Furthermore, in the semiconductor device of this embodiment configured as described above, The set value is represented by the multiple of the impedance Zg in the first path to the impedance Zs in the third path, i.e., Zg / Zs, which is set to 10.

[0068] The inventors, through thorough research, determined that by setting the impedance of the gate line (first path) to more than 10 times that of the source line (third path), the current winding back to the gate line could be effectively suppressed. This further effectively suppressed gate floating of semiconductor switching elements, aiming to suppress operational malfunctions.

[0069] Furthermore, in the semiconductor device of this embodiment configured as described above, The first path includes an inductive element that exhibits a frequency characteristic where impedance increases at the resonant frequency of the series resonant circuit. The first condition is ensured based on the impedance at the resonant frequency of the series resonant circuit containing the inductive element.

[0070] Furthermore, in the semiconductor device of this embodiment configured as described above, The inductive element is a ferrite bead inductive element.

[0071] Therefore, the first path of the gate line includes an inductive element such as a ferrite bead that has a frequency characteristic of increasing impedance at the resonant frequency, and the impedance of the semiconductor device is adjusted to ensure the first condition based on the impedance at the resonant frequency. Thus, for example, it is not necessary to increase the resistance value of the gate resistor to ensure the first condition. Therefore, a small semiconductor device can be provided without deteriorating switching losses.

[0072] Furthermore, in the semiconductor device of this embodiment configured as described above, An LC series circuit having a first capacitive component and a first inductive component is connected in parallel with the third path. The first capacitor component and the first inductor component are adjusted so that the impedance in the LC series circuit is lower than the impedance in the third path at the resonant frequency of the series resonant circuit, thereby ensuring the first condition.

[0073] Therefore, an LC series circuit consisting of the first capacitive component and the first inductive component is connected in parallel to the source line, i.e., the third path. Furthermore, the first capacitive component and the first inductive component are adjusted so that, at the resonant frequency of the series resonant circuit, the impedance in the LC series circuit is lower than the impedance in the third path of the source line. This further reduces the impedance at the source terminal of the semiconductor switching element at the resonant frequency, thus further suppressing gate floating of the semiconductor switching element stably regardless of the frequency of the resonant current, and suppressing operational malfunctions.

[0074] Furthermore, in the power conversion device of this embodiment configured as described above, Each phase of a power converter that performs power conversion between direct current and alternating current includes a semiconductor device configured as described above. The control unit controls the power converter to perform power conversion between DC and AC.

[0075] By adopting this structure, malfunctions of semiconductor switching elements are suppressed, enabling the provision of power conversion devices with small and efficient inverters and other power converters.

[0076] Implementation method 2. Hereinafter, Embodiment 2 of this application will be described using the accompanying drawings, focusing on the differences from Embodiment 1 described above. The same reference numerals will be used for the parts that are the same as in Embodiment 1 described above, and descriptions will be omitted. Figure 14 This is a simplified structural diagram of the semiconductor device 220 according to Embodiment 2. Figure 15 This is a diagram used to illustrate the effects of the semiconductor device 220 according to Embodiment 2. In addition, in this embodiment, for the sake of simplicity, the description will focus on the gate portion of the semiconductor switching element group 3U.

[0077] The semiconductor device 220 in this embodiment is configured such that gate drive circuits 15 for controlling MOSFETs 11 are independently provided in each power module 10aU of phase A and power module 10bU of phase B. That is, the MOSFETs 11 in the power module 10aU of phase A and the MOSFETs 11 in the power module 10bU of phase B are controlled by different gate drive circuits 15.

[0078] Here, each gate drive circuit 15 is provided with a gate drive power supply 15P for driving the power supply section, and the voltage driving each gate drive circuit 15 is generated by each gate drive power supply 15P. By employing this structure, the impedance between each gate drive power supply 15P is ensured to be sufficiently large. Therefore, the impedance between the gate terminals of MOSFET11 in phase A and MOSFET11 in phase B is ensured to be relatively large.

[0079] That is, by simply configuring the gate drivers 15 to be independently set and separated, it is possible to generate a path that resonates along the gate drive power supplies 15P. However, in the semiconductor device 220 of this embodiment, in order to ensure the first condition, the impedance between each gate drive power supply 15P is increased, thereby adjusting the impedance in the gate line. Thus, as Figure 15 As shown, the resonant path of the resonant current that wraps back to the gate line can be eliminated, that is, the resonant path can be separated, and the gate floating of MOSFET11 can be suppressed.

[0080] Furthermore, although not illustrated, in a semiconductor device employing a structure with only one gate drive power supply 15P, configured to drive each gate drive circuit 15 by this single gate drive power supply, it is sufficient to configure the power supply path from the single gate drive power supply 15P to each gate drive circuit 15 to be a high impedance. In this case, methods such as making the power supply path a long wiring path can be cited. Therefore, the impedance between the gate terminals of MOSFET11 in phase A and MOSFET11 in phase B can be increased, which can ensure the first condition mentioned above.

[0081] In the semiconductor device of this embodiment configured as described above, The control unit is independently provided for each of the semiconductor switching elements to ensure the first condition.

[0082] Therefore, by configuring each semiconductor switching element to be independently equipped with a gate drive circuit as a control unit, the impedance between the gate terminals of the parallel-connected semiconductor switching elements can be increased, and the first condition mentioned above can be ensured. Thus, the same effect as in Embodiment 1 is achieved: even if resonance occurs between parallel-connected semiconductor switching elements, the amount of resonant current flowing back to the gate line can be reduced. Therefore, gate floating of semiconductor switching elements can be suppressed, and false arcing can be suppressed.

[0083] Furthermore, in the semiconductor device of this embodiment configured as described above, Each of the control units is independently provided with a power supply unit that supplies power to each control unit. Adjust the impedance between each of the power supply units to ensure the first condition.

[0084] Therefore, a gate drive power supply is independently provided for each gate drive circuit. Furthermore, by adjusting the impedance between the gate drive power supplies to increase the impedance between the gate terminals of the parallel-connected semiconductor switching elements, the impedance between the gate terminals can be increased, and the first condition mentioned above can be reliably ensured. This can further reduce the amount of resonant current that flows back to the gate line, and more effectively suppress gate floating of semiconductor switching elements.

[0085] Furthermore, in the semiconductor device of this embodiment configured as described above, The impedance of the power path that supplies power from the power supply unit to each of the control units via the power path is adjusted to ensure the first condition.

[0086] For example, even when configured with only one gate drive power supply, by adjusting the impedance of the power path supplying power to the gate drive circuit, the impedance between the gate terminals of the parallel-connected semiconductor switching elements can be increased, ensuring the first condition. This reduces the amount of resonant current flowing back to the gate line, effectively suppressing gate floating of the semiconductor switching elements.

[0087] Implementation method 3. Hereinafter, Embodiment 3 of this application will be described using the accompanying drawings, focusing on the differences from Embodiment 1 described above. The same reference numerals will be used for the parts that are the same as in Embodiment 1 described above, and descriptions will be omitted. Figure 16 This is a simplified structural diagram of the semiconductor device 320 according to Embodiment 3. Figure 17 This is a diagram used to illustrate the effects of the semiconductor device 320 according to Embodiment 3. Similar to Embodiment 2 described above, the solution to the problem of this application in the semiconductor device 320 of Embodiment 3 is to separate the resonant path.

[0088] like Figure 16 As shown, a switching element 312 is provided as an on / off device for opening and closing the gate line in the first path of the gate terminal of the MOSFET 11 in the power module 10aU of phase A and the gate terminal of the MOSFET 11 in the power module 10bU of phase B. When MOSFET 11 is in the ON state, the gate drive circuit 15 controls these switching elements 312 to the OFF state, and controls the switching device to the OFF state when MOSFET 11 is in the OFF state. That is, in the state where the resonant current flows, Figure 8 When MOSFET11 is in the off state in the operating mode (mode e), the impedance between the gate terminals of the parallel-connected MOSFET11 is increased, resulting in infinite impedance, to ensure the first condition mentioned above. Thus, as... Figure 17 As shown, the resonant path of the resonant current can be eliminated, and gate floating can be suppressed.

[0089] In addition, the switching elements 312 shown in the figure are P-channel MOSFETs, but are not limited to them, as long as they have switching functions.

[0090] The following is another variation for reliably ensuring the first condition, regarding... Figure 18 Different semiconductor devices 320ex shown above will be described. When using a MOSFET as the switching device located on the gate line, a parasitic diode exists. Therefore, even when the MOSFET is off, if the potential of the gate drive circuit 15 is lower than the gate voltage of the MOSFET 11, the parasitic diode of the MOSFET, acting as the switching device, will conduct. Therefore, to completely isolate the resonant path, a structure is used where MOSFET 312-1 and MOSFET 312-2 are connected in reverse series as the switching device. This allows the AC resonant current to be interrupted and reliably ensures the first condition.

[0091] Furthermore, in the semiconductor device of this embodiment configured as described above, The first path includes an opening and closing device. When the semiconductor switching element is in the on state, the switching device is controlled to be in the closed state, and when the semiconductor switching element is in the off state, the switching device is controlled to be in the open state, thereby ensuring the first condition.

[0092] Therefore, by configuring the switching device to switch on and off according to the semiconductor switching elements in the power module, the impedance between the gate terminals of the MOSFETs in the parallel-connected power modules can be increased, that is, the impedance can be made infinite, thereby reliably ensuring the first condition mentioned above. Thus, the same effect as in Embodiment 1 is achieved: even if resonance occurs between parallel-connected semiconductor switching elements, the amount of resonant current flowing back to the gate line can be reduced. Therefore, gate floating of semiconductor switching elements can be suppressed, and false arcing can be suppressed.

[0093] Implementation method 4. Hereinafter, Embodiment 4 of this application will be described using the accompanying drawings, focusing on the differences from Embodiment 1 described above. The same reference numerals will be used for the parts that are the same as in Embodiment 1 described above, and descriptions will be omitted. As described above, the gate floating mechanism of the semiconductor switching element, which is the problem of this application, arises from the following situation: in a circuit with a structure of multiple power modules connected in parallel, the recovery timing after switching is offset, resulting in a potential difference between the drain and source of each power module. That is, current flows from the power module with higher voltage to the power module with lower voltage.

[0094] Furthermore, as mentioned above, even with consistent switching timing, if the impedances of the drain and source terminals of each power module are different, the current during conduction will also be different. That is, compared to... Figure 5 The state shown in the action pattern (pattern b) is the same.

[0095] Figure 19This is a simplified structural diagram of the semiconductor device 420 according to Embodiment 4. Figure 20 This is a diagram used to illustrate the effects of the semiconductor device 420 according to Embodiment 4. In the semiconductor device 420 according to Embodiment 4, in order to suppress resonance while ensuring consistent switching timing, such as Figure 19 As shown, the inductance components L410LU-A and L410LU-B of phase A and phase B of the upper arm of the main circuit line of each power module 10 of the semiconductor switching element group 3D are balanced. In addition, the inductive components L410LD-A and L410LD-B of phase A in the lower arm are balanced.

[0096] That is, in the semiconductor switching element group 3U of the upper arm, in the path from the smoothing capacitor 2 to the main circuit source line of each power module 10aU, 10bU, the inductance components L410LU-A and L410LU-B in each of the fourth paths from the connection point PU through each phase power module 10aU, 10bU to the three-phase output terminals Vu, Vv, Vw are equal. Furthermore, in the semiconductor switching element group 3 of the lower arm, the inductance components L410LD-A and L410LD-B in each of the fourth paths from the drain terminal side of each power module 10aD and 10bD to the smoothing capacitor 2 are equal. This balances the conduction current during switching and matches the recovery timing. Consequently, it suppresses potential differences between power modules and suppresses resonant current.

[0097] like Figure 20 As shown, the inventors, through analysis of the relationship between the switching speed of the power module and the inductor deviation, confirmed that under the condition of a switching speed (di / dt) of 10 kA / μs for the power module, by setting the inductor deviation to less than 3% (less than 1 nH relative to approximately 33 nH), the current deviation during conduction essentially disappears. Therefore, the potential difference between the power modules can be suppressed, and the resonant current can be suppressed.

[0098] In the semiconductor device of this embodiment configured as described above, The connection point between the second electrodes of each semiconductor switching element on the second path is designated as the first connection point, and the connection point between the third electrodes of each semiconductor switching element on the third path is designated as the second connection point. The impedances of each fourth path from the first connection point through each of the semiconductor switching elements to the second connection point are equal.

[0099] Thus, the impedances in the paths from the first connection point PU on the drain line of the second path connecting the drain terminals of the parallel semiconductor switching elements to each other, and the second connection point on the source line of the third path connecting the source terminals of the main circuit to each other, via the semiconductor switching elements of phase A and phase B, are respectively equal. By using such a structure in conjunction with the structures shown in Embodiments 1 to 3 above, current deviation during conduction can be suppressed, and gate floating of semiconductor switching elements can be suppressed.

[0100] The larger the potential difference, the more likely the resonance phenomenon caused by the potential difference between power modules, which is a problem of this application as described in Embodiments 1 to 3, will occur. Even if the timing deviation of the switching and recovery can be suppressed, if the switching speed (dV / dt) is fast, even a slight timing deviation may generate a potential difference. Therefore, in the semiconductor device of this embodiment, the faster the switching speed (which easily generates a potential difference), the more effective the element is. That is, the more the semiconductor switching element is a wide-bandgap semiconductor SiC element, the easier it is for resonance to occur. That is, the semiconductor switching elements in each embodiment use wide-bandgap semiconductors formed from silicon carbide, gallium nitride, or diamond.

[0101] Furthermore, while examples of using an inverter circuit as a power converter are described in the power conversion devices of each embodiment, the invention is not limited to this and can also use a converter circuit. The same problem arises with a power converter having multiple semiconductor switching elements connected in parallel, which can be solved using the countermeasures described above. Furthermore, the number of semiconductor switching element chips inside the power module is not shown in the semiconductor devices involved in each embodiment, but the same problem will occur regardless of whether there is one or more chips in the package, and the countermeasures can achieve the same effect. Furthermore, in the semiconductor devices involved in each embodiment, a structure in which the number of semiconductor switching elements connected in parallel is set to 2 has been described, but it is not limited to this. As long as there are multiple elements connected in parallel, it can also be 3 elements connected in parallel.

[0102] Figure 21 This is a simplified structural diagram showing the hardware structure of the control unit involved in embodiments 1 to 4. In addition, such as Figure 21As shown in the example of hardware, the control unit 50 consists of a processor 51 and a storage device 52. The storage device 52 includes volatile storage devices such as random access memory (not shown) and non-volatile auxiliary storage devices such as flash memory. Alternatively, an auxiliary storage device such as a hard disk can be used instead of flash memory. The processor 51 executes the program input from the storage device 52. In this case, the program is input from the auxiliary storage device to the processor 51 via a volatile storage device. Furthermore, the processor 51 can output data such as calculation results to the volatile storage device of the storage device 52, or it can save data to the auxiliary storage device via the volatile storage device.

[0103] Although this application describes various exemplary implementation methods and embodiments, the various features, methods and functions described in one or more implementation methods are not limited to the application of a particular implementation method, and can be applied to the implementation method individually or in various combinations. Therefore, numerous variations not illustrated are conceivable within the scope of the technology disclosed in this application. For example, this could include variations, additions, or omissions of at least one constituent element, or the extraction of at least one constituent element and its combination with constituent elements of other embodiments. Label Explanation

[0104] 11MOSFET (Metal-Oxide-Semiconductor Switching Device) 3. 3U, 3D semiconductor switching element group (Circuit 1) 15 Gate drive circuit (control unit) 15P Gate Drive Power Supply (Power Supply Section) 20, 20ex, 220, 320, 320ex, 420 semiconductor devices 50 Control Department 312, 312-1, 312-2 Switching Elements (Opening and Closing Devices) 100 power conversion device.

Claims

1. A semiconductor device, comprising: A first circuit, wherein a semiconductor switching element is connected in parallel, the semiconductor switching element having a first electrode, a second electrode, and a third electrode, wherein the voltage between the first electrode and the third electrode is used to control the connection between the second electrode and the third electrode to be either on or off; and A control unit, connected to the first electrode of each of the semiconductor switching elements, controls the voltage between the first electrode and the third electrode. The semiconductor device is characterized in that... The configuration is designed to ensure a first condition, in which the impedance Zg in the first path between the first electrodes of each of the semiconductor switching elements is greater than the impedance Zs in the third path connecting the third electrodes of each of the semiconductor switching elements, and the difference between the impedance Zg and the impedance Zs is above a set value. The first condition is ensured based on the impedance at the resonant frequency of a series resonant circuit, which includes the inductive component in the second path connecting the second electrodes of each of the semiconductor switching elements, the inductive and resistive components in the first path, and the capacitive component of the semiconductor switching elements. An LC series circuit having a first capacitive component and a first inductive component is connected in parallel with the third path. The first capacitor component and the first inductor component are adjusted so that the impedance in the LC series circuit is lower than the impedance in the third path at the resonant frequency of the series resonant circuit, thereby ensuring the first condition.

2. The semiconductor device as claimed in claim 1, characterized in that, The control unit is independently provided for each of the semiconductor switching elements to ensure the first condition.

3. A semiconductor device, comprising: A first circuit, wherein a semiconductor switching element is connected in parallel, the semiconductor switching element having a first electrode, a second electrode, and a third electrode, wherein the voltage between the first electrode and the third electrode is used to control the connection between the second electrode and the third electrode to be either on or off; and A control unit, connected to the first electrode of each of the semiconductor switching elements, controls the voltage between the first electrode and the third electrode. The semiconductor device is characterized in that... The configuration is designed to ensure a first condition, in which the impedance Zg in the first path between the first electrodes of each of the semiconductor switching elements is greater than the impedance Zs in the third path connecting the third electrodes of each of the semiconductor switching elements, and the difference between the impedance Zg and the impedance Zs is above a set value. The control unit is independently provided for each of the semiconductor switching elements, and the impedance of the power path that supplies power from the power supply unit to each control unit via the power path is adjusted to ensure the first condition.

4. A semiconductor device, comprising: A first circuit, wherein a semiconductor switching element is connected in parallel, the semiconductor switching element having a first electrode, a second electrode, and a third electrode, wherein the voltage between the first electrode and the third electrode is used to control the connection between the second electrode and the third electrode to be either on or off; and A control unit, connected to the first electrode of each of the semiconductor switching elements, controls the voltage between the first electrode and the third electrode. The semiconductor device is characterized in that... The configuration is designed to ensure a first condition, in which the impedance Zg in the first path between the first electrodes of each of the semiconductor switching elements is greater than the impedance Zs in the third path connecting the third electrodes of each of the semiconductor switching elements, and the difference between the impedance Zg and the impedance Zs is above a set value. The control unit is independently provided for each of the semiconductor switching elements, and a power supply unit is independently provided for each control unit to supply power to each control unit. The impedance between the power supply units is adjusted to ensure the first condition.

5. The semiconductor device as claimed in claim 3 or 4, characterized in that, The first condition is ensured based on the impedance at the resonant frequency of a series resonant circuit, which includes the inductive component in the second path connecting the second electrodes of each of the semiconductor switching elements, the inductive and resistive components in the first path, and the capacitive component of the semiconductor switching elements.

6. The semiconductor device as claimed in claim 5, characterized in that, An LC series circuit having a first capacitive component and a first inductive component is connected in parallel with the third path. The first capacitor component and the first inductor component are adjusted so that the impedance in the LC series circuit is lower than the impedance in the third path at the resonant frequency of the series resonant circuit, thereby ensuring the first condition.

7. The semiconductor device as claimed in any one of claims 1, 2, and 6, characterized in that, The first path includes an inductive element that exhibits a frequency characteristic where impedance increases at the resonant frequency of the series resonant circuit. The first condition is ensured based on the impedance at the resonant frequency of the series resonant circuit containing the inductive element.

8. The semiconductor device according to any one of claims 1, 2, 3, 4, and 6, characterized in that, The set value is represented by the multiple of the impedance Zg in the first path to the impedance Zs in the third path, i.e., Zg / Zs, which is set to 10.

9. The semiconductor device according to any one of claims 1, 2, 3, 4, and 6, characterized in that, The first path includes an opening and closing device. When the semiconductor switching element is in the on state, the switching device is controlled to be in the closed state, and when the semiconductor switching element is in the off state, the switching device is controlled to be in the open state, thereby ensuring the first condition.

10. The semiconductor device according to any one of claims 1, 2, 3, 4, and 6, characterized in that, The connection point between the second electrodes of each semiconductor switching element on the second path connecting the second electrodes of each semiconductor switching element is designated as the first connection point, and the connection point between the third electrodes of each semiconductor switching element on the third path is designated as the second connection point. The impedances of each fourth path from the first connection point through each of the semiconductor switching elements to the second connection point are equal.

11. The semiconductor device as claimed in claim 10, characterized in that, The configuration is such that the impedance deviation between each of the fourth paths is within ±3%.

12. The semiconductor device as claimed in claim 7, characterized in that, The inductive element is a ferrite bead inductive element.

13. The semiconductor device according to any one of claims 1, 2, 3, 4, 6, 11, and 12, characterized in that, The semiconductor switching element uses a wide-bandgap semiconductor formed from silicon carbide, gallium nitride, or diamond.

14. The semiconductor device according to any one of claims 1, 2, 3, 4, 6, 11, and 12, characterized in that, The switching speed of the semiconductor switching element is adjusted to be above 10kA / μs.

15. A power conversion device, characterized in that, In each phase of a power converter that performs power conversion between direct current and alternating current, a semiconductor device as described in any one of claims 1 to 14 is provided. The control unit controls the power converter to perform power conversion between DC and AC.

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