Clock recovery circuit and communication device

Abstract

The application provides a clock recovery circuit and a communication device. The clock recovery circuit comprises a clock phase discrimination unit and a clock adjustment circuit. The clock phase discrimination unit comprises a processing module and a calculation unit. The processing module is configured to process a clock signal to be recovered, so as to output a first undersampling signal and a second undersampling signal with different sampling phases. The calculation unit is configured to estimate a time error signal of a first sampling clock according to an energy difference or an amplitude difference of the first undersampling signal and the second undersampling signal. The clock adjustment circuit is configured to adjust the first sampling clock according to the time error signal. The embodiments of the application can implement clock recovery for signals of various modulation formats, and the system stability and robustness are high.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a clock recovery circuit and a communication device. Background Technology

[0002] In a communication system, a transmitter can send data signals driven by a local clock. The receiver samples the data signal using a clock signal generated by a phase-locked loop (PLL) and detects the deviation between the sampling position and the transmitting clock sampling position. This time difference can be used to adjust the phase and frequency of the PLL-generated clock, thereby restoring the transmitter's clock. Therefore, accurately detecting the deviation between the receiving sampling position and the transmitting clock sampling position to drive the PLL for clock synchronization is crucial for the normal operation of a communication system.

[0003] Existing clock recovery circuits lack sufficient robustness in detecting clock skew. Furthermore, they are costly, power-consuming, and complex to implement. Summary of the Invention

[0004] In view of this, this application provides a clock recovery circuit and a communication device. By adopting the embodiments of this application, the local clock of the receiver and the clock of the transmitter can be synchronized quickly, and the power consumption is low, saving costs.

[0005] In a first aspect, embodiments of this application provide a clock recovery circuit, which includes a clock phase detection unit and a clock adjustment circuit. The clock phase detection unit includes a processing module and a calculation unit; the processing module processes the clock signal to be recovered to output a first undersampled signal and a second undersampled signal with different sampling phases; the calculation unit estimates a time error signal of the first sampled clock based on the energy difference or amplitude difference between the first undersampled signal and the second undersampled signal. The clock adjustment circuit adjusts the first sampled clock according to the time error signal.

[0006] By employing the embodiments of this application, the sampling clock can be adjusted according to the time error signal output by the clock phase detector unit, so that the time error is continuously reduced, thereby recovering the required clock signal and completing clock recovery. The embodiments of this application can quickly synchronize the local clock of the receiver and the clock of the transmitter, and have low power consumption and save costs.

[0007] In one possible design, the processing module includes a first processing unit and a second processing unit. The first processing unit performs signal processing on the clock signal to be recovered to output a first undersampled signal; the second processing unit performs signal processing on the clock signal to be recovered to output a second undersampled signal, wherein the sampling phases of the first undersampled signal and the second undersampled signal are different. Based on this design, the clock recovery circuit of this application can calculate the time error signal of the first sampled clock using two undersampled signals with different sampling phases, thereby completing clock recovery.

[0008] In one possible design, the first processing unit is used to undersample the clock signal to be recovered using a second sampling clock of the first phase, outputting a first undersampled signal; the second processing unit is used to undersample the clock signal to be recovered using a third sampling clock of the second phase, outputting a second undersampled signal; and the calculation unit is used to estimate the time error signal of the first sampling clock based on the energy difference or amplitude difference between the first and second undersampled signals. Based on this design, the clock recovery circuit of this application can obtain two undersampled signals by using two sampling clocks with different phases, thus allowing the calculation of the energy difference between the two undersampled signals and obtaining the time error signal more accurately.

[0009] In one possible design, the clock adjustment circuit is further configured to divide the first sampling clock to generate a second sampling clock for the first processing unit, and the clock adjustment circuit is further configured to delay the first sampling clock and divide the delayed first sampling clock to generate the third sampling clock, so as to output the third sampling clock to the second processing unit.

[0010] In one possible design, the clock recovery circuit further includes a demodulation unit electrically connected to the first sample-and-hold unit. The demodulation unit is used to demodulate the received signal, and the demodulated baseband signal is sampled by the first sample-and-hold unit to obtain the clock reconstructed sampled signal.

[0011] In one possible design, the clock recovery circuit further includes a power detection unit, which acquires the power amplitude of the baseband signal and performs clock recovery based on this power amplitude. With this design, the power detection unit can acquire the instantaneous power of the baseband signal corresponding to the high-frequency modulation signal and perform clock recovery based on this instantaneous power signal.

[0012] In one possible design, the clock recovery circuit further includes a first sample-and-hold unit, and the clock phase detector unit further includes a delay unit. The first sample-and-hold unit receives the baseband signal and samples and holds the baseband signal according to the first sampling clock to output an oversampled signal to the clock phase detector unit. The first processing unit extracts one output from the plurality of oversampled signals to output the first undersampled signal. The delay unit delays the oversampled signal and transmits the delayed oversampled signal to the second processing unit. The second processing unit extracts one output from the multiple delayed oversampled signals to output the second undersampled signal. Based on this design, the sampling clock can be adjusted according to the time error signal output by the clock phase detector unit, so that the time error continuously decreases to recover the required clock signal and complete clock recovery. The embodiments of this application can quickly synchronize the receiver's local clock and the transmitter's clock, and have low power consumption and save costs.

[0013] In one possible design, the clock phase detector unit further includes a first power processing unit and a second power processing unit. The first power processing unit is electrically connected to the first processing unit, and the second power processing unit is electrically connected to the second processing unit. The first power processing unit is used to calculate a first power of the first undersampled signal, and the second power processing unit is used to calculate a second power of the second undersampled signal. Based on this design, the calculation unit can obtain a time error signal by calculating the energy difference between the two powers, thereby achieving clock recovery.

[0014] In one possible design, the computing unit is connected to both the first power processing unit and the second power processing unit. The computing unit calculates the power energy difference between the first power and the second power to output the time error signal to the clock adjustment circuit. Based on this design, the computing unit can obtain the time error signal by calculating the energy difference between the two power sources, thereby achieving clock recovery.

[0015] In one possible design, the clock phase detection unit further includes a clock combining unit and a serial-to-parallel conversion unit. The clock combining unit is used to output a fourth sampling clock to the processing module. The processing module is used to undersample the clock signal to be recovered using the fourth sampling clock to output a first undersampled signal and a second undersampled signal to the serial-to-parallel conversion unit. The serial-to-parallel conversion unit is used to output the first undersampled signal and the second undersampled signal in parallel to the calculation unit.

[0016] In one possible design, the clock recovery circuit further includes a first sample-and-hold unit, and the clock phase detection unit further includes a serial-to-parallel conversion unit. The first sample-and-hold unit is used to receive the baseband signal and to sample and hold the baseband signal using the first sampling clock to output an oversampled signal to the clock phase detection unit. The processing module is used to extract two outputs from the multiple oversampled signals to output a first undersampled signal and a second undersampled signal with different sampling phases to the serial-to-parallel conversion unit.

[0017] In one possible design, the clock phase detector unit further includes a first power processing unit and a second power processing unit. The serial-to-parallel conversion unit is used to output the first undersampled signal and the second undersampled signal in parallel to the first power processing unit and the second power processing unit. The first power processing unit is used to calculate the first power of the first undersampled signal, and the second power processing unit is used to calculate the second power of the second undersampled signal. The calculation unit is used to calculate the power energy difference between the first power and the second power to output the time error signal to the clock adjustment circuit.

[0018] In one possible design, the clock phase detection unit further includes a first filtering unit, which is used to filter out the in-band spectral components of the clock signal to be recovered. Based on this design, the high-pass filtering unit can suppress noise and improve the robustness of the phase detection signal.

[0019] In one possible design, the clock recovery circuit further includes a second filtering unit connected to the calculation unit. This second filtering unit filters the time error signal to obtain a filtered time error signal. Based on this design, out-of-band noise can be suppressed, loop stability improved, and the clock recovery circuit can meet the performance requirements of certain applications.

[0020] In one possible design, the clock adjustment circuit is further configured to receive the filtered time error signal and adjust the frequency of the first sampling clock according to the filtered time error signal. Based on this design, the voltage-controlled oscillator unit can continuously reduce the time error and quickly synchronize the receiver's local clock and the transmitter's clock.

[0021] Secondly, embodiments of this application also provide a communication device, the communication device including the clock recovery circuit as described above.

[0022] The clock recovery circuit and communication device provided in this application can extract the clock signal from the received signal, perform clock phase detection, and drive the clock recovery circuit to achieve clock recovery. The clock recovery circuit of this application can be independent of the signal eye diagram, is applicable to various modulation modes, and can perform clock recovery before the receiver's channel equalization. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a clock recovery circuit provided in an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of a clock phase detector unit provided in an embodiment of this application.

[0025] Figure 3 Another schematic diagram of the clock recovery circuit provided in an embodiment of this application.

[0026] Figure 4a This is a signal spectrum diagram of the baseband signal in an embodiment of this application.

[0027] Figure 4b This is a frequency response diagram of the high-pass filter unit in an embodiment of this application.

[0028] Figure 5 This is a spectrum diagram of the signal after filtering by the high-pass filter unit in an embodiment of this application.

[0029] Figure 6 This is a spectrum diagram of the undersampled signal according to an embodiment of this application.

[0030] Figure 7 Another schematic diagram of the clock recovery circuit provided in an embodiment of this application.

[0031] Figure 8 Another schematic diagram of the clock recovery circuit provided in an embodiment of this application.

[0032] Figure 9 Another schematic diagram of the clock recovery circuit provided in an embodiment of this application.

[0033] Figure 10 Another schematic diagram of the clock recovery circuit provided in an embodiment of this application.

[0034] Figure 11 This is a schematic diagram of the sampling clock processing by the clock combining unit provided in the embodiments of this application.

[0035] Figure 12 Another schematic diagram of the clock recovery circuit provided in an embodiment of this application.

[0036] Figure 13 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application.

[0037] Explanation of main component symbols

[0038]

[0039] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0040] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or may also have a component that is centrally located. When a component is considered to be "set" on another component, it can be directly set on the other component or may also have a component that is centrally located.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] To facilitate understanding of the clock recovery circuit provided in the embodiments of this application, the application scenarios of the clock recovery circuit in the embodiments of this application are described below. This clock recovery circuit can be applied in communication equipment, and can be used to synchronize the local clock of the receiver and the clock of the transmitter.

[0043] In one possible scenario, a clock recovery circuit can detect the time error between the local clock and the transmitted clock by comparing the positional deviation between the sampling position and the edge or apex of the received eye diagram, thereby driving the phase-locked loop (PLL) to recover the clock. The clock recovery circuit in this scenario is highly dependent on the eye diagram of the received signal. However, for non-amplitude modulation (AM) communication systems, if the received signal does not include a simple eye diagram, the clock recovery circuit will fail. When intersymbol interference (ISI) exists in the transmission channel, the received signal of an AM communication system needs to undergo channel equalization to recover the eye diagram. In this case, an equalization module needs to be added to the clock recovery circuit, which will increase the loop delay, thereby reducing loop stability and clock tracking capability.

[0044] In another possible scenario, in a receiver using an orthogonal mixer architecture, a local clock at twice the signal baud rate is generated via a phase-locked loop (PLL) to oversample the received I / Q signals, thus obtaining two sampling points from each signal. Since the time interval between the two sampling points is half a symbol period, when the sampling clock is synchronized with the transmission clock, the two sampling points can simultaneously capture both the stable peak point and the transition point of the transmitted signal. Utilizing the statistical distribution characteristics of the transition and peak points, the statistical error when the sampling position deviates can be detected; this error corresponds to the time error between the sampling clock and the transmission clock. Clock recovery can then be achieved using this time error. The clock recovery method in the above scenario requires the receiver to sample the received signal at twice the symbol rate. However, in high-baud-rate transmission systems, generating a sampling clock at twice the rate would introduce significant power consumption and complexity.

[0045] Based on this, embodiments of this application provide a clock recovery circuit and a communication device. The clock recovery circuit and communication device can realize clock recovery for signals with various modulation formats. The clock recovery circuit can be independent of the eye diagram quality of the signal and can realize clock recovery at the front end of the receiver, with high system stability and robustness.

[0046] Please see Figure 1 , Figure 1 The diagram shown is a block diagram of a clock recovery circuit 100 provided in one embodiment of this application.

[0047] The clock recovery circuit 100 described in this embodiment can be applied to a receiver. It is understood that the receiver and transmitter can constitute a communication system. The transmitter can send signals driven by a local clock (e.g., a high-speed clock), and the receiver can receive these signals. The receiver can extract the transmitter's clock signal from the received signal using the clock recovery circuit 100, and then adjust its local clock signal based on the extracted transmitter clock signal, thereby synchronizing the receiver's local clock with the transmitter's clock.

[0048] In one embodiment, the clock recovery circuit 100 may include a sampling circuit 10, a clock phase detector unit 20, a loop filter unit 30, and a clock adjustment circuit 40. The sampling circuit 10 may be electrically connected to the clock phase detector unit 20 and the clock adjustment circuit 40, the clock phase detector unit 20 may be electrically connected to the loop filter unit 30, and the loop filter unit 30 may be electrically connected to the clock adjustment circuit 40.

[0049] It is understood that the sampling circuit 10 in this embodiment can sample the received signal of the receiver according to the local clock signal, and can output the sampled signal to the clock phase detector unit 20.

[0050] The clock phase detection unit 20 can estimate the time error between the sampling clock and the transmission clock from the clock signal to be recovered, and output the time error signal to the loop filtering unit 30.

[0051] The loop filtering unit 30 can filter the time error signal. The clock adjustment circuit 40 can adjust the filtered sampling clock to continuously reduce the time error, thereby completing clock recovery and realizing normal communication reception.

[0052] Please see Figure 2 , Figure 2 The diagram shown is a schematic diagram of the structure of a clock phase detector unit 20 provided in an embodiment of this application.

[0053] It is understood that the clock phase detection unit 20 in this embodiment may include a high-pass filter unit 22, a first processing unit 24, a second processing unit 26, and a calculation unit 28. The first processing unit 24 can be used to sample the input signal and output a sampled signal. The second processing unit 26 can be used to sample the input signal and output a sampled signal. The high-pass filter unit 22 can be electrically connected to the sampling circuit 10, the first processing unit 24 is electrically connected between the high-pass filter unit 22 and the calculation unit 28, the second processing unit 26 is electrically connected between the high-pass filter unit 22 and the calculation unit 28, and the calculation unit 28 is electrically connected to the loop filter unit 30. It is understood that in one embodiment, the calculation unit 28 can be a calculation unit or a comparator, and this application is not limited thereto. It is understood that in one possible implementation, the first processing unit 24 and the second processing unit 26 can be implemented using the same device or circuit. In one possible implementation, both the first processing unit 24 and the second processing unit 26 may include a sample-and-hold unit.

[0054] In this embodiment, the high-pass filter unit 22 can be used to filter out the in-band spectral components of the sampled signal, where the spectral component refers to the amplitude of the frequency in the frequency domain after transformation. The spectrum reflects the distribution of signal amplitude and phase with frequency, describing the characteristics of the signal in the frequency domain. The first processing unit 24 can undersample the filtered signal by a specific ratio using a sampling clock of the first phase, and output a first undersampled signal to the calculation unit 28. The second processing unit 26 can undersample the filtered signal by a specific ratio using a sampling clock of the second phase, and output a second undersampled signal to the calculation unit 28. The calculation unit 28 calculates the energy difference or amplitude difference between the two signals, and this energy difference is the time error. It can be understood that the difference between the first phase and the second phase can characterize that there is a time difference between the sampling clock of the first processing unit 24 and the sampling clock of the second processing unit 26.

[0055] It is understood that, in one embodiment, the sampling phases of the first undersampled signal and the second undersampled signal are different, and the different sampling phases can represent different sampling positions.

[0056] Please see Figure 3 , Figure 3 The diagram shown is a schematic diagram of the clock recovery circuit 100 provided in one embodiment of this application.

[0057] In this embodiment, the sampling circuit 10 may include an envelope detection unit 12 and a sample-and-hold unit 14. Specifically, the transmitter sends an amplitude-modulated signal to the receiver under the drive of a local clock. The envelope detection unit 12 can demodulate the received modulated signal to obtain the baseband signal. It can be understood that the sample-and-hold unit 14 can sample the baseband signal to obtain the reconstructed transmitted signal.

[0058] The envelope detection unit 12 can output a baseband signal to the high-pass filter unit 22. The high-pass filter unit 22 filters the baseband signal, and the output signal is sampled by the first processing unit 24 and the second processing unit 26 to obtain two undersampled signals. Since these two undersampled signals are unipolar signals (e.g., positive or negative signals), the energy difference can be approximated by a subtractor. Therefore, after calculation by the calculation unit 28, the energy difference or amplitude difference between the two signals can be approximated. The output of the calculation unit 28 is a time error signal. The calculation unit 28 outputs the time error signal to the clock adjustment circuit 40.

[0059] In one possible implementation, the clock adjustment circuit 40 may include a voltage-controlled oscillator unit 41, a first frequency divider unit 42, a second frequency divider unit 43, and a first clock delay unit 44.

[0060] In this embodiment, the voltage-controlled oscillator unit 41 can be electrically connected to the loop filter unit 30, the first frequency divider unit 42 is electrically connected between the voltage-controlled oscillator unit 41 and the first processing unit 24, and the second frequency divider unit 43 is electrically connected between the second processing unit 26 and the first clock delay unit 44. The first clock delay unit 44 is electrically connected to the voltage-controlled oscillator unit 41. The sample-and-hold unit 14 can also be electrically connected to the first clock delay unit 44 and the voltage-controlled oscillator unit 41. It can be understood that, in one possible implementation, the first clock delay unit 44 can be a shift register or a digital buffer unit.

[0061] In the specific implementation of this application, the loop filtering unit 30 can filter the time error signal output by the clock phase detector unit 20 and transmit the filtered signal to the voltage-controlled oscillator unit 41. This can suppress out-of-band noise, improve loop stability, and enable the clock recovery circuit 100 to meet certain high-performance requirements. In one possible implementation, the loop filtering unit 30 can be any one of a first-order filter, a second-order filter, or a higher-order filter; this application does not limit this.

[0062] The voltage-controlled oscillator unit 41 can generate a clock signal based on the received time error signal, and the frequency of the clock signal can be adjusted under the control of the input signal. Based on this design, the time error signal output by the clock phase detector unit 20 can be processed sequentially by the loop filter unit 30 and the voltage-controlled oscillator unit 41 to output a clock signal with a symbol rate of M / N times, where M>N. It can be understood that this clock signal can drive the sample-and-hold unit 14 to perform normal signal sampling.

[0063] It is understood that, in one possible implementation, the clock signal of the voltage-controlled oscillator unit 41 can also be output to the first frequency divider unit 42 and the first clock delay unit 44. Specifically, the first frequency divider unit 42 receives the clock signal output by the voltage-controlled oscillator unit 41, and the clock signal can be divided by 1 / M times by the first frequency divider unit 42 to obtain the first undersampled clock.

[0064] The clock signal output by the voltage-controlled oscillator unit 41 can be delayed by L beats by the first clock delay unit 44, and then passed through the second frequency divider unit 43 by a factor of 1 / M to generate a second undersampled clock. It can be understood that the signals of the first undersampled clock and the second undersampled clock can be used to drive the first processing unit 24 and the second processing unit 26 in the clock phase detector unit 20, respectively.

[0065] Figure 4a The image shows the signal spectrum of the baseband signal. Figure 4b The diagram shows the frequency response of the high-pass filter unit 22. It can be understood that the high-pass filter unit 22 can filter the baseband signal. The bandwidth of the baseband signal can be (1+α)×B.

[0066] Where B is the symbol baud rate, α is the roll-off factor, and α < 1. From Figure 4a and Figure 4b Therefore, in this embodiment, the optimal high-pass cutoff frequency of the high-pass filter unit 22 is fc = (1-α) / 2 × B. The narrower the transition band of the high-pass filter unit 22, the better.

[0067] Figure 5 The image shows the signal spectrum after filtering by the high-pass filter unit 22. It can be seen that the filtered signal only contains the spectra of the sidebands and roll-off region.

[0068] When there is a clock delay of length τ between the sampled signal and the transmitted signal, according to the characteristics of the Fourier transform, the spectrum of the sampled signal can be equivalent to a linear phase difference τf superimposed on the phase frequency response of the transmitted signal, that is, the spectrum R(f) of the received signal can satisfy the following formula (1):

[0069] (1)

[0070] Where S(f) is the spectrum of the transmitted signal. Based on the periodicity of the spectrum of the transmitted signal outside the sideband, the spectrum of S(f) is the same near f=±B / 2 on both sidebands, that is, S(-B / 2)= S(B / 2).

[0071] It is understandable that, in a certain scenario, if the spectrum R(f) of the received signal is undersampled in a specific way, an undersampled signal with an integer multiple of the transmitted symbol period can be obtained, and the spectrum S(f) of the received signal will be aliased. Since the period of the undersampled signal is an integer multiple of the symbol period, the spectra near the two sidebands f=±B / 2 can be superimposed on the same frequency point when aliased, and the aliased spectrum can satisfy the following formula (2):

[0072] (2)

[0073] Where f0 represents the original sideband frequency point f=±B / 2 after aliasing. Since the aliased spectrum D has a cosine component related to τ, the amplitude of D in formula (2) can reach its maximum value when τ=0. Therefore, the amplitude value of D can have the ability to detect time errors.

[0074] If the clock period of the undersampled signal is four times the clock period of the transmitted signal, the spectrum of the sampled signal will be aliased four times.

[0075] like Figure 6 As shown, the aliased spectrum can be formed by superimposing parts g1, g2, g3, and g4. Parts g1, g2, g3, and g4 correspond to four sub-spectral segments of the signal spectrum before undersampling. It can be understood that parts g3 and g4 are roll-off regions of two sidebands. The aliased spectrum D of this roll-off region can detect clock errors; therefore, parts g3 and g4 can be useful signals for identifying clock errors. Parts g1 and g2 are located within the in-band segments of the original signal spectrum. Due to the randomness of their spectral content, they cannot be used to identify clock errors after aliasing, and the detection of clock errors is considered noise. Therefore, to improve the signal-to-noise ratio (SNR) for detecting time errors, the embodiments of this application can suppress the in-band spectral components before undersampling using the high-pass filter unit 22, thereby significantly improving the SNR of the useful signal after undersampling and the accuracy of time error detection.

[0076] For example, the roll-off factor can be α=0.2, and the sampling clock CLKc can be 1.25 times the symbol baud rate, i.e., M / N=5 / 4. The sampling clock CLKc can be the clock signal recovered by the voltage-controlled oscillator unit 41. If the sampling clock CLKc generated by the clock recovery circuit 100 needs to be maintained at M / N=5 / 4 times the transmit clock, the clock phase detector unit 20 needs to detect the clock error of the signal filtered by the high-pass filter unit 22 according to the detection principle of the aliasing spectrum D.

[0077] It is understood that in this embodiment, the first frequency divider unit 42 can generate an undersampled clock CLKa based on the sampling clock CLKc output by the voltage-controlled oscillator unit 41. The first clock delay unit 44 receives the sampling clock CLKc output by the voltage-controlled oscillator unit 41 and delays the sampling clock CLKc. The second frequency divider unit 43 can generate an undersampled clock CLKb based on the delayed sampling clock CLKc from the voltage-controlled oscillator unit.

[0078] In some scenarios, the period of the undersampled clock can be an integer multiple of the symbol period, and both the first frequency division unit 42 and the second frequency division unit 43 can be 1 / M frequency division, such as a 1 / 5 frequency division unit.

[0079] In the embodiments of this application, when the clocks generated by the first frequency divider unit 42 and the second frequency divider unit 43 drive the first processing unit 24 and the second processing unit 26 to undersample the signal filtered by the high-pass filter unit 22, the period of the undersampling clock can be N times (e.g., 4 times) the transmission clock period. Therefore, the spectrum of the sampled signal will undergo 4 times aliasing.

[0080] In one possible implementation, when the first frequency divider unit 42 divides the sampling clock CLKc to generate an undersampled clock CLKa, one undersampled clock CLKa is generated every M sampling clocks CLKc. Any one of the M consecutive sampling clocks CLKc can be used as the starting clock clock of the undersampled clock CLKa. Therefore, the first frequency divider unit 42 and the second frequency divider unit 43 can have M different frequency division time differences when dividing the frequency.

[0081] It is understandable that, in one possible implementation, for a sampling clock CLKc with M / N times oversampling, if the time error between the first sampling clock CLKc and the transmitting clock is τ, then there are M different frequency division time differences. The following formula (3) must be satisfied:

[0082] (3)

[0083] Where T = 1 / B, and T is the symbol period of the transmitted signal. In this embodiment, M = 5 and N = 4, therefore the five different frequency division time differences are respectively , , , , .

[0084] It can be understood that the clock recovery circuit 100 according to the embodiments of the present application can generate two undersampled clocks CLKa and CLKb with different frequency division time differences through the first clock delay unit and two frequency division units. Among them, the frequency division time difference of the undersampled clock CLKb can be denoted as τb, and the frequency division time difference of the undersampled clock CLKa can be denoted as τa. In this embodiment, the frequency division time difference τb of the undersampled clock CLKb is delayed by L beats of the sampling clock CLKc compared to the frequency division time difference τa of the undersampled clock CLKa, and 1 < L < M. It can be understood that, as described above, under the condition of 1 / M frequency division, the undersampled clock can have M different starting sampling phases. Therefore, the effect of L ≥ M can be the same as the effect within the range of 1 < L < M, and it can still fall within the effect range of the present application.

[0085] It can be understood that when the sampling clock CLKc is delayed by L beats, there is a time difference between the frequency division time difference τb and the frequency division time difference τa, and this time difference can be .

[0086] As can be seen from formula (3), .

[0087] In a possible implementation manner, the first clock delay unit 44 may include L latches. It can be understood that in some other possible implementation manners, the first clock delay unit 44 may also include a shift register, a delay line, a state machine, etc. The present application does not make any limitations in this regard.

[0088] It can be understood that in some possible implementation manners, the first processing unit 24 may sample the signal filtered by the high-pass filter unit 22 under the drive of the undersampled clock CLKa, and the aliasing spectrum Da may satisfy the following formula (4):

[0089] (4)

[0090] It can be understood that in some possible implementation manners, the second processing unit 26 may sample the signal filtered by the high-pass filter unit 22 under the drive of the undersampled clock CLKb, and the aliasing spectrum Db may satisfy the following formula (5):

[0091] (5)

[0092] Thus, by taking the difference between Da and Db, the phase discrimination error Err of the clock phase discrimination unit 20 can be obtained, that is, the phase discrimination error Err may satisfy the following formula (6):

[0093] (6)

[0094] As can be seen from the above formula (6), if the phase detection error Err is used to drive the clock recovery circuit to complete the locking, the phase detection error Err can be kept at 0, that is, the undersampled clock CLKa can be locked to a stable frequency division time difference. Furthermore, if the sampling clock CLKc has M frequency division time differences... There exists a certain frequency division time difference. ,but Then the sampling clock CLKc can lock and restore the transmitting clock at a multiple of M / N.

[0095] It is understood that in this embodiment, since the signal input to the clock phase detector unit 20 passes through the envelope detector unit 12, the amplitude of the baseband signal is positive. The spectral energy of this positive signal can be proportional to the signal amplitude. This embodiment uses an undersampled signal to replace its spectral energy D for difference calculation, thereby enabling the detection of time errors.

[0096] In one possible implementation, the first clock delay unit 44 may include a latch, i.e., L=1. In this case, β=0.8, the frequency division time difference of the undersampled clock CLKa is τa=-0.4T, and there is a frequency division time difference τj=τa+0.4T=0 in the sampled clock CLKc. Therefore, the undersampled clock CLKc achieves the recovery of 1.25 times the transmission clock. It can be understood that in another possible implementation, the subtractor used in the above formula (6) can also be replaced by a comparator, and the phase detection error Err can satisfy the following formula (7):

[0097] (7)

[0098] Where, if a>0, Sign{a}=1; if a<0, Sign{a}=-1; if a=0, Sign{a}=0.

[0099] It can be understood that from the above formula (7), when Da is greater than Db, the phase detection error Err is equal to 1; when Da is less than Db, the phase detection error Err is equal to -1; when Da is equal to Db, the phase detection error Err is equal to 0.

[0100] The clock recovery circuit of the embodiments of this application can extract the clock signal from the received signal and perform clock phase detection. When the sampling clock is M / N times the transmitted clock, it is only necessary to satisfy M>N to detect the time error and drive the clock recovery circuit to achieve clock recovery. The embodiments of this application do not depend on the signal eye diagram, can be applied to various modulation modes, and can perform clock recovery before the channel equalization of the receiver.

[0101] Please see Figure 7 , Figure 7 The diagram shown is a schematic diagram of the clock recovery circuit 100 provided in another embodiment of this application.

[0102] and Figure 3 The difference in the clock recovery circuit 100 shown is that, as Figure 7 As shown, the clock recovery circuit 100 in this embodiment may further include a second clock delay unit 45 and a third frequency divider unit 46.

[0103] In this embodiment, the second clock delay unit 45 can be electrically connected to the voltage-controlled oscillator unit 41 and the first clock delay unit 44, and the third frequency divider unit 46 can be electrically connected to the second clock delay unit 45 and the sample-and-hold unit 14.

[0104] It is understood that the third frequency divider unit 46 can receive the sampling clock CLKc and can be used to generate a sampling clock CLKd that is locked to the same frequency as the transmitting clock. In one possible implementation, the third frequency divider unit 46 can be an N / M frequency divider unit, that is, the third frequency divider unit 46 can be a 1 / M frequency divider unit connected in series with an N-fold multiplier.

[0105] To achieve a clock in phase with the transmitting clock, the sampling clock CLKd output by the third frequency divider unit 46 needs to have no time error of non-integer symbol periods with the transmitting clock. Therefore, in this embodiment, before the third frequency divider unit 46 performs N / M frequency conversion on the sampling clock CLKc, a second clock delay unit 45 of length H can be added. This second clock delay unit 45 can obtain a clock signal with a time difference of τd from the transmitting clock. It can be understood that H can be the number of clock delays by the second clock delay unit 45.

[0106] In this embodiment, the time difference τa can be locked to a fixed deviation determined by L. Therefore, the second delay unit 45 can delay H, that is, it can generate a fixed deviation between the time difference τd and the time difference τa. That is, τd-τa= This means that the time difference between the sampling clock CLKd and the transmitting clock (which is not an integer symbol period) can be eliminated, thus achieving clock in-phase operation. In one scenario, half the time error between the sampling clock CLKb and the sampling clock CLKa generated by L can be canceled out by the time error between the sampling clock CLKd and the sampling clock CLKa generated by H. In this case, the canceled time error is 0 or can be an integer multiple of the transmitting clock period. In another scenario, L=1, β=0.8, H=3, and τd-τa=0.4T. In this case, the sampling clock CLKd can be in-phase with the transmitting clock, and the time error is 0.

[0107] In another possible implementation, when the receiver does not have a requirement for the sampling clock CLKd to be in phase with the transmitting clock, or when... When τd = 0, τd can also be 0. In this case, there may be no second clock delay unit 45 between the third frequency division unit 46 and the voltage-controlled oscillator unit 41.

[0108] Please see Figure 8 , Figure 8 The diagram shown is a schematic diagram of the clock recovery circuit 100 provided in another embodiment of this application.

[0109] and Figure 3 The difference in the clock recovery circuit 100 shown is that, as Figure 8 As shown, the clock recovery circuit 100 in this embodiment may further include a demodulation unit 50 and a power detection unit 51.

[0110] In this embodiment, the demodulation unit 50 is electrically connected to the sample and hold unit 14, and the power detection unit 51 is electrically connected between the demodulation unit 50 and the high-pass filter unit 22.

[0111] The demodulation unit 50 is used to demodulate the received high-frequency modulated signal. The demodulated baseband signal can be sampled by the sample-and-hold unit 14 under the drive of the recovered sampling clock to obtain the clock-reconstructed sampling signal.

[0112] The power detection unit 51 is used to acquire the instantaneous power of the baseband signal corresponding to the high-frequency modulation signal, and to perform clock recovery using this instantaneous power signal. Optionally, the power detection unit 51 can be a self-mixer, an envelope detector unit, or a photodiode, etc. Based on this design, the power detection unit 51 can directly obtain the baseband power of the modulation signal.

[0113] Please see Figure 9 , Figure 9The diagram shown is a schematic diagram of the clock recovery circuit 100 provided in another embodiment of this application.

[0114] The clock recovery circuit 100 in this embodiment may include a mixer unit 60, a sample and hold unit 70, a clock phase detector unit 20, a loop filter unit 30, and a voltage-controlled oscillator unit 41.

[0115] The mixing unit 60 can be electrically connected to the sample and hold unit 70, the sample and hold unit 70 is electrically connected to the clock phase detector unit 20, the clock phase detector unit 20 is connected to the loop filter unit 30, and the voltage-controlled oscillator unit 41 is electrically connected between the sample and hold unit 70 and the loop filter unit 30.

[0116] In this embodiment, the mixing unit 60 can be used to receive a high-frequency modulated signal and demodulate the received high-frequency modulated signal into a baseband signal. The mixing unit 60 can also transmit the baseband signal to the sample-and-hold unit 70. It is understood that, in one possible implementation, the mixing unit 60 can be an I / Q mixer.

[0117] The sample-and-hold unit 70 can be used to receive the baseband signal output by the mixing unit 60, and to sample and hold the baseband signal according to the sampling clock CLKc, so as to output an oversampled signal to the clock phase detector unit 20.

[0118] In this embodiment, the clock phase detection unit 20 may include a high-pass filter unit 22, a delay unit 47, a first processing unit 24, a second processing unit 26, a first power processing unit 80, a second power processing unit 82, and a calculation unit 28.

[0119] The high-pass filter unit 22 is electrically connected to the sample-and-hold unit 70, the first processing unit 24 and the delay unit 47. The first processing unit 24 is electrically connected to the first power processing unit 80. The delay unit 47 is electrically connected to the second processing unit 26. The second power processing unit is electrically connected to the second processing unit 26 and the calculation unit 28. The first power processing unit 80 is electrically connected to the calculation unit 28.

[0120] The high-pass filter unit 22 can be used to perform high-pass filtering on the oversampled signal. In one embodiment, the high-pass filter unit 22 can be any one of an analog filter, a finite-length impulse response (FIR) filter, or a digital filter.

[0121] The first processing unit 24 can extract one output from every M signals in the oversampled signal filtered by the high-pass filter unit 22 to obtain the first undersampled signal.

[0122] The delay unit 47 is used to delay the oversampled signal. It is understood that, in one possible implementation, the delay unit 47 may be a shift register or a digital buffer unit.

[0123] The second processing unit 26 is used to extract one output from every M signals in the input oversampled signal to obtain the second undersampled signal.

[0124] The first power processing unit 80 is used to calculate the power of the first undersampled signal.

[0125] The second power processing unit 82 is used to calculate the power of the second undersampled signal.

[0126] In this embodiment, the calculation unit 28 can be used to calculate the difference between two power energies and output a time error signal to the loop filter unit 30.

[0127] Please see Figure 10 , Figure 10 The diagram shown is a schematic diagram of the clock recovery circuit 100 provided in another embodiment of this application.

[0128] like Figure 10 As shown, the clock phase detection unit 20 in this embodiment includes a high-pass filter unit 22, a processing module 25, a serial-to-parallel conversion unit 27, a calculation unit 28, and a clock combining unit 29.

[0129] The processing module 25 is electrically connected between the high-pass filter unit 22 and the serial-to-parallel conversion unit 27, the clock combining unit 29 is electrically connected between the clock adjustment circuit 40 and the processing module 25, and the serial-to-parallel conversion unit 27 is electrically connected to the computing unit 28.

[0130] and Figure 3 The difference in the clock recovery circuit 100 shown is that, as Figure 10 As shown, in this embodiment, the first processing unit 24 and the second processing unit 26 can be implemented using the same device or circuit. The processing module 25 in this embodiment may include a sample-and-hold unit. The processing module 25 can process the clock signal to be recovered to output two undersampled signals with different sampling phases.

[0131] Specifically, the clock combining unit 29 is electrically connected to the first frequency divider unit 42 and the second frequency divider unit 43. The first frequency divider unit 42 and the second frequency divider unit 43 output undersampled clocks CLKa and CLKb to the clock combining unit 29, respectively. The clock combining unit 29 outputs a sampling clock CLKe to the processing module 25 to drive the processing module 25 to perform signal sampling. Thus, the processing module 25 can sample the signal output by the high-pass filter unit 22 under the drive of a sampling clock CLKe that is 2 / N times its normal value, to obtain a sampled signal. This sampled signal can be input to the serial-to-parallel conversion unit 27, which can output two undersampled signals in parallel to the calculation unit 28.

[0132] The serial-to-parallel conversion unit 27 can process two consecutive input signals and output the two signals in parallel from two output ports. It is understood that, in one possible implementation, the serial-to-parallel conversion unit 27 can be implemented using two alternately operating latches. In another possible implementation, the serial-to-parallel conversion unit 27 can also be implemented using a buffer with a depth of 2.

[0133] It is understood that in this embodiment, the undersampled clock CLKa and the undersampled clock CLKb are two clock signals with different phases. Figure 11 As shown, the undersampled clocks CLKa and CLKb have different level transition positions within one cycle. The clock combining unit 29 combines the two clocks to obtain the sampling clock CLKe. The sampling clock CLKe includes the level transition positions of both clocks within one cycle, and its clock frequency is twice that of both the undersampled clocks CLKa and CLKb.

[0134] In one possible implementation, the clock combining unit 29 can be implemented using a signal combiner or an adder.

[0135] It can be understood that, in this embodiment, the two signals output in parallel by the serial-to-parallel conversion unit 27 are equivalent to the signals sampled under the drive of the undersampled clock CLKa and the undersampled clock CLKb. Therefore, the effect of the clock phase detector unit 20 in this embodiment is similar to... Figure 3 The clock phase detector unit 20 in the embodiment has the same effect.

[0136] Please see Figure 12 , Figure 12 The diagram shown is a schematic diagram of the clock recovery circuit 100 provided in another embodiment of this application.

[0137] and Figure 9 The difference in the clock recovery circuit 100 shown is that, as Figure 12 As shown, the clock phase detection unit 20 in this embodiment may include a high-pass filter unit 22, a processing module 25, a serial-to-parallel conversion unit 27, a first power processing unit 80, a second power processing unit 82, and a calculation unit 28.

[0138] The high-pass filter unit 22 is electrically connected to the sample-and-hold unit 70 and the processing module 25. The serial-to-parallel conversion unit 27 is electrically connected to the first power processing unit 80 and the second power processing unit 82. The serial-to-parallel conversion unit 27 is also electrically connected to the processing module 25. The first power processing unit 80 and the second power processing unit 82 are electrically connected to the computing unit 28.

[0139] In this embodiment, the high-pass filter unit 22 can be used to perform high-pass filtering on the oversampled signal. In one embodiment, the high-pass filter unit 22 can be any one of an analog filter, a finite-length impulse response (FIR) filter, or a digital filter.

[0140] The processing module 25 can extract the oversampled signal filtered by the high-pass filter unit 22 and output an undersampled signal. In this embodiment, the processing module 25 can extract two signals from every M signals in the received oversampled signal and output them. It can be understood that the two different extraction positions of the signal extraction unit correspond to two different undersampled phases.

[0141] The output of the processing module 25 can be processed by a 1:2 serial-to-parallel conversion unit 27. The serial-to-parallel conversion unit 27 can output two parallel undersampled signals to the first power processing unit 80 and the second power processing unit 82 respectively. Specifically, the serial-to-parallel conversion unit 27 can output a first undersampled signal and a second undersampled signal to the first power processing unit 80 and the second power processing unit 82 respectively. The first and second undersampled signals output by the processing module 25 have different phases. It is understood that in one possible implementation, the serial-to-parallel conversion unit 27 can be implemented using two alternately operating latches. In another possible implementation, the serial-to-parallel conversion unit 27 can also be implemented using a buffer with a depth of 2.

[0142] The first power processing unit 80 is used to calculate the power of the first undersampled signal.

[0143] The second power processing unit 82 is used to calculate the power of the second undersampled signal.

[0144] In this embodiment, the calculation unit 28 can be used to calculate the difference between two power energies and output a time error signal to the loop filter unit 30.

[0145] Please see Figure 13 Embodiments of this application also provide a communication device 200, such as... Figure 13 As shown, the communication device 200 may include the clock recovery circuit 100 described in the above embodiments, and the communication device 200 can operate on the required clock signal. The clock can be synchronized through the function of the clock recovery circuit 100.

[0146] The above description is merely a preferred embodiment of this application and is not intended to limit this application in any way. Although the preferred embodiment has been disclosed above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A clock recovery circuit, characterized by comprising: The clock recovery circuit includes: A clock phase detection unit includes a processing module and a calculation unit. The processing module processes the clock signal to be recovered to output a first undersampled signal and a second undersampled signal with different sampling phases. The calculation unit estimates the time error signal of the first sampled clock based on the energy difference or amplitude difference between the first undersampled signal and the second undersampled signal. A clock adjustment circuit is used to adjust the first sampling clock according to the time error signal.

2. The clock recovery circuit according to claim 1, characterized in that, The processing module includes a first processing unit and a second processing unit. The first processing unit is used to perform signal processing on the clock signal to be recovered to output a first undersampled signal. The second processing unit is used to perform signal processing on the clock signal to be recovered to output a second undersampled signal. The sampling phases of the first undersampled signal and the second undersampled signal are different.

3. The clock recovery circuit according to claim 2, characterized in that, The first processing unit is used to undersample the clock signal to be recovered using a second sampling clock of the first phase and output a first undersampled signal. The second processing unit is used to undersample the clock signal to be recovered using a third sampling clock of the second phase and output a second undersampled signal. The calculation unit is used to estimate the time error signal of the first sampling clock based on the energy difference or amplitude difference between the first undersampled signal and the second undersampled signal.

4. The clock recovery circuit according to claim 3, characterized in that, The clock adjustment circuit is further configured to divide the first sampling clock to generate a second sampling clock for the first processing unit. The clock adjustment circuit is further configured to delay the first sampling clock and divide the delayed first sampling clock to generate the third sampling clock, and output the third sampling clock to the second processing unit.

5. The clock recovery circuit according to any one of claims 2-4, characterized in that, The clock recovery circuit further includes a demodulation unit, which is electrically connected to the first sample-and-hold unit. The demodulation unit is used to demodulate the received signal, and the baseband signal obtained by demodulation is sampled by the first sample-and-hold unit to obtain the sampled signal after clock reconstruction.

6. The clock recovery circuit according to claim 5, characterized in that, The clock recovery circuit further includes a power detection unit, which is used to obtain the power amplitude of the baseband signal and perform clock recovery based on the power amplitude.

7. The clock recovery circuit according to claim 2, characterized in that, The clock recovery circuit further includes a first sample-and-hold unit, and the clock phase detection unit further includes a delay unit. The first sample-and-hold unit is used to receive a baseband signal and sample and hold the baseband signal according to the first sampling clock to output an oversampled signal to the clock phase detection unit. The first processing unit is used to extract one output from the plurality of oversampled signals to output the first undersampled signal. The delay unit is used to delay the oversampled signal and transmit the delayed oversampled signal to the second processing unit. The second processing unit is used to extract one output from the plurality of delayed oversampled signals to output the second undersampled signal.

8. The clock recovery circuit according to any one of claims 2-4, characterized in that, The clock phase detection unit further includes a first power processing unit and a second power processing unit. The first power processing unit is electrically connected to the first processing unit, and the second power processing unit is electrically connected to the second processing unit. The first power processing unit is used to calculate the first power of the first undersampled signal, and the second power processing unit is used to calculate the second power of the second undersampled signal.

9. The clock recovery circuit according to claim 8, characterized in that, The computing unit is connected to the first power processing unit and the second power processing unit. The computing unit is used to calculate the power energy difference between the first power and the second power, so as to output the time error signal to the clock adjustment circuit.

10. The clock recovery circuit according to claim 1, characterized in that, The clock phase detection unit further includes a clock combining unit and a serial-to-parallel conversion unit. The clock combining unit is used to output a fourth sampling clock to the processing module. The processing module is used to undersample the clock signal to be recovered using the fourth sampling clock to output the first undersampled signal and the second undersampled signal to the serial-to-parallel conversion unit. The serial-to-parallel conversion unit is used to output the first undersampled signal and the second undersampled signal in parallel to the calculation unit.

11. The clock recovery circuit according to claim 1, characterized in that, The clock recovery circuit further includes a first sample-and-hold unit, and the clock phase detection unit further includes a serial-to-parallel conversion unit. The first sample-and-hold unit is used to receive the baseband signal and to sample and hold the baseband signal using the first sampling clock to output an oversampled signal to the clock phase detection unit. The processing module is used to extract two outputs from the multiple oversampled signals to output a first undersampled signal and a second undersampled signal with different sampling phases to the serial-to-parallel conversion unit.

12. The clock recovery circuit according to claim 11, characterized in that, The clock phase detection unit further includes a first power processing unit and a second power processing unit. The serial-to-parallel conversion unit is used to output the first undersampled signal and the second undersampled signal in parallel to the first power processing unit and the second power processing unit. The first power processing unit is used to calculate the first power of the first undersampled signal, and the second power processing unit is used to calculate the second power of the second undersampled signal. The calculation unit is used to calculate the power energy difference between the first power and the second power, so as to output the time error signal to the clock adjustment circuit.

13. The clock recovery circuit according to any one of claims 1-4, characterized in that, The clock phase detection unit further includes a first filtering unit, which is used to filter out the in-band spectral components of the clock signal to be recovered.

14. The clock recovery circuit according to any one of claims 1-4, characterized in that, The clock recovery circuit further includes a second filtering unit connected to the calculation unit. The second filtering unit is used to filter the time error signal to obtain a filtered time error signal.

15. The clock recovery circuit according to claim 14, characterized in that, The clock adjustment circuit is also used to receive the filtered time error signal and adjust the frequency of the first sampling clock according to the filtered time error signal.

16. A communication device, characterized by The communication device includes a clock recovery circuit as described in any one of claims 1-15.

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