Substrate including interconnects embedded in a solder resist layer

Abstract

A substrate comprising: a core layer; at least one first dielectric layer over a first surface of the core layer; at least one second dielectric layer over a second surface of the core layer; a plurality of first interconnects over a surface of the at least one first dielectric layer; a plurality of second interconnects over the surface of the at least one first dielectric layer; a plurality of third interconnects over the surface of the at least one first dielectric layer; and a solder resist layer over a surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are coplanar with the plurality of first interconnects. The solder resist layer comprises a first portion, a second portion, and a third portion.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to and the benefit of pending non-provisional application No. 17 / 066,318 filed in the United States Patent and Trademark Office on October 8, 2020, the contents of which are incorporated herein as if fully set forth below in their entirety and for all applicable purposes. TECHNICAL FIELD

[0003] Various features relate to substrates, and more particularly, to substrates including high density interconnects. BACKGROUND

[0004] Figure 1 A package 100 is illustrated including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. The plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. The plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. Manufacturing substrates including high density interconnects can be expensive. There is a continuing need to provide low cost substrates including high density interconnects. SUMMARY

[0005] Various features relate to substrates, and more particularly, to substrates including high density interconnects.

[0006] One example provides a substrate comprising: a core layer; at least one first dielectric layer over a first surface of the core layer; at least one second dielectric layer over a second surface of the core layer; a plurality of first interconnects over a surface of the at least one first dielectric layer; a plurality of second interconnects over the surface of the at least one first dielectric layer; a plurality of third interconnects over the surface of the at least one first dielectric layer; and a solder resist layer over a surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are coplanar with the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion. The first portion of the solder resist layer contacting the plurality of first interconnects includes a first thickness that is less than a thickness of the plurality of first interconnects. The second portion of the solder resist layer contacting the plurality of second interconnects includes a second thickness that is greater than a thickness of the plurality of second interconnects. The third portion of the solder resist layer is over a top surface and a side surface of the plurality of third interconnects.

[0007] Another example provides an apparatus comprising an integrated device and a substrate coupled to the integrated device. The substrate comprises: a core layer; at least one first dielectric layer over a first surface of the core layer; at least one second dielectric layer over a second surface of the core layer; a feature for a first interconnect over a surface of the at least one first dielectric layer; a feature for a second interconnect over the surface of the at least one first dielectric layer; a feature for a third interconnect over the surface of the at least one first dielectric layer; and a solder resist layer over a surface of the at least one second dielectric layer. The feature for the third interconnect and the feature for the second interconnect are coplanar with the feature for the first interconnect. The solder resist layer comprises a first portion, a second portion, and a third portion. The first portion of the solder resist layer contacting the feature for the first interconnect comprises a first thickness that is less than a thickness of the feature for the first interconnect. The second portion of the solder resist layer contacting the feature for the second interconnect comprises a second thickness that is greater than a thickness of the feature for the second interconnect. The third portion of the solder resist layer is over a top surface and a side surface of the feature for the third interconnect.

[0008] Another example provides a method for fabricating a substrate. The method provides a core layer comprising a first surface and a second surface. The method forms at least one first dielectric layer over the first surface of the core layer. The method forms at least one second dielectric layer over the second surface of the core layer. The method forms a plurality of first interconnects over a surface of the at least one first dielectric layer. The method forms a plurality of second interconnects over the surface of the at least one first dielectric layer. The plurality of second interconnects and the plurality of first interconnects are on a same metal layer. The method forms a plurality of third interconnects over the surface of the at least one first dielectric layer. The plurality of third interconnects, the plurality of second interconnects, and the plurality of first interconnects are on a same metal layer. The method forms a solder resist layer over the surface of the at least one first dielectric layer. The method removes a portion of the solder resist layer. A first portion of the solder resist layer contacting the plurality of first interconnects comprises a first thickness that is less than a thickness of the plurality of first interconnects. A second portion of the solder resist layer contacting the plurality of second interconnects comprises a second thickness that is greater than a thickness of the plurality of second interconnects. A third portion of the solder resist layer is over a top surface and a side surface of the plurality of third interconnects. BRIEF DESCRIPTION OF DRAWINGS

[0009] Various features, nature, and advantages will become apparent from the specific embodiments set forth below when considered in connection with the drawings, in which like numbers in different drawings correspond to like components throughout.

[0010] Figure 1 A cross-sectional view of a package comprising a substrate and an integrated device coupled to the substrate is illustrated.

[0011] Figure 2A cross-sectional view of a package including a substrate and an integrated device coupled to high density interconnects and interconnects embedded in a solder resist layer of the substrate is illustrated.

[0012] Figure 3 A cross-sectional view of a package including a substrate and an integrated device coupled to high density interconnects and interconnects embedded in a solder resist layer of the substrate is illustrated.

[0013] Figure 4 A plan view of a substrate including high density interconnects and interconnects embedded in a solder resist layer of the substrate is illustrated.

[0014] Figure 5 A plan view of a substrate including high density interconnects and interconnects embedded in a solder resist layer of the substrate is illustrated.

[0015] Figure 6 A cross-sectional view of a package including a substrate and an integrated device coupled to high density interconnects and interconnects embedded in a solder resist layer of the substrate is illustrated.

[0016] Figures 7A-7E An exemplary sequence for fabricating a substrate including high density interconnects embedded in a solder resist layer is illustrated.

[0017] Figure 8 An exemplary flowchart of a method for fabricating a substrate including high density interconnects embedded in a solder resist layer is illustrated.

[0018] Figure 9 An exemplary sequence for fabricating a package including an integrated device and a substrate including high density interconnects embedded in a solder resist layer is illustrated.

[0019] Figure 10 Various electronic devices that can incorporate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive elements, packages, and / or device packages described herein are illustrated. DETAILED DESCRIPTION

[0020] In the following description, specific details are set forth to provide a thorough understanding of various aspects of the disclosure. However, persons having ordinary skill in the art will appreciate that the various aspects can be practiced without these specific details. For example, circuits can be shown in block diagrams in order to avoid obscuring aspects of the present disclosure. In other instances, well-known circuits, structures, and techniques have not been shown in order to avoid obscuring aspects of the present disclosure.

[0021] The present disclosure describes a substrate comprising: a core layer; at least one first dielectric layer (e.g., a first prepreg layer) over a first surface of the core layer; at least one second dielectric layer (e.g., a second prepreg layer) over a second surface of the core layer; a plurality of first interconnects (e.g., high density pad interconnects) over a surface of the at least one first dielectric layer; a plurality of second interconnects over the surface of the at least one first dielectric layer; a plurality of third interconnects (e.g., high density trace interconnects) over the surface of the at least one first dielectric layer; and a solder resist layer over a surface of the at least one second dielectric layer. The plurality of third interconnects are coupled to the plurality of first interconnects. The plurality of third interconnects and the plurality of second interconnects are coplanar with the plurality of first interconnects. The solder resist layer comprises a first portion, a second portion, and a third portion. The first portion of the solder resist layer contacting the plurality of first interconnects comprises a first thickness that is less than a thickness of the plurality of first interconnects. The second portion of the solder resist layer contacting the plurality of second interconnects comprises a second thickness that is greater than a thickness of the plurality of second interconnects. The third portion of the solder resist layer is over a top surface and a side surface of the plurality of third interconnects. An integrated device can be coupled to the plurality of high density interconnects and the plurality of interconnects of the substrate through the plurality of column interconnects and / or the plurality of solder interconnects. As will be further described below, the substrate provides a low cost high reliability substrate with low shorting risk in the escape portion of the substrate. Further, a shorter manufacturing process for the substrate is provided that can reduce the cost of the substrate.

[0022] Exemplary package including a substrate comprising high density interconnects embedded in a solder resist layer

[0023] Figure 2 A cross-sectional view of a package 200 including an integrated device and a substrate comprising high density interconnects embedded in a solder resist layer is illustrated. The package 200 includes a substrate 202, an integrated device 204. The integrated device 204 is coupled to a first surface (e.g., a top surface) of the substrate 202 through a plurality of column interconnects 290 and / or a plurality of solder interconnects 280. The plurality of column interconnects 290 includes a plurality of column interconnects 290a and a plurality of column interconnects 290b. The plurality of solder interconnects 280 includes a plurality of solder interconnects 280a and a plurality of solder interconnects 280b.

[0024] As Figure 2As shown in the middle, the substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a solder resist layer 250, and a solder resist layer 260. The solder resist layer 250 can be located on a first surface (e.g., a top surface) of the substrate 202. The solder resist layer 260 can be located on a second surface (e.g., a bottom surface) of the substrate 202. Some of the plurality of interconnects 222 can be located in the at least one dielectric layer 220. Some of the plurality of interconnects 222 can be located on one or more surfaces of the at least one dielectric layer 220. The plurality of interconnects 222 can include a plurality of high-density interconnects 222a (e.g., a plurality of first interconnects), a plurality of interconnects 222b (e.g., a plurality of second interconnects), a plurality of high-density interconnects 222c, and a plurality of interconnects 222d. Some of the plurality of interconnects 222 can be embedded in the solder resist layer 250 and / or the solder resist layer 260. The plurality of high-density interconnects 222a, the plurality of interconnects 222b, and the plurality of high-density interconnects 222c can be coplanar with each other. For example, the plurality of high-density interconnects 222a and the plurality of high-density interconnects 222c can be located on the same metal layer of the substrate 202 as the plurality of interconnects 222b. The plurality of high-density interconnects 222a, the plurality of high-density interconnects 222c, and the plurality of interconnects 222b are embedded in the solder resist layer 250. The substrate 202 can include an escape portion 224 (e.g., an integrated escape portion) and a non-escape portion 226. The plurality of high-density interconnects 222a (e.g., high-density pad interconnects) and the plurality of high-density interconnects 222c (e.g., high-density trace interconnects) can be located in the escape portion 224 of the substrate 202. The plurality of high-density interconnects 222a can be coupled to the plurality of high-density interconnects 222c. The plurality of high-density interconnects 222a can be configured to be electrically coupled to the plurality of high-density interconnects 222c. The escape portion 224 of the substrate 202 is a portion of the substrate 202 that includes interconnects (e.g., pad interconnects) configured to be electrically coupled to solder interconnects of an integrated device. At least in Figure 4 and Figure 5The escape portions are further illustrated and described. The plurality of high-density interconnects 222a can be partially embedded in the solder resist layer 250. The plurality of high-density interconnects 222c can be fully embedded in the solder resist layer 250. The solder resist layer 250 can have different portions of different thicknesses. The solder resist layer 250 can include a solder resist layer portion 250a (e.g., a first portion), a solder resist layer portion 250b (e.g., a second portion), a solder resist layer portion 250c (e.g., a third portion), and a solder resist layer portion 250d. The solder resist layer portion 250a can be partially embedded in the plurality of high-density interconnects 222a. However, the top surfaces of the plurality of high-density interconnects 222a can be free of the solder resist layer. In some implementations, a portion of the side surfaces of the plurality of high-density interconnects 222a can be covered by the solder resist layer. In some implementations, the plurality of high-density interconnects 222a can not directly contact the solder resist layer. In such cases, the solder resist layer portion 250a can not exist and the solder resist layer portion 250a can be considered to have a thickness of zero. The solder resist layer portion 250b can be partially embedded in the plurality of interconnects 222b. A portion of the top surfaces of the plurality of interconnects 222b can be free of the solder resist layer and another portion of the top surfaces of the plurality of interconnects 222b can be covered by the solder resist layer (e.g., the solder resist layer portion 250b). The solder resist layer portion 250c can be fully embedded in the plurality of interconnects 222c. For example, the top surfaces and the side surfaces of the plurality of high-density interconnects 222c can be covered by the solder resist layer (e.g., the solder resist layer portion 250c). The thickness of the solder resist layer portion 250a can be less than the thickness of the solder resist layer portion 250b, the thickness of the solder resist layer portion 250c, and the thickness of the solder resist layer portion 250d.

[0025] In some implementations, the plurality of high-density interconnects 222a and the plurality of high-density interconnects 222c can have a lower minimum width and / or a lower minimum spacing than the minimum width and / or the minimum spacing of the plurality of interconnects 222b and / or the plurality of interconnects 222d. For example, the plurality of high-density interconnects 222a and the plurality of high-density interconnects 222c can include interconnects having (i) a minimum width of 8 microns and (ii) a minimum spacing of 10 microns, and the plurality of interconnects 222b and the plurality of interconnects 222d can include interconnects having (i) a minimum width of 20 microns and (ii) a minimum spacing of 25 microns. An interconnect that is not a high-density interconnect can be a low-density interconnect having a lower minimum width and / or a lower minimum spacing than the minimum width and / or the minimum spacing of the high-density interconnect.

[0026] As mentioned above, the integrated device 204 is coupled to the first surface (e.g., top surface) of the substrate 202 by a plurality of column interconnects 290 and / or a plurality of solder interconnects 280. The plurality of column interconnects 290a are coupled to the plurality of solder interconnects 280a. The plurality of solder interconnects 280a are coupled to the plurality of high density interconnects 222a. The plurality of column interconnects 290b are coupled to the plurality of solder interconnects 280b. The plurality of solder interconnects 280b are coupled to the plurality of interconnects 222b.

[0027] The plurality of high density interconnects 222a and / or the plurality of high density interconnects 222c can be examples of components for high density interconnects. The plurality of interconnects 222b and / or the plurality of interconnects 222d can be examples of components for interconnects.

[0028] Figure 3 A package 300 including a substrate 302 and an integrated device 204 is illustrated. The package 300 can be similar to the package 200 and, thus, can include similar components and / or be arranged in a similar manner as described for the package 200. The substrate 302 can be similar to the substrate 202 and, thus, can include similar components and / or be arranged in a similar manner as described for the substrate 202. The integrated device 204 is coupled to a first surface (e.g., top surface) of the substrate 302 by a plurality of column interconnects 290 and / or a plurality of solder interconnects 280.

[0029] The substrate 302 can be a laminate substrate including a core layer. The substrate 302 includes a core layer 320, at least one first dielectric layer (e.g., 322, 324), at least one second dielectric layer (e.g., 326, 328), a solder resist layer 250, a solder resist layer 260, a plurality of core interconnects 321, a plurality of interconnects 325, and a plurality of interconnects 327. The plurality of solder interconnects 280 can be coupled to the substrate 302 by the plurality of interconnects 325.

[0030] The core layer 320 can include fiberglass with resin or glass. However, the core layer 320 can include different materials. The dielectric layers 322, 324, 326, and / or 328 can each include a prepreg (e.g., prepreg layer). The dielectric layers 322, 324, 326, and / or 328 can be build-up layers. The dielectric layers 322, 324, 326, and / or 328 can include different materials than the core layer 320. As will be further described below, different implementations can have different numbers of dielectric layers and / or different numbers of metal layers. Figure 3 A substrate including 6 metal layers (e.g., Ml, M2, M3, M4, M4, M5, M6) is illustrated. However, the substrate can include more or fewer metal layers and / or more or fewer dielectric layers. For example, the substrate can include 10 metal layers.

[0031] Some of the plurality of interconnects 325 can be located in the dielectric layers 322 and / or 324. Some of the plurality of interconnects 325 can be located on a surface of the dielectric layer 324. The plurality of interconnects 325 includes a plurality of high-density interconnects 325a (e.g., a plurality of first interconnects, a plurality of pad interconnects), a plurality of interconnects 325b (e.g., a plurality of second interconnects), a plurality of high-density interconnects 325c (e.g., a plurality of third interconnects, a plurality of high-density trace interconnects), and a plurality of interconnects 325d. The core layer 320 includes a first surface and a second surface. At least one first dielectric layer (e.g., 322, 324) is located on the first surface of the core layer 320. At least one second dielectric layer (e.g., 326, 328) is located on the second surface of the core layer 320. The plurality of high-density interconnects 325a and the plurality of high-density interconnects 325c are located on a surface of the at least one first dielectric layer 324. The plurality of interconnects 325b and the plurality of interconnects 325d are located on a surface of the at least one first dielectric layer 324. The soldermask layer 250 is located on a surface of the at least one first dielectric layer 324. The plurality of high-density interconnects 325a, the plurality of interconnects 325b, the plurality of high-density interconnects 325c, and the plurality of interconnects 325d are coplanar with each other. The plurality of high-density interconnects 325a, the plurality of interconnects 325b, the plurality of high-density interconnects 325c, and the plurality of interconnects 325d can be located on a same metal layer (e.g., Ml) of the substrate 302. The soldermask layer 250 includes a first thickness and a second thickness.

[0032] The substrate 302 can include an escape portion 224 (e.g., an integrated escape portion) and a non-escape portion 226. The plurality of high-density interconnects 325a (e.g., pad interconnects) and the plurality of high-density interconnects 325c (e.g., trace interconnects) can be located in the escape portion 224 of the substrate 302. The escape portion 224 of the substrate 302 is a portion of the substrate 302 that includes interconnects (e.g., pad interconnects) configured to be electrically coupled to solder interconnects of an integrated device. The plurality of high-density interconnects 325a can be coupled to the plurality of high-density interconnects 325c. The plurality of high-density interconnects 325a (e.g., high-density pad interconnects) can be configured to be electrically coupled to the plurality of high-density interconnects 325c (e.g., high-density trace interconnects).

[0033] Soldermask portion 250a and soldermask portion 250c can be located in escape portion 224 of substrate 302. Soldermask portion 250a can partially embed plurality of high-density interconnects 325a. However, a top surface of plurality of high-density interconnects 325a can be free of soldermask. In some implementations, a portion of a side surface of plurality of high-density interconnects 325a can be covered by soldermask. In some implementations, plurality of high-density interconnects 325a can not be in direct contact with soldermask. In such cases, soldermask portion 250a can not exist, and soldermask portion 250a can be considered to have a zero thickness. Soldermask portion 250b can partially embed plurality of interconnects 325b. A portion of a top surface of plurality of interconnects 325b can be free of soldermask and another portion of a top surface of plurality of interconnects 325b can be covered by soldermask (e.g., soldermask portion 250b). Soldermask portion 250c can fully embed plurality of interconnects 325c. A top surface and a side surface of plurality of high-density interconnects 325c can be covered by soldermask (e.g., soldermask portion 250c). A thickness of soldermask portion 250a can be less than a thickness of soldermask portion 250b, a thickness of soldermask portion 250c, and / or a thickness of soldermask portion 250d.

[0034] In some implementations, plurality of high-density interconnects 325a and plurality of high-density interconnects 325c can have a lower minimum width and / or minimum spacing than a minimum width and / or minimum spacing of plurality of interconnects 325b and / or plurality of interconnects 325d. For example, plurality of high-density interconnects 325a and plurality of high-density interconnects 325c can include interconnects having (i) a minimum width of 8 microns and (ii) a minimum spacing of 10 microns, and plurality of interconnects 325b and plurality of interconnects 325d can include interconnects having (i) a minimum width of 20 microns and (ii) a minimum spacing of 25 microns. Interconnects that are not high-density interconnects can be low-density interconnects having a lower minimum width and / or minimum spacing than a minimum width and / or minimum spacing of high-density interconnects.

[0035] As described above, integrated device 204 is coupled to a first surface (e.g., a top surface) of substrate 202 by plurality of column interconnects 290 and / or plurality of solder interconnects 280. Plurality of column interconnects 290a is coupled to plurality of solder interconnects 280a. Plurality of solder interconnects 280a is coupled to plurality of high-density interconnects 325a. Plurality of column interconnects 290b is coupled to plurality of solder interconnects 280b. Plurality of solder interconnects 280b is coupled to plurality of interconnects 325b. Plurality of solder interconnects 270 is coupled to plurality of interconnects 327d.

[0036] The plurality of high-density interconnects 325a and / or the plurality of high-density interconnects 325c can be examples of components for high-density interconnects. The plurality of interconnects 325b and / or the plurality of interconnects 325d can be examples of components for interconnects. The plurality of solder interconnects 280 can be examples of components for solder interconnects. The plurality of post interconnects 290 can be examples of components for post interconnects.

[0037] Figure 4 A plan view of an AA cross-section of the substrate 302 is illustrated. As Figure 4 The substrate 302 includes a solder mask layer 250 including a solder mask layer portion 250a, a solder mask layer portion 250b, a solder mask layer portion 250c, a solder mask layer portion 250d, a plurality of high-density interconnects 325a, a plurality of interconnects 325b, a plurality of high-density interconnects 325c, and a plurality of interconnects 325d, as shown in FIG. 3B. The plurality of high-density interconnects 325a, the plurality of high-density interconnects 325c, the solder mask layer portion 250a, and the solder mask layer portion 250c are located in an escape portion 224 of the substrate 302. The escape portion 224 of the substrate 302 can be defined as a portion configured to be located on top of or underneath a portion of an integrated device coupled to the substrate 302 (e.g., near a peripheral portion). The plurality of interconnects 325b and the solder mask layer portion 250b are located in a non-escape portion 226 of the substrate 302. The non-escape portion 226 can be configured to be located on top of or underneath an integrated device coupled to the substrate 302. The escape portion 224 can laterally surround the non-escape portion 226. The integrated device 204 can vertically overlap the escape portion 224 and the non-escape portion 226 of the substrate 302 when coupled to the substrate 302. The substrate 302 can also include a portion 426. The portion 426 can include the plurality of interconnects 325d and the solder mask layer portion 250d. The portion 426 is a portion of the substrate that does not vertically overlap the integrated device 204. The escape portion 224 can be located between the portion 426 and the non-escape portion 226. The portion 426 includes interconnects having a higher minimum width and / or a higher minimum spacing than a minimum width and / or a minimum spacing of the interconnects of the escape portion 224. The portion 426 includes interconnects having a minimum width and / or a minimum spacing equal to and / or higher than a minimum width and / or a minimum spacing of the non-escape portion 226.

[0038] Figure 5 A plan view of a BB cross-section of the substrate 302 is illustrated. As Figure 5As shown in FIG. 3, the substrate 302 includes a solder mask layer 250 including a solder mask layer portion 250a, a solder mask layer portion 250b, a solder mask layer portion 250c, a solder mask layer portion 250d, a plurality of solder interconnects 280a, and a plurality of solder interconnects 280b. The plurality of solder interconnects 280a can be coupled to the plurality of high-density interconnects 325a. The plurality of solder interconnects 280a can be located in a void of the solder mask layer 250. A void can be at least one region that is free of solid material. The void can include a cavity. The void can be occupied by a gas (e.g., air). The plurality of solder interconnects 280b can be coupled to the plurality of interconnects 325b. Figure 4 and Figure 5 in combination illustrate how the integrated device is configured to be electrically coupled to the post interconnect 290 and the solder interconnect 280 through the escape portion 224. Note that, Figure 4 and Figure 5 are not limited to being applicable to Figure 3 . Figure 4 and Figure 5 may also be applicable to Figure 6 . That is, Figure 4 and Figure 5 the planar cross-sections shown in Figure 6 . That is,

[0039] Figure 6 FIG. 6 illustrates a cross-sectional view of a package 600 including a substrate including high-density interconnects embedded in a solder mask layer. The package 600 is similar to the package 300 of Figure 3 and thus includes the same or similar components as described for the package 300. The package 600 includes a substrate 602 and an integrated device 204. The substrate 602 is similar to the substrate 302 and thus includes similar components as described for the substrate 302. The substrate 602 includes a plurality of high-density interconnects 325a that are partially embedded in a solder mask layer 250. The substrate 602 includes a plurality of high-density interconnects 325a that do not directly contact the solder mask layer (e.g., 250). For example, the top surface and side surfaces of the plurality of high-density interconnects 325a are not covered by the solder mask layer.

[0040] In some implementations, the plurality of high-density interconnects (e.g., 325a) can have a surface roughness that is lower than the plurality of interconnects (e.g., 325b). In some implementations, the plurality of interconnects (e.g., 325b) can have a surface roughness that is higher than the plurality of high-density interconnects (e.g., 325a). For example, the plurality of high-density interconnects (e.g., 325a) can include a surface roughness in the range of about 0.2 to 0.5 microns, and the plurality of interconnects (e.g., 325b) can include a surface roughness in the range of about 0.6 to 0.8 microns. The difference in surface roughness can be due to the sandblasting performed on the portion of the substrate.

[0041] The term “high-density interconnect(s)” can mean that the interconnect(s) have a lower minimum line (e.g., width), minimum spacing, and / or minimum pitch than the minimum line (e.g., width), minimum spacing, and / or minimum pitch of interconnects (e.g., core interconnects) in other portions of the substrate. The plurality of high-density interconnects (e.g., 222a, 325a) can be components for high-density interconnects. The plurality of interconnects (e.g., 222b, 325b) can be components for interconnects.

[0042] The integrated device (e.g., 204) can include a die (e.g., a semiconductor die). The integrated device can include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a GaAs-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a processor, a memory, and / or a combination thereof. The integrated device (e.g., 204) can include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0043] The package (e.g., 200, 300, 600) can be implemented in a radio frequency (RF) package. The RF package can be a radio frequency front end package (RFFE). The package (e.g., 200, 300, 600) can be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 200, 300, 600) can be configured to support global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 200, 300, 600) can be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0044] Having described various substrates including various high-density interconnects, an order for fabricating a substrate including high-density interconnects embedded in a solder resist layer will now be described below. As shown in the following, the substrates described in the present disclosure provide a low-cost substrate, a high-reliability substrate, with a low short risk in the escape area. In addition, a shorter fabrication process can be used to fabricate the substrate.

[0045] An exemplary order for fabricating a substrate including high-density interconnects embedded in a solder resist layer

[0046] Figures 7A-7E An exemplary order for providing or fabricating a substrate including high-density interconnects embedded in a solder resist layer is illustrated. In some implementations, Figures 7A-7EThe order of the stages can be used to provide or manufacture a substrate 302, or any substrate described in the present disclosure (e.g., 202, 602). Figure 3 The order of the stages can be combined one or more stages in order to simplify and / or clarify the order for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure. Different implementations can manufacture a substrate differently.

[0047] It should be noted that, Figures 7A-7E The order of the stages can be combined one or more stages in order to simplify and / or clarify the order for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure. Different implementations can manufacture a substrate differently.

[0048] As shown in FIG. 1A, stage 1 illustrates a state after providing a core layer 320. The core layer 320 can include glass fibers or glass with resin. However, the core layer 320 can include different materials. The core layer 320 can have different thicknesses. Figure 7A Stage 2 illustrates a state after forming a plurality of cavities 710 in the core layer 320. The plurality of cavities 710 can be formed by a laser process and / or a drilling process. The plurality of cavities 710 can pass through the core layer 320.

[0049] Stage 3 illustrates a state after forming a first plurality of core interconnects 321 in the plurality of cavities 710. For example, the first plurality of core interconnects 321 can be formed in the plurality of cavities 710. A plating process can be used to form the first plurality of core interconnects 321. However, different implementations can use different processes to form the first plurality of core interconnects 321. The first plurality of core interconnects 321 can include core vias located in the core layer 320.

[0050] Stage 4 illustrates a state after forming a plurality of interconnects 762 over a first surface (e.g., a top surface) of the core layer 320. The plurality of interconnects 762 can be coupled to the first plurality of core interconnects 321. Stage 4 also illustrates a state after forming a plurality of interconnects 764 over a second surface (e.g., a bottom surface) of the core layer 320. The plurality of interconnects 764 can be coupled to the first plurality of core interconnects 321. A patterning process, a lift-off process, and / or a plating process can be used to form the plurality of interconnects 762 and the plurality of interconnects 764.

[0051] As shown in FIG. 1B, stage 5 illustrates a state after forming a dielectric layer 322 over the first surface of the core layer 320 and a dielectric layer 326 over the second surface of the core layer 320. A deposition process and / or a lamination process can be used to form the dielectric layers 322 and 326. The dielectric layers 322 and 326 can include prepreg (e.g., prepreg layers).

[0052] Figure 7B Stage 6 illustrates a state after forming a plurality of interconnects 762 over the dielectric layer 322 and a plurality of interconnects 764 over the dielectric layer 326. The plurality of interconnects 762 and the plurality of interconnects 764 can be coupled to the first plurality of core interconnects 321. A patterning process, a lift-off process, and / or a plating process can be used to form the plurality of interconnects 762 and the plurality of interconnects 764.

[0053] ​Stage 6 illustrates a state after forming a plurality of cavities 770 in the dielectric layer 322 and a plurality of cavities 771 in the dielectric layer 326. The plurality of cavities 770 and the plurality of cavities 771 can be formed using a laser process (e.g., laser drilling, laser ablation).

[0054] Stage 7 illustrates a state after forming a plurality of interconnects 772 over and coupled to the dielectric layer 322 and the plurality of cavities 770. The plurality of interconnects 772 can be coupled to the plurality of interconnects 762. Stage 7 also illustrates a state after forming a plurality of interconnects 774 over and coupled to the dielectric layer 326 and the plurality of cavities 771. The plurality of interconnects 774 can be coupled to the plurality of interconnects 764. The plurality of interconnects 772 and the plurality of interconnects 774 can be formed using a patterning process, a lift-off process, and / or a plating process.

[0055] As shown in Figure 7C Stage 8 illustrates a state after forming a dielectric layer 324 over and coupled to a first surface of the dielectric layer 322, and forming a dielectric layer 328 over and coupled to a second surface of the dielectric layer 326. A deposition process and / or a lamination process can be used to form the dielectric layers 324 and 328. The dielectric layers 324 and 328 can include a prepreg (e.g., a prepreg layer).

[0056] Stage 9 illustrates a state after forming a plurality of cavities 780 in the dielectric layer 324 and a plurality of cavities 781 in the dielectric layer 328. A laser process (e.g., laser drilling, laser ablation) can be used to form the plurality of cavities 780 and the plurality of cavities 781.

[0057] As shown in Figure 7D Stage 10 illustrates a state after forming a plurality of interconnects 782 over and coupled to the dielectric layer 324 and the plurality of cavities 780. The plurality of interconnects 782 can be coupled to the plurality of interconnects 772. Stage 10 also illustrates a state after forming a plurality of interconnects 784 over and coupled to the dielectric layer 328 and the plurality of cavities 781. The plurality of interconnects 784 can be coupled to the plurality of interconnects 774. The plurality of interconnects 782 and the plurality of interconnects 784 can be formed using a patterning process, a lift-off process, and / or a plating process. It should be noted that additional dielectric layers and additional interconnects can be formed by repeating stages 8-10 as described above. The plurality of interconnects 782 can represent the plurality of interconnects 325. Figures 7C-7D ​

[0058] Stage 11 illustrates a state after (i) a solder resist layer 250 is formed over the dielectric layer 324 and the plurality of interconnects 782, and (ii) a solder resist layer 260 is formed over the dielectric layer 328 and the plurality of interconnects 784. The solder resist layer 250 and the solder resist layer 260 can use a deposition process.

[0059] As shown in Stage 12, a dry film 720 is formed over the solder resist layer 250 after the solder resist layer 250 is formed. Figure 7E

[0060] Stage 13 illustrates a state after the exposed portions of the solder resist layer 250 are partially removed. For example, as shown in Stage 13, portions of the solder resist layer 250 can be removed such that the remaining thickness of the solder resist layer 250 is less than the thickness of the high density interconnects 325a. In some implementations, some portions of the solder resist layer 250 can have a lower thickness than the thickness of the plurality of high density interconnects 325a. A sandblasting process can be used to remove portions of the solder resist layer 250. Removing portions of the solder resist layer 250 can include thinning portions and / or removing portions of the solder resist layer 250 in the escape portions 224 of the substrate 302. One effect of the sandblasting process is that the surfaces of the plurality of high density interconnects 325a have a lower surface roughness than the surfaces of the plurality of interconnects 325b. Stage 13 can illustrate the substrate 302 including the plurality of high density interconnects 325a, the plurality of high density interconnects 325c, and the plurality of interconnects 325b.

[0061] Exemplary flowchart of a method for manufacturing a substrate including high density interconnects embedded in a solder resist layer

[0062] In some implementations, manufacturing a substrate includes several processes. Figure 8 An exemplary flowchart of a method 800 for providing or manufacturing a substrate is illustrated. In some implementations, the method 800 can be used to provide or manufacture a substrate as described in Figure 8 The method 800 can be used to provide or manufacture a substrate as described in Figure 3 For example, the method can be used to manufacture the substrate 302. However, the method can be used to manufacture any substrate in the present disclosure, such as the substrate 302a and the substrate 302b. Figure 8 The method can be used to manufacture the substrate 302. However, the method can be used to manufacture any substrate in the present disclosure, such as the substrate 302a and the substrate 302b. Figure 8 The method can be used to manufacture the substrate 302. However, the method can be used to manufacture any substrate in the present disclosure, such as the substrate 302a and the substrate 302b. Figure 2 The method can be used to manufacture the substrate 302. However, the method can be used to manufacture any substrate in the present disclosure, such as the substrate 302a and the substrate 302b. Figure 6 The method can be used to manufacture the substrate 302. However, the method can be used to manufacture any substrate in the present disclosure, such as the substrate 302a and the substrate 302b.

[0063] It should be noted that the method can incorporate one or more processes in order to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified. Figure 8 The method can be used to manufacture the substrate 302. However, the method can be used to manufacture any substrate in the present disclosure, such as the substrate 302a and the substrate 302b.

[0064] ​The method provides (at 805) a core layer (e.g., 320). The core layer 320 can include glass fibers or glass with resin. However, the core layer 320 can include different materials. The core layer 320 can have different thicknesses. Figure 7A Stage 1 of FIG. 1 illustrates and describes an example of a core layer provided.

[0065] The method forms (at 810) a plurality of cavities (e.g., 710) in the core layer. A laser process or a drilling process can be used to form the cavities. The plurality of cavities can run through the core layer 320. Figure 7A Stage 2 of FIG. 1 illustrates and describes an example of forming cavities in a core layer.

[0066] The method forms (at 815) a plurality of core interconnects (e.g., 321) in the plurality of cavities (e.g., 710). For example, a first plurality of core interconnects 321 can be formed in the plurality of cavities 710. A plating process can be used to form the first plurality of core interconnects 321. However, different implementations can use different processes to form the first plurality of core interconnects 321. The first plurality of core interconnects 321 can include core vias located in the core layer 320. Figure 7A Stage 3 of FIG. 1 illustrates and describes an example of core interconnects located in a core layer.

[0067] The method forms (at 820) a plurality of interconnects (e.g., 325, 327) and at least one dielectric layer (e.g., 322, 324) over a first surface of the core layer and a second surface of the core layer (e.g., 320). A patterning process, a lift-off process, and / or a plating process can be used to form the plurality of interconnects. A laser process (e.g., laser drilling, laser ablation) can be used to form a plurality of cavities in the dielectric layer. A deposition process and / or a lamination process can be used to form the at least one dielectric layer. The at least one dielectric layer can include a prepreg (e.g., a prepreg layer). Figures 7B-7D Stages 5 through Figure 10 of FIG. 1 illustrate and describe an example of forming a plurality of interconnects and at least one dielectric layer (e.g., a prepreg).

[0068] The method forms (at 825) at least one solder resist layer (e.g., 250) over a first surface of the dielectric layer and at least one solder resist layer (e.g., 260) over a second surface of the dielectric layer. A deposition process can be used to form the solder resist layer 250 and the solder resist layer 260. Figure 7D Stage 11 of FIG. 1 illustrates and describes an example of forming a solder resist layer over a dielectric layer.

[0069] This method (at 830) removes a portion (e.g., 250) of the solder mask layer. Removing a portion of the solder mask layer may include thinning a portion of the solder mask layer. In some implementations, some portions of the solder mask layer 250 may have a thickness lower than the thickness of the plurality of high-density interconnects 325a. In some implementations, some portions of the solder mask layer 250 may have a thickness equal to the thickness of the plurality of high-density interconnects 325a. Different implementations may use different processes to remove portions of the solder mask layer. A sandblasting process may be used to remove portions of the solder mask layer 250. Removing portions of the solder mask layer 250 may include thinning a portion of the solder mask layer 250 in the escape portion 224 of the substrate 302. Removing portions of the solder mask layer may include applying a dry film and performing sandblasting on the exposed portions of the solder mask layer (e.g., without a dry film). After sandblasting, the dry film may be removed. One effect of the sandblasting process is that the surfaces of the plurality of high-density interconnects 327a have a lower surface roughness than the surfaces of the plurality of interconnects 327b. Figure 7E Stages 12 and 13 are illustrated and an example of removing the solder mask layer is described.

[0070] This method (at 835) can couple multiple solder interconnects (e.g., 270) to a substrate (e.g., 202, 302, 602). For example, a reflow soldering process can be used to couple multiple solder interconnects 270 to multiple interconnects 327 of substrate 202.

[0071] Exemplary sequence for manufacturing a package including a substrate containing high-density interconnects embedded in a solder resist layer.

[0072] Figure 9 The illustration depicts an exemplary sequence for providing or manufacturing a package comprising a substrate containing high-density interconnects embedded in a solder resist layer. In some implementations, Figure 9 The order can be used for supplying or manufacturing. Figure 6 The package 600, or any package described in this disclosure.

[0073] It should be noted that, Figure 9 The sequence of processes can be combined with one or more stages to simplify and / or clarify the sequence used to provide or manufacture the package. In some implementations, the sequence of processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. Different implementations can manufacture the package differently.

[0074] like Figure 9 As shown in Figure A, Stage 1 illustrates the state after substrate 602 has been provided. It can be used... Figures 7A-7EThe substrate 602 can be provided by the processes described in the

[0075] Stage 2 illustrates a state after the integrated device 204 is coupled to the substrate 602 by the plurality of pillar interconnects 290 and / or the plurality of solder interconnects 280. A pick and place process can be used to place the integrated device 204 over the first surface of the substrate 602. A reflow soldering process can be used to couple the integrated device 204 to the substrate 602. The integrated device 204 can be located over the non-escape portion 226 and the escape portion 224 of the substrate 604, as described above in Figure 3 and Figure 6 .

[0076] Exemplary Electronic Devices

[0077] Figure 10 Various electronic devices are illustrated, which can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-a-package (SiP), or system-on-a-chip (SoC). For example, a mobile phone device 1002, a laptop computer device 1004, a fixed location terminal device 1006, a wearable device 1008, or an automotive vehicle 1010 can include a device 1000 as described herein. The device 1000 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Figure 10 The devices 1002, 1004, 1006, and 1008, and the vehicle 1010 shown in are exemplary only. Other electronic devices can also feature the device 1000, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in an automotive vehicle (e.g., an autonomous vehicle), or any other device, or any combination thereof.

[0078] Figures 2-6 , Figures 7A-7E and / or Figures 9-10One or more components, processes, features and / or functions illustrated in the figures can be rearranged and / or combined into a single component, process, feature or function or embodied in several components, processes, or features. Additional elements, components, processes, and / or functions can also be added or made optional without departing from the disclosure. Also, it will be understood that Figures 2-6 , Figures 7A-7E and / or Figures 9-10 and their corresponding descriptions in the disclosure are not limited to dies and / or ICs. In some implementations, Figures 2-6 , Figures 7A-7E and / or Figures 9-10 and their corresponding descriptions can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the devices can include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package on package (PoP) devices, heat spreading devices, and / or interposers.

[0079] It should be noted that the figures in the disclosure can represent actual and / or conceptual representations of various portions, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures can not be drawn to scale. In some cases, not all components and / or components can be shown for the sake of clarity. In some cases, the position, location, size, and / or shape of various components and / or components in the figures can be exemplary. In some implementations, various components and / or components in the figures can be optional.

[0080] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” is not meant to limit the present disclosure to a certain number of aspects. The term “coupled” is used herein to refer to a direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically touches object B, and object B touches object C, then objects A and C can still be considered coupled to one another — even if they do not directly physically touch one another. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that electrical current (e.g., a signal, power, ground) can flow between the two objects. The two objects that are electrically coupled can or can not have electrical current flowing therebetween. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any fourth above) is arbitrary. Any of the components described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “encapsulate” means that the object can partially encapsulate or fully encapsulate another object. The terms “top” and “bottom” are arbitrary. A component that is on top of another component can be on top of a component that is on the bottom. A top component can be considered a bottom component and vice versa. As described in the present disclosure, a first component that is on top of a second component can mean that the first component is on top of or below the second component, depending on how top or bottom are arbitrarily defined. In another example, a first component can be on top of (e.g., on) a first surface of a second component, and a third component can be on top of (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that the term “on” used in the context of one component being on another component in the present application can be used to mean a component that is on and / or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is on a second component can mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on (e.g., on a surface of) the second component, and / or (3) the first component is in (e.g., embedded in) the second component. A first component that is in a second component can be partially in the second component or fully in the second component. The term “about ‘value X’” or “approximately value X” used in the present disclosure means within ten percent of ‘value X.’ For example, a value that is about 1 or approximately 1 can mean a value in the range of 0.9 to 1.1.

[0081] In some implementations, an interconnect is a device or an element or component of a package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect can include a trace, a via, a pad, a pillar, a redistribution metal layer, and / or an under bump metallization (UBM) layer. An interconnect can include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect is an electrically conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal, a ground, or a power supply). An interconnect can be part of a circuit. An interconnect can include more than one element or component. An interconnect can be defined by one or more interconnects. Different implementations can use similar or different processes to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form an interconnect. A sputtering process, a spray process, and / or a plating process can be used to form multiple interconnects.

[0082] It is also noted that the various disclosures contained herein can be described as a process that is depicted as a flowchart, flow diagram, structure diagram, or block diagram. Although the flowchart can describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations can be rearranged. A process is terminated when its operations are completed.

[0083] The various features of the present disclosure described herein can be implemented in different systems. It should be noted that the foregoing aspects of the present disclosure are merely examples and are not to be construed as limiting the present disclosure. The description of aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of apparatuses. Numerous replacements, modifications, and variations of the present teachings will be apparent to those skilled in the art.

Claims

1. A substrate comprising: a core layer comprising a first surface and a second surface; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; a plurality of first interconnects on a surface of the at least one first dielectric layer, wherein the plurality of first interconnects comprise a first surface roughness; a plurality of second interconnects on the surface of the at least one first dielectric layer, wherein the plurality of second interconnects comprise a second surface roughness that is greater than the first surface roughness; and a plurality of third interconnects on the same surface of the at least one first dielectric layer as the plurality of first interconnects, wherein the plurality of third interconnects are coupled to the plurality of first interconnects, and wherein the plurality of first interconnects and the plurality of third interconnects are in an integrated device escape portion of the substrate; wherein an interconnect of the plurality of first interconnects has a first minimum width and a first minimum spacing, an interconnect of the plurality of second interconnects has a second minimum width and a second minimum spacing, and the second minimum width is greater than the first minimum width, the second minimum spacing is greater than the first minimum spacing, or the second minimum width is greater than the first minimum width and the second minimum spacing is greater than the first minimum spacing; and a solder resist layer on the surface of the at least one first dielectric layer, the solder resist layer comprising a first portion, a second portion, and a third portion, wherein the first portion of the solder resist layer that contacts the plurality of first interconnects comprises a first thickness that is less than a thickness of the plurality of first interconnects, wherein the second portion of the solder resist layer that contacts the plurality of second interconnects comprises a second thickness that is greater than a thickness of the plurality of second interconnects, and wherein the third portion of the solder resist layer is on a top surface and a side surface of each of the plurality of third interconnects.

2. The substrate of claim 1, wherein the plurality of first interconnects comprise a plurality of pad interconnects, and wherein the plurality of third interconnects comprise a plurality of trace interconnects.

3. The substrate of claim 1, wherein the plurality of first interconnects comprise interconnects having a minimum width of 8 microns and a minimum spacing of 10 microns, wherein the plurality of second interconnects comprise interconnects having a minimum width of 20 microns and a minimum spacing of 25 microns, and wherein the plurality of third interconnects comprise interconnects having a minimum width of 8 microns and a minimum spacing of 10 microns.

4. The substrate of claim 1, wherein the first surface roughness is in a range of 0.2 microns - 0.5 microns, and wherein the second surface roughness is in a range of 0.6 microns - 0.8 microns.

5. The substrate of claim 1, wherein a side surface of the plurality of first interconnects is free of the solder resist layer. ​ 6. The substrate of claim 1, wherein a portion of a side surface of the plurality of first interconnects is free of the solder resist layer.

7. The substrate of claim 1, wherein the plurality of third interconnects are completely covered by the solder resist layer.

8. The substrate of claim 1, wherein the plurality of first interconnects, the plurality of second interconnects, and the plurality of third interconnects are on a same metal layer of the substrate.

9. A device comprising: an integrated device; and a substrate coupled to the integrated device, the substrate comprising: a core layer comprising a first surface and a second surface; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; a plurality of first interconnects on a surface of the at least one first dielectric layer, wherein the plurality of first interconnects comprise a first surface roughness; a plurality of second interconnects on the surface of the at least one first dielectric layer, wherein the plurality of second interconnects comprise a second surface roughness that is greater than the first surface roughness; and a plurality of third interconnects on the same surface of the at least one first dielectric layer as the plurality of first interconnects; wherein the plurality of third interconnects are coupled to the plurality of first interconnects, and wherein the plurality of first interconnects and the plurality of third interconnects are in an integrated device escape portion of the substrate, wherein the plurality of first interconnects comprise interconnects having a minimum width of 8 microns and a minimum spacing of 10 microns, wherein the plurality of second interconnects comprise interconnects having a minimum width of 20 microns and a minimum spacing of 25 microns, and wherein the plurality of third interconnects comprise interconnects having a minimum width of 8 microns and a minimum spacing of 10 microns; and a solder resist layer on the surface of the at least one first dielectric layer, the solder resist layer comprising a first portion, a second portion, and a third portion, wherein the first portion of the solder resist layer that contacts the plurality of first interconnects comprises a first thickness that is less than a thickness of the plurality of first interconnects, wherein the second portion of the solder resist layer that contacts the plurality of second interconnects comprises a second thickness that is greater than a thickness of the plurality of second interconnects, and wherein the third portion of the solder resist layer is on a top surface and a side surface of each of the plurality of third interconnects.

10. The device of claim 9, wherein the plurality of first interconnects comprise a plurality of pad interconnects, and wherein the plurality of third interconnects comprise a plurality of trace interconnects.

11. The device of claim 9, wherein a portion of a side surface of the plurality of first interconnects is free of the solder resist layer.

12. The device of claim 9, wherein the plurality of third interconnects are completely covered by the solder resist layer.

13. The device of claim 9, wherein the plurality of first interconnects, the plurality of second interconnects, and the plurality of third interconnects are on a same metal layer of the substrate.

14. The device of claim 9, wherein the device is selected from a group consisting of: an entertainment unit, a navigation device, a communications device, a mobile device, a fixed location terminal, a computer, a wearable device, an Internet of Things (IoT) device, and a device in an automotive vehicle.

15. The device of claim 9, wherein the device is selected from a group consisting of: a music player, a video player, a mobile phone, a smart phone, a personal digital assistant, a tablet computer, a laptop computer, a server.

16. A device comprising: an integrated device; and a substrate coupled to the integrated device, the substrate comprising: a core layer comprising a first surface and a second surface; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; a plurality of first interconnects located on a surface of the at least one first dielectric layer, wherein the plurality of first interconnects comprises a first surface roughness; a plurality of second interconnects located on the surface of the at least one first dielectric layer, wherein the plurality of second interconnects comprises a second surface roughness, the second surface roughness being greater than the first surface roughness; a plurality of third interconnects located on the same surface of the at least one first dielectric layer as the plurality of first interconnects, wherein the plurality of third interconnects are coupled to the plurality of first interconnects, wherein the plurality of first interconnects and the plurality of third interconnects are located in an integrated device escape portion of the substrate, and wherein an interconnect of the plurality of first interconnects has a first minimum width and a first minimum spacing, an interconnect of the plurality of second interconnects has a second minimum width and a second minimum spacing, and the second minimum width is greater than the first minimum width, the second minimum spacing is greater than the first minimum spacing, or the second minimum width is greater than the first minimum width and the second minimum spacing is greater than the first minimum spacing; a solder resist layer located on the surface of the at least one first dielectric layer, the solder resist layer comprising a first portion, a second portion, and a third portion, wherein the first portion of the solder resist layer contacting the plurality of first interconnects comprises a first thickness, the first thickness being less than a thickness of the plurality of first interconnects, wherein the second portion of the solder resist layer contacting the plurality of second interconnects comprises a second thickness, the second thickness being greater than a thickness of the plurality of second interconnects, wherein the third portion of the solder resist layer is located on a top surface and a side surface of each of the plurality of third interconnects, and wherein a portion of a side surface of the plurality of first interconnects is free of the solder resist layer.

17. The device of claim 16, wherein the plurality of first interconnects comprises a plurality of pad interconnects, and wherein the plurality of second interconnects comprises a plurality of trace interconnects. wherein the plurality of third interconnects includes a plurality of trace interconnects.

18. The device of claim 16, wherein the plurality of third interconnects is completely covered by the solder mask.

19. The device of claim 16, wherein the plurality of first interconnects, the plurality of second interconnects, and the plurality of third interconnects are on a same metal layer of the substrate.

20. The device of claim 16, wherein the device is selected from the group consisting of an entertainment unit, a navigation device, a communications device, a mobile device, a fixed location terminal, a computer, a wearable device, an Internet of Things (IoT) device, and a device in a motor vehicle.

21. The device of claim 16, wherein the device is selected from the group consisting of a music player, a video player, a mobile phone, a smart phone, a personal digital assistant, a tablet computer, a laptop computer, a server.

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