A structure for realizing high-voltage current detection

Abstract

The application discloses a structure for realizing high-voltage current detection, which is characterized by the connection of a main input pair and an auxiliary input pair with an output stage NMOS transistor, thereby avoiding the introduction of inherent imbalance due to the current of the detection circuit, reducing the precision of high-voltage current detection, and being beneficial to improving the precision of high-voltage current detection and reducing the number of high-voltage transistors used in the detection circuit.

Description

Technical Field

[0001] This invention relates to high-voltage current detection technology, and in particular to a structure for realizing high-voltage current detection. Background Technology

[0002] In high-voltage current detection schemes, current is typically converted into voltage using a sense resistor in the high-voltage path, and then the voltage is converted into current output using a common-gate operational amplifier. This requires a large number of resistors and high-voltage MOSFETs, resulting in a large chip area and poor accuracy. The detection circuit includes a resistor R1 between high-voltage node A and high-voltage node B. The detection current I1 flows from A through resistor R1 to B. The first PMOS transistor M1 and the second PMOS transistor M2 in the input pair, which share a common gate, connect their sources to A and B in a one-to-one manner through their respective resistors R2 with equal resistance values. The current flowing from A through R2 is I2. The source voltages of M1 and M2 are equal. The drains of the input pair M1 and M2 are grounded through the common-gate NMOS transistor. The drain of M2 is connected to the gate of the output current transistor PMOS. The drain of the output current transistor PMOS forms the output current I3. The source of the output current transistor PMOS is connected to the source of M1. Thus, we get: VA-VB=I2*R2-Im2*R2;Im1=Im2;VA-VB=(I2-Im1)*R2;I2-Im1=I3;(VA-VB) / R2=I3;I3=(I1-I2)R1 / R2. Im1 is the source current of M1, and Im2 is the source current of M2. As can be seen from the above, the formula for calculating the final output current includes a term I2, which is the current of the detection circuit. This introduces inherent offset, leading to reduced accuracy. This structure also has a large number of high-voltage MOSFETs and a large chip area. Summary of the Invention

[0003] This invention addresses the defects or deficiencies in existing technologies by providing a structure for high-voltage current detection.

[0004] The technical solution of the present invention is as follows:

[0005] A structure for high-voltage current detection is characterized by comprising a main input pair formed by a first PMOS transistor and a second PMOS transistor. The sources of the first and second PMOS transistors are interconnected and connected to a first current source. The gate of the first PMOS transistor is connected to a first voltage node on a high-voltage path, and the gate of the second PMOS transistor is connected to a second voltage node on the high-voltage path. The high-voltage current flows from the first voltage node through a first resistor to the second voltage node. The drain of the first PMOS transistor serves as a fourth voltage node, with its first path connected to the negative input terminal of an operational amplifier, its second path grounded through a second resistor, and its third path connected to an auxiliary input pair. The drain of the second PMOS transistor serves as a fifth voltage node, with its first path connected to the positive input terminal of the operational amplifier, its second path grounded through a fourth resistor, and its third path connected to the auxiliary input pair. The output terminal of the operational amplifier is connected to the gate of an output stage NMOS transistor. The source of the output stage NMOS transistor serves as a third voltage node, with its first path connected to the auxiliary input pair and its second path grounded through a third resistor. The drain of the output stage NMOS transistor forms the output terminal current.

[0006] The auxiliary input pair includes a third PMOS transistor and a fourth PMOS transistor. The sources of the third PMOS transistor and the fourth PMOS transistor are interconnected and connected to a second current source. The gate of the third PMOS transistor is connected to the third voltage node, the gate of the fourth PMOS transistor is grounded, the drain of the third PMOS transistor is connected to the fifth voltage node, and the drain of the fourth PMOS transistor is connected to the third voltage node.

[0007] The second resistor has the same resistance value as the fourth resistor.

[0008] The second current source has the same current value as the first current source.

[0009] Let the resistance of the first resistor be R1, the current flowing through R1 be I1, the resistance of the third resistor be R3, and the drain current flowing into the output stage NMOS transistor be Iout. Then Iout = I1 * R1 / R3, and thus the high voltage current I1 is determined.

[0010] Let the voltage at the first voltage node be VA, the voltage at the second voltage node be VB, and the voltage at the third voltage node be VC. Then VA - VB = VC.

[0011] The equivalent transconductance of the main input pair is equal to the equivalent transconductance of the auxiliary input pair.

[0012] Let the voltage at the fourth voltage node be VD and the voltage at the fifth voltage node be VE. When the circuit enters steady state, VD = VE.

[0013] The technical effects of this invention are as follows: This invention provides a structure for realizing high-voltage current detection. By setting the connection between the main input pair and the auxiliary input pair and the output stage NMOS transistor, it avoids the inherent offset introduced by the current setting of the detection circuit, which would reduce the accuracy of high-voltage current detection. This is beneficial to improving the accuracy of high-voltage current detection and reducing the number of high-voltage transistors used in the detection circuit. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the circuit principle of a structure for realizing high-voltage current detection according to the present invention.

[0015] The reference numerals in the attached diagram are listed below: I1 - Detected current or high-voltage current (or measured current; nodes A and B are both high-voltage nodes, I1 flows from A to B through resistor R1); Ib1~Ib2 - First current source to second current source (where the current values ​​of Ib1 and Ib2 are equal); Iout - Output current terminal or output current; M1~M4 - First PMOS transistor to fourth PMOS transistor (where M1 and M2 form the main input pair, and the transconductance of the main input pair is Gm). 1,2 M3 and M4 form an auxiliary input pair, and the transconductance of the auxiliary input pair is Gm. 3,4 M5 - the fifth NMOS transistor (i.e., the output stage NMOS transistor, and the operational amplifier is between M5 and the main input pair); R1 to R4 - the first to the fourth resistors (where the resistance values ​​of R2 and R4 are equal); A to E - the first to the fifth voltage nodes (where the relationship between the node voltages is: VA - VB = VC - GND, GND is the ground potential, i.e., VA - VB = VC). Detailed Implementation

[0016] The following is in conjunction with the attached diagram ( Figure 1 The present invention will be described below.

[0017] Figure 1 This is a schematic diagram of the circuit principle for implementing a high-voltage current detection structure according to the present invention. (Reference) Figure 1As shown, a structure for realizing high-voltage current detection includes a main input pair formed by a first PMOS transistor M1 and a second PMOS transistor M2. The sources of the first PMOS transistor M1 and the second PMOS transistor M2 are interconnected and connected to a first current source Ib1. The gate of the first PMOS transistor M1 is connected to a first voltage node A on the high-voltage path, and the gate of the second PMOS transistor M2 is connected to a second voltage node B on the high-voltage path. The high-voltage current flows from the first voltage node A through a first resistor R1 to the second voltage node B. The drain of the first PMOS transistor M1 serves as the first path of the fourth voltage node D, connected to the negative input of the operational amplifier. The input terminal is (-), the second path is grounded through the second resistor R2, the third path is connected to the auxiliary input pair, the drain of the second PMOS transistor M2 serves as the fifth voltage node E, the first path is connected to the positive input terminal (+) of the operational amplifier, the second path is grounded through the fourth resistor R4, the third path is connected to the auxiliary input pair, the output terminal of the operational amplifier is connected to the gate of the output stage NMOS transistor (i.e., the fifth NMOS transistor M5), the source of the output stage NMOS transistor serves as the third voltage node C, the first path is connected to the auxiliary input pair, the second path is grounded through the third resistor R3, and the drain of the output stage NMOS transistor forms the output current Iout.

[0018] The auxiliary input pair includes a third PMOS transistor M3 and a fourth PMOS transistor M4. The sources of the third PMOS transistor M3 and the fourth PMOS transistor M4 are interconnected and connected to a second current source Ib2. The gate of the third PMOS transistor M3 is connected to the third voltage node C, the gate of the fourth PMOS transistor M4 is grounded, the drain of the third PMOS transistor M3 is connected to the fifth voltage node E, and the drain of the fourth PMOS transistor M4 is connected to the fourth voltage node D. The second resistor R2 has the same resistance as the fourth resistor R4. The second current source Ib2 has the same current value as the first current source Ib1. Let the resistance of the first resistor be R1, the current flowing through R1 be I1, the resistance of the third resistor be R3, and the drain current flowing into the output stage NMOS transistor be Iout. Then Iout = I1 * R1 / R3, thereby determining the high voltage current I1. Let the voltage of the first voltage node be VA, the voltage of the second voltage node be VB, and the voltage of the third voltage node be VC. Then VA - VB = VC. The equivalent transconductance of the main input pair is equal to that of the auxiliary input pair. Let the voltage at the fourth voltage node be VD and the voltage at the fifth voltage node be VE. When the circuit reaches steady state, VD = VE.

[0019] like Figure 1As shown, compared to existing structures that use a low-voltage auxiliary operational amplifier to convert the voltage drop across a resistor into current, the high-voltage MOSFET and resistor values ​​are reduced, and the operating current does not affect the sense voltage value, achieving high-precision detection. This invention uses an auxiliary input pair to achieve current conversion. A and B are two high-voltage points. The detection current flows from point A to point B, passing through R1 and generating a voltage drop. Therefore, VA - VB = ΔV = I1 * R1. The current at M1 is less than that at M2, and the voltage at point D is lower than that at point E. At this point, the auxiliary operational amplifier output adjusts the gate of M5, increasing the voltage at point C. Consequently, the current at M3 decreases, and the voltage at point E decreases. Ultimately, the voltages at the two input terminals of the auxiliary operational amplifier are equal, and the circuit enters a steady state.

[0020] Since the source currents of the two input pairs are equal, either both Ib1 or both Ib2, then Im1 + Im2 = Im3 + Im4. And since the voltages at points D and E are equal, then Im1 + Im4 = Im2 + Im3. Therefore, Im2 = Im4, Im1 = Im3, and Im2 - Im1 = Im4 - Im3. Im2 - Im1 = Gm 1,2 *(VA-VB),Im4-Im3=Gm 3,4 *VC.

[0021] Gm 1,2 *(VA-VB)=Gm 3,4 *VC, because the source currents of the two input pairs are equal, i.e., Ib1 = Ib2, then the equivalent transconductance Gm 1,2 =Gm 3,4 Then VA-VB=VC, Iout=I1*R1 / R3.

[0022] The circuit structure of this invention can detect high-voltage current, and uses fewer high-voltage transistors, resulting in higher accuracy.

[0023] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A structure for realizing high-voltage current detection, characterized in that, The system includes a main input pair formed by a first PMOS transistor and a second PMOS transistor. The sources of the first and second PMOS transistors are interconnected and connected to a first current source. The gate of the first PMOS transistor is connected to a first voltage node on a high-voltage path, and the gate of the second PMOS transistor is connected to a second voltage node on the high-voltage path. The high-voltage current flows from the first voltage node through a first resistor to the second voltage node. The drain of the first PMOS transistor serves as a fourth voltage node, with its first path connected to the negative input terminal of the operational amplifier, its second path grounded through a second resistor, and its third path connected to the auxiliary input pair. The drain of the second PMOS transistor serves as a fifth voltage node, with its first path connected to the positive input terminal of the operational amplifier, its second path grounded through a fourth resistor, and its third path connected to the auxiliary input pair. The output terminal of the operational amplifier is connected to the gate of an output stage NMOS transistor. The source of the output stage NMOS transistor serves as a third voltage node, with its first path connected to the auxiliary input pair and its second path grounded through a third resistor. The drain of the output stage NMOS transistor forms the output terminal current. The auxiliary input pair includes a third PMOS transistor and a fourth PMOS transistor. The sources of the third PMOS transistor and the fourth PMOS transistor are interconnected and connected to a second current source. The gate of the third PMOS transistor is connected to the third voltage node, the gate of the fourth PMOS transistor is grounded, the drain of the third PMOS transistor is connected to the fifth voltage node, and the drain of the fourth PMOS transistor is connected to the fourth voltage node.

2. The structure for realizing high-voltage current detection according to claim 1, characterized in that, The second resistor has the same resistance value as the fourth resistor.

3. The structure for realizing high-voltage current detection according to claim 1, characterized in that, The second current source has the same current value as the first current source.

4. The structure for realizing high-voltage current detection according to claim 1, characterized in that, Let the resistance of the first resistor be R1, the current flowing through R1 be I1, the resistance of the third resistor be R3, and the drain current flowing into the output stage NMOS transistor be Iout. Then, Iout = I1. R1 / R3, thus determining the high-voltage current I1.

5. The structure for realizing high-voltage current detection according to claim 1, characterized in that, Let the voltage at the first voltage node be VA, the voltage at the second voltage node be VB, and the voltage at the third voltage node be VC, then VA - VB = VC.

6. The structure for realizing high-voltage current detection according to claim 1, characterized in that, The equivalent transconductance of the main input pair is equal to the equivalent transconductance of the auxiliary input pair.

7. The structure for realizing high-voltage current detection according to claim 1, characterized in that, Let the voltage at the fourth voltage node be VD and the voltage at the fifth voltage node be VE. When the circuit reaches steady state, VD = VE.

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