Identification system and its static random access memory cell

Abstract

The present invention is an identification system and a static random access memory unit thereof. The static random access memory unit includes a first inverter and a second inverter that are cross-coupled; a first access transistor controlled by a word line to access the output of the first inverter; a second access transistor controlled by the word line to access the output of the second inverter; a first pass transistor controlled by the output of the first inverter to allow a common-mode voltage to pass; a second pass transistor controlled by the output of the second inverter to allow an input signal to pass; and a capacitor that switches the coupling between the common-mode voltage and the input signal via the first pass transistor and the second pass transistor, respectively. The present invention has the advantages of low power consumption and / or increased bandwidth.

Description

Technical Field

[0001] The present invention relates to recognition technology, and more particularly to a recognition system using a neural network. Background Art

[0002] Voice activity detection (VAD) can be used to detect or recognize human speech. VAD can trigger voice-based applications, such as Apple's Siri (Speech Interpretation and Recognition Interface) virtual assistant. VAD is a front-end device that is typically always-on and low-power.

[0003] Modern computer architecture, proposed by John von Neumann in 1945, suffers from the von Neumann bottleneck caused by the shared bus between program and data memory. Because a single bus can only access either program or data memory at a time, processing power is far lower than the CPU's operating speed. When the CPU is asked to process large amounts of data, this severely limits its effective processing speed. The CPU is constantly forced to wait for the required data to be moved to or from memory.

[0004] Computing-in-Memory (CIM) is a technology that integrates computing and memory. Embedding computation in memory reduces data movement, resulting in more efficient energy use, and massively parallel operations conserves bandwidth. CIM facilitates edge computing, a distributed computing approach that stores computation and data close to the data source. This approach can be applied to machine learning in the Internet of Things (IoT).

[0005] Therefore, there is an urgent need to propose a novel mechanism to improve the performance of low-power and / or high-bandwidth systems (such as speech recognition systems). Summary of the Invention

[0006] In view of the above, one of the objectives of the embodiments of the present invention is to provide an identification system including a static random access memory (SRAM) cell, which uses the charge redistribution principle to generate an accumulated signal with low power consumption and / or improved bandwidth.

[0007] The present invention is a static random access memory cell, comprising: a first inverter connected between ground and a power supply; a second inverter connected between the ground and the power supply, the first inverter and the second inverter being cross-coupled; a first access transistor controlled by a word line to access the output of the first inverter, which is transmitted via a first bit line; a second access transistor controlled by the word line to access the output of the second inverter, which is transmitted via a second bit line; a first pass transistor controlled by the output of the first inverter to allow a common-mode voltage to pass; a second pass transistor controlled by the output of the second inverter to allow an input signal to pass; and a capacitor, switchingly coupling the common-mode voltage and the input signal via the first pass transistor and the second pass transistor, respectively.

[0008] Preferably, the device further comprises a switch for switching the capacitor to be connected to the outputs of the first pass transistor and the second pass transistor, wherein the switch is controlled by a sampling clock signal.

[0009] Preferably, the switch is turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the switch is turned off during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch, and the reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

[0010] Preferably, the device further comprises: a first switching transistor connected in series with the first pass transistor; and a second switching transistor connected in series with the second pass transistor; wherein the first pass transistor indirectly receives the common-mode voltage via the first switching transistor, and the first switching transistor is controlled by a sampling clock signal; and the second pass transistor indirectly receives the input signal via the second switching transistor, and the second switching transistor is controlled by the sampling clock signal.

[0011] Preferably, the first switching transistor and the second switching transistor are turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are disconnected during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch, and the reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

[0012] Preferably, the first inverter includes a first transistor and a second transistor, which are connected in series between the ground and the power supply, wherein the type of the second transistor is opposite to that of the first transistor; the second inverter includes a third transistor and a fourth transistor, which are connected in series between the ground and the power supply, wherein the type of the fourth transistor is opposite to that of the third transistor.

[0013] According to an embodiment of the present invention, a recognition system includes a plurality of static random access memory (SRAM) cells and a quantizer. The SRAM cells are arranged in rows. The SRAM cells in each row receive corresponding input signals and generate corresponding output signals. The SRAM cells are connected to generate sub-signals, and the sub-signals in all rows are connected to generate an accumulated signal. The quantizer receives the accumulated signal and generates a digital output. The quantizer includes at least one capacitor array shared with the SRAM cells.

[0014] Preferably, the quantizer comprises a sequential approximation analog-to-digital converter.

[0015] Preferably, the sequential approximation analog-to-digital converter includes: a first digital-to-analog converter including a capacitor array; a second digital-to-analog converter including a capacitor array; a comparator receiving an output of the first digital-to-analog converter, an output of the second digital-to-analog converter, and the accumulated signal; and sequential approximation logic receiving a comparison result of the comparator to generate the digital output accordingly.

[0016] Preferably, it comprises a neural network comprising: an input layer, whose nodes receive the input signal; a first layer, whose nodes receive the output of the input layer; and an output layer, whose nodes receive the output of the first layer to identify the input signal; wherein the multiple static random access memory units constitute the nodes of the input layer.

[0017] Preferably, each node of the first layer includes: a digital-to-analog converter, including a capacitor array, which includes a plurality of capacitors; wherein the upper plates of the plurality of capacitors are connected together as the output of the digital-to-analog converter; and the lower plates of the plurality of capacitors are switched to receive the digital output or the reverse digital output of the input layer.

[0018] Preferably, each of the plurality of SRAM cells includes: a first inverter connected between ground and a power supply; a second inverter connected between the ground and the power supply, the first inverter and the second inverter being cross-coupled; a first access transistor controlled by a word line to access an output of the first inverter, which is transmitted via a first bit line; a second access transistor controlled by the word line to access an output of the second inverter, which is transmitted via a second bit line; a first pass transistor controlled by the output of the first inverter to allow a common-mode voltage to pass; a second pass transistor controlled by the output of the second inverter to allow an input signal to pass; and a capacitor, coupled between the common-mode voltage and the input signal via the first pass transistor and the second pass transistor, respectively; wherein the capacitors of the plurality of SRAM cells in different rows each have a weighted binary value.

[0019] Preferably, the SRAM cell further comprises a switch for switching the capacitor to be connected to the outputs of the first pass transistor and the second pass transistor, wherein the switch is controlled by a sampling clock signal.

[0020] Preferably, the switch is turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the switch is turned off during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch, and the reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

[0021] Preferably, the static random access memory unit further includes: a first switching transistor connected in series with the first pass transistor; and a second switching transistor connected in series with the second pass transistor; wherein the first pass transistor indirectly receives the common-mode voltage via the first switching transistor, and the first switching transistor is controlled by a sampling clock signal; and the second pass transistor indirectly receives the input signal via the second switching transistor, and the second switching transistor is controlled by the sampling clock signal.

[0022] Preferably, the first switching transistor and the second switching transistor are turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are disconnected during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch, and the reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

[0023] By means of the above technical solution, the present invention has at least the following advantages and effects: the present invention can improve the performance of low-power and / or high-bandwidth systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A A schematic diagram showing an (artificial) neural network suitable for a recognition system according to an embodiment of the present invention.

[0025] Figure 1B A block diagram showing an identification system according to an embodiment of the present invention.

[0026] Figure 2A The static random access memory cell ( Figure 1B ) circuit diagram.

[0027] Figure 2B Another embodiment of the present invention shows a static random access memory cell ( Figure 1B ) circuit diagram.

[0028] Figure 3A A circuit diagram of a sequential approximation analog-to-digital converter (SAR ADC) according to an embodiment of the present invention is shown, which is used as a quantizer in a recognition system.

[0029] Figure 3B A circuit diagram of a sequential approximation analog-to-digital converter (SAR ADC) according to another embodiment of the present invention is shown, which is used as a quantizer in a recognition system.

[0030] Figure 4A The equivalent circuit of a sequential approximation analog-to-digital converter (SAR ADC) in the first sampling stage is shown.

[0031] Figure 4B The equivalent circuit of a sequential approximation analog-to-digital converter (SAR ADC) in the second sampling stage is shown.

[0032] Figure 4C and Figure 4D The equivalent circuits of a SAR ADC in the first and second quantization stages are shown respectively when Vip (of the first DAC) is greater than Vin (of the second DAC).

[0033] Figure 4E and Figure 4F The equivalent circuits of a SAR ADC in the first and second quantization stages are shown respectively when Vip (of the first DAC) is less than Vin (of the second DAC).

[0034] Figure 5A A circuit diagram showing a digital-to-analog converter (DAC) representing Figure 1A The nodes of the first layer.

[0035] Figure 5B and Figure 5C The equivalent circuit diagrams of the digital-to-analog converter in the reset stage and the output stage are shown respectively.

[0036] Figure 5D Example Figure 5B and Figure 5C Timing diagram of the relevant signals.

[0037]

Main component symbol description

[0038] 100: Identification system

[0039] 11: Static random access memory unit

[0040] 200A: Continuous Approximation Analog-to-Digital Converter

[0041] 200B: Sequential Approximation Analog-to-Digital Converter

[0042] 21: First Digital to Analog Converter

[0043] 211: First virtual capacitor

[0044] 22: Second digital to analog converter

[0045] 221: Second virtual capacitor

[0046] 23: Comparator

[0047] 24: Sequential and Asymptotic Logic

[0048] Vin: input signal

[0049] Vin1~Vin6: input signal

[0050] CLKs: sampling clock signal

[0051] CLKsb: reverse sampling clock signal

[0052] Vcm: common mode voltage

[0053] Vmac: Accumulated signal

[0054] SRAM: Static Random Access Memory

[0055] M1: first transistor

[0056] M2: Second transistor

[0057] M3: The third transistor

[0058] M4: the fourth transistor

[0059] M5: Fifth transistor / first access transistor

[0060] M6: Sixth transistor / second access transistor

[0061] M7: Seventh transistor / first path transistor

[0062] M8: Eighth transistor / second channel transistor

[0063] M9: Ninth transistor / first switching transistor

[0064] M10: Tenth transistor / second switching transistor

[0065] Q: Output

[0066] Qb: output

[0067] BL: First bit line

[0068] BLb: Second bit line

[0069] WL: character line

[0070] SW1: switch

[0071] SW2: Reverse switch

[0072] C: Capacitor

[0073] Vref: reference voltage

[0074] Vrefp: positive reference voltage

[0075] Vrefn: negative reference voltage

[0076] Dout: digital output

[0077] DACout: output

[0078] bit0 to bit3: digital output

[0079] bit0b~bit3b: reverse digital output

[0080] SW: switch

[0081] SWb: switch

[0082] Reset: Reset signal

[0083] Reset_b: reverse reset signal DETAILED DESCRIPTION

[0084] Figure 1A A schematic diagram of an (artificial) neural network suitable for a recognition system according to an embodiment of the present invention is shown. A neural network may include connected nodes (or neurons) with weights between the connected nodes, which may be obtained through training with a dataset. The recognition system may be suitable for speech recognition to identify whether an input signal is speech or noise. Figure 1A In the example shown, the nodes in the input layer receive input signals (e.g., Vin1-Vin6), representing extracted features of different channels, and the nodes in the output layer can identify whether the input signal is speech or noise. The nodes in one or more hidden layers (e.g., the first layer shown) receive the output of the previous layer and generate outputs to be sent to the next layer.

[0085] Figure 1B A block diagram of an identification system 100 according to an embodiment of the present invention is shown. Figure 1B The illustrated recognition system 100 may be applicable to Figure 1A According to one of the features of this embodiment, the recognition system 100 uses a computation-in-memory (CIM) technique that integrates computation and memory, thereby reducing power consumption and saving bandwidth.

[0086] The recognition system 100 of this embodiment may include a plurality of static random access memory (SRAM) cells 11 arranged in rows. For each row, the SRAM cells 11 receive corresponding input signals (e.g., Vin1-Vin6) and generate corresponding (weighted) output signals, which are concatenated (added) to produce a sub-signal. Subsequently, the sub-signals from all rows are concatenated to produce a cumulative signal Vmac, which represents the output signal resulting from a multiply-accumulate operation performed by the plurality of SRAM cells 11 on the input signals.

[0087] Figure 2A The static random access memory unit 11 ( Figure 1B) circuit diagram. In this embodiment, the SRAM cell 11 may include eight transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) and one capacitor (i.e., 8T1C). The SRAM cell 11 of this embodiment may include a first inverter, which includes a first transistor M1 (e.g., an N-type metal oxide semiconductor field effect transistor) and a second transistor M2 (e.g., a P-type metal oxide semiconductor field effect transistor) connected in series between ground and a power supply, wherein the second transistor M2 has a type opposite to that of the first transistor M1. The SRAM cell 11 further includes a second inverter, which includes a third transistor M3 (e.g., an N-type metal oxide semiconductor field effect transistor) and a fourth transistor M4 (e.g., a P-type metal oxide semiconductor field effect transistor) connected in series between ground and a power supply, wherein the fourth transistor M4 has a type opposite to that of the third transistor M3. The first inverter (M1, M2) and the second inverter (M3, M4) are cross-coupled. That is, the output Q of the first inverter (M1, M2) is coupled to the input of the second inverter (M3, M4), and the (inverted) output Qb of the second inverter (M3, M4) is coupled to the input of the first inverter (M1, M2).

[0088] The SRAM cell 11 may include a first access transistor, including a fifth transistor M5 (e.g., an N-type metal oxide semiconductor field effect transistor), which is controlled by a word line WL to access the output Q of the first inverter (M1, M2), which is transmitted via a first bit line BL. The SRAM cell 11 further includes a second access transistor, including a sixth transistor M6 (e.g., an N-type metal oxide semiconductor field effect transistor), which is controlled by the word line WL to access the (inverted) output Qb of the second inverter (M3, M4), which is transmitted via a second bit line BLb.

[0089] According to one feature of this embodiment, the SRAM cell 11 may include a first pass transistor, comprising a seventh transistor M7 (e.g., an N-type metal oxide semiconductor field effect transistor), whose gate is controlled by the output Q of the first inverter (M1, M2) to allow the common-mode voltage Vcm to pass through (via the drain). The SRAM cell 11 further includes a second pass transistor, comprising an eighth transistor M8 (e.g., an N-type metal oxide semiconductor field effect transistor), whose gate is controlled by the output Qb of the second inverter (M3, M4) to allow the input signal Vin to pass through (via the drain). The outputs of the seventh transistor M7 and the eighth transistor M8 are connected together (at their sources).

[0090] According to another feature of this embodiment, the SRAM cell 11 may include a capacitor C that is switchably coupled to the common-mode voltage Vcm and the input signal Vin via the seventh transistor M7 and the eighth transistor M8, respectively. In this embodiment, the capacitor C receives the outputs of the first and second pass transistors M7 and M8 via a switch SW1, which is controlled by the sampling clock signal CLKs. It is worth noting that the values (or weights) of the capacitors C in different rows (of the identification system 100) are different from each other. The capacitors C in different rows of the SRAM cells 11 have binary-weighted values (e.g., C, 2C, 4C, and 8C).

[0091] Figure 2B Another embodiment of the present invention shows a static random access memory unit 11 ( Figure 1B In this embodiment, the SRAM cell 11 may include ten transistors and one capacitor (ie, 10T1C). Figure 2B The static random access memory unit 11 is similar to Figure 2A , the differences are explained as follows. Figure 2B As shown, the SRAM cell 11 further includes a first switching transistor comprising a ninth transistor M9 (e.g., an N-type metal oxide semiconductor field effect transistor) connected in series with the first pass transistor M7; and a second switching transistor comprising a tenth transistor M10 (e.g., an N-type metal oxide semiconductor field effect transistor) connected in series with the second pass transistor M8. Thus, the first pass transistor M7 indirectly receives the common-mode voltage Vcm via the first switching transistor M9 (whose gate is controlled by the sampling clock signal CLKs); and the second pass transistor M8 indirectly receives the input signal Vin via the second switching transistor M10 (whose gate is controlled by the sampling clock signal CLKs). However, the capacitor C is not directly connected to the outputs of the first and second pass transistors M7 / M8 via the switch SW1. Therefore, the first switching transistor M9 and the second switching transistor M10 serve together as a switch, so that the capacitor C can switch to receive the common mode voltage Vcm and the input signal Vin through the first pass transistor M7 and the second pass transistor M8 respectively.

[0092] During operation, switch SW1 (or the first / second switching transistors M9 / M10) is turned on during the sampling phase, causing the lower plate of capacitor C to sample the analog voltage (from the output of the first / second pass transistors M7 / M8), while the upper plate of capacitor C is coupled to the common-mode voltage Vcm. Switch SW1 (or the first / second switching transistors M9 / M10) is turned off during the quantization phase, and the lower plate of capacitor C is coupled to a reference voltage Vref (e.g., a positive reference voltage Vrefp or a negative reference voltage Vrefn) via a reverse switch SW2. This reverse switch SW2 is controlled by a reverse sampling clock signal CLKsb (which has an opposite polarity relative to the sampling clock signal CLKs), while the upper plate of capacitor C receives the previously sampled voltage.

[0093] Figure 3A The circuit diagram of a successive approximation register analog-to-digital converter (SAR ADC) 200A according to an embodiment of the present invention is shown as a quantizer in the recognition system 100. The successive approximation register analog-to-digital converter 200A converts a continuous analog wave into discrete digital values, performing a binary search at all quantization levels, and finally converging to a digital output Dout at each conversion. The successive approximation register analog-to-digital converter 200A is a quantizer that can be used in conjunction with the quantizer. Figure 1B The static random access memory cell 11 of the sequential approximation analog-to-digital converter 200A may include a first digital-to-analog converter (DAC) 21 including a capacitor array; and a second digital-to-analog converter (DAC) 22 including a capacitor array. The capacitor arrays of the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 may be switchably coupled to an input signal (e.g., Vin1 to Vin6) and a common-mode voltage Vcm. The sequential approximation analog-to-digital converter 200A may include a comparator 23, which receives the output of the first digital-to-analog converter (DAC) 21 (at a non-inverting input node) and receives the output of the second digital-to-analog converter (DAC) 22 (at an inverting input node). In addition, the comparator 23 also receives an accumulation signal Vmac. The sequential approximation analog-to-digital converter 200A may include a sequential approximation logic 24, which receives the comparison result of the comparator 23 and generates a digital output Dout accordingly. According to one of the features of this embodiment, the capacitor arrays of the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 can be connected to Figure 1B The static random access memory unit 11 is shared.

[0094] Figure 3BA circuit diagram of a sequential approximation analog-to-digital converter (SAR ADC) 200B according to another embodiment of the present invention is shown, serving as a quantizer in the recognition system 100 . Figure 3B The SAR ADC 200B is similar to Figure 3A The differences of the SAR ADC 200A are described below. In this embodiment, the first DAC 21 and the second DAC 22 further include a first dummy capacitor 211 and a second dummy capacitor 221, respectively, which are switchably connected to the input signals (e.g., Vin1-Vin6) and the common-mode voltage Vcm.

[0095] Figure 4A The equivalent circuit of the SAR ADC 200B in the first sampling stage is shown, and Figure 4B The equivalent circuit of the SAR ADC 200B in the second sampling stage is shown. Figure 4C and Figure 4D The equivalent circuits of the SAR ADC 200B in the first and second quantization stages are shown respectively when Vip (of the first DAC 21 ) is greater than Vin (of the second DAC 22 ). Figure 4E and Figure 4F The equivalent circuits of the SAR ADC 200B in the first and second quantization stages are shown respectively when Vip (of the first DAC 21 ) is less than Vin (of the second DAC 22 ).

[0096] According to the above embodiment, the static random access memory unit 11 adopts the charge redistribution principle to generate the accumulated signal Vmac, rather than the charge sharing principle of the conventional system. Therefore, compared with the conventional system, the timing of the above embodiment of the present invention becomes simpler and does not require a reset phase. In addition, the capacitor array of the sequential analog-to-digital converter 200A / B can generate the accumulated signal Vmac during the sampling phase. Furthermore, in Figure 3B The sequential approximation analog-to-digital converter 200B uses virtual capacitors so that the signal swing can approach the full range.

[0097] Figure 5A A circuit diagram showing a digital-to-analog converter (DAC) 500 is shown, which represents Figure 1AThe nodes of the first layer. Figure 5B and Figure 5C The equivalent circuit diagrams of the digital-to-analog converter 500 in the reset phase and the output phase are shown respectively, and Figure 5D Example Figure 5B and Figure 5C In this embodiment, the digital-to-analog converter (DAC) 500 may include a capacitor array, which includes a plurality of capacitors (e.g., C, 2C, 4C, and 8C). The upper plates of the capacitors are connected together as the output DACout of the digital-to-analog converter (DAC) 500. The lower plates of the capacitors switch to receive the digital output or the reverse digital output of the previous layer. Among them, bit0 to bit3 represent the previous layer (e.g. Figure 1A The digital outputs generated by the sequential approximation logic 24 of the input layer (bit0b-bit3b) are shown. Bits 0b-3b represent inverted digital outputs, with polarities opposite to those of the digital outputs bit 0-bit 3. For example, digital outputs bit 0 and bit 0b are electrically coupled to corresponding capacitors via switches SW and SWb, respectively (where switch SW operates oppositely to switch SWb). Switches SW and SWb are controlled by pre-trained and pre-stored weights. The output DACout of digital-to-analog converter (DAC) 500 is then transmitted to a comparator (e.g., a node located at the output layer) for speech or noise recognition.

[0098] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A static random access memory unit, characterized in that: Include: A first inverter is connected between the ground and the power supply; A second inverter is connected between the ground and the power supply, and the first inverter and the second inverter are cross-coupled; A first access transistor is controlled by a word line to access the output of the first inverter, which is transmitted via a first bit line; A second access transistor is controlled by the word line to access the output of the second inverter, which is transmitted via a second bit line; A first pass transistor, controlled by the output of the first inverter, for passing the common mode voltage; a second pass transistor, controlled by the output of the second inverter, for passing the input signal; and The capacitor switches and couples the common mode voltage and the input signal through the first pass transistor and the second pass transistor, respectively.

2. The static random access memory unit according to claim 1, wherein: Also includes: The switch is used to switch the capacitor to be connected to the outputs of the first pass transistor and the second pass transistor, and the switch is controlled by a sampling clock signal.

3. The static random access memory unit according to claim 2, wherein: The switch is turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampled voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the switch is turned off during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch. The reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampled voltage.

4. The static random access memory unit according to claim 1, wherein: Also includes: A first switching transistor is connected in series to the first pass transistor; and a second switching transistor connected in series to the second pass transistor; The first pass transistor indirectly receives the common mode voltage via the first switching transistor, which is controlled by a sampling clock signal; and the second pass transistor indirectly receives the input signal via the second switching transistor, which is controlled by the sampling clock signal.

5. The static random access memory unit according to claim 4, wherein: The first switching transistor and the second switching transistor are turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampled voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are turned off during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch. The reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampled voltage.

6. The static random access memory unit according to claim 1, wherein: The first inverter includes a first transistor and a second transistor, which are connected in series between the ground and the power supply, wherein the type of the second transistor is opposite to that of the first transistor; the second inverter includes a third transistor and a fourth transistor, which are connected in series between the ground and the power supply, wherein the type of the fourth transistor is opposite to that of the third transistor.

7. An identification system, characterized in that Include: A plurality of static random access memory cells are arranged in rows, wherein the static random access memory cells in each row receive corresponding input signals and generate corresponding output signals, which are connected to generate sub-signals, and the sub-signals in all rows are connected to generate an accumulated signal; and a quantizer receiving the accumulated signal to generate a digital output, the quantizer comprising at least one capacitor array; wherein the at least one capacitor array is shared with the plurality of static random access memory cells; Each of the plurality of static random access memory cells comprises: A first inverter is connected between the ground and the power supply; A second inverter is connected between the ground and the power supply, and the first inverter and the second inverter are cross-coupled; A first access transistor is controlled by a word line to access the output of the first inverter, which is transmitted via a first bit line; A second access transistor is controlled by the word line to access the output of the second inverter, which is transmitted via the second bit line; A first pass transistor, controlled by the output of the first inverter, for passing the common mode voltage; a second pass transistor, controlled by the output of the second inverter, for passing the input signal; and The capacitor switches and couples the common mode voltage and the input signal through the first pass transistor and the second pass transistor, respectively.

8. The identification system according to claim 7, characterized in that The quantizer includes a sequential approximation analog-to-digital converter.

9. The identification system according to claim 8, characterized in that The sequential approximation analog-to-digital converter comprises: a first digital-to-analog converter comprising a capacitor array; a second digital-to-analog converter comprising a capacitor array; a comparator receiving an output of the first digital-to-analog converter, an output of the second digital-to-analog converter, and the accumulated signal; and The sequential approximation logic receives the comparison result of the comparator and generates the digital output accordingly.

10. The identification system according to claim 7, characterized in that Contains a neural network, which contains: an input layer, whose nodes receive the input signal; The first layer, whose nodes receive the output of the input layer; and an output layer, whose nodes receive the output of the first layer and identify the input signal accordingly; The plurality of static random access memory units constitute nodes of the input layer.

11. The identification system according to claim 10, characterized in that Each node in the first layer contains: a digital-to-analog converter comprising a capacitor array including a plurality of capacitors; The upper plates of the plurality of capacitors are connected together as the output of the digital-to-analog converter; and the lower plates of the plurality of capacitors are switched to receive the digital output or the inverse digital output of the input layer.

12. The identification system according to claim 7, characterized in that The capacitors of the plurality of static random access memory cells in different rows respectively have weighted binary values.

13. The identification system according to claim 12, characterized in that The static random access memory unit further comprises: The switch is used to switch the capacitor to be connected to the outputs of the first pass transistor and the second pass transistor, and the switch is controlled by a sampling clock signal.

14. The identification system according to claim 13, characterized in that The switch is turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampled voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the switch is turned off during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch. The reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampled voltage.

15. The identification system according to claim 12, characterized in that The static random access memory unit further comprises: A first switching transistor is connected in series to the first pass transistor; and a second switching transistor connected in series to the second pass transistor; The first pass transistor indirectly receives the common mode voltage via the first switching transistor, which is controlled by a sampling clock signal; and the second pass transistor indirectly receives the input signal via the second switching transistor, which is controlled by the sampling clock signal.

16. The identification system according to claim 15, characterized in that The first switching transistor and the second switching transistor are turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampled voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are turned off during the quantization phase, and the lower plate of the capacitor is switched to be coupled to the reference voltage by a reverse switch. The reverse switch is controlled by a reverse sampling clock signal, which has an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampled voltage.

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