IGBT devices

Abstract

The present invention belongs to the technical field of semiconductor power devices and specifically discloses an IGBT device, comprising an n-type semiconductor layer; a plurality of p-type body regions located in the n-type semiconductor layer, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a shield gate located in the lower portion of the gate trench, and a gate located in the upper portion of the gate trench, wherein the gate, the shield gate and the n-type semiconductor layer are insulated and isolated from each other; among the plurality of p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region, the first doping concentration of the first p-type body region being less than the second doping concentration of the second p-type body region; at least one shield gate in the gate trench adjacent to the first p-type body region is externally connected to a gate voltage, and the shield gates in the remaining gate trenches are externally connected to an emitter voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and in particular relates to an IGBT device. Background Art

[0002] An insulated gate bipolar transistor (IGBT) is a composite of a metal oxide semiconductor (MOS) transistor and a bipolar transistor. The IGBT's input is a MOS transistor, and its output is a PNP transistor. It combines the advantages of both transistors, offering the low drive power and fast switching speed of a MOS transistor with the low saturation voltage drop and high capacitance of a bipolar transistor. Due to the low hole injection efficiency and low carrier concentration distribution at the interface between the p-type body and n-type drift regions of an IGBT, the saturation voltage drop increases. During shutdown, a large number of minority carriers accumulate in the n-type drift region, resulting in severe current tailing and high turn-off losses. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide an IGBT device to reduce the turn-off loss of the IGBT device.

[0004] To achieve the above-mentioned object of the present invention, the present invention provides an IGBT device, comprising:

[0005] p-type collector region;

[0006] an n-type semiconductor layer located above the p-type collector region;

[0007] a plurality of p-type body regions located in the n-type semiconductor layer, wherein n-type emitter regions are provided in the p-type body regions;

[0008] a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a shield gate located in a lower portion of the gate trench, and a gate located in an upper portion of the gate trench, wherein the gate, the shield gate, and the n-type semiconductor layer are insulated from each other;

[0009] Among the plurality of p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region, wherein the first doping concentration of the first p-type body region is less than the second doping concentration of the second p-type body region;

[0010] The shielding gate in at least one of the gate trenches adjacent to the first p-type body region is externally connected to a gate voltage, and the shielding gates in the remaining gate trenches are externally connected to an emitter voltage.

[0011] Optionally, the shielding gate extends upward from the lower portion of the gate trench to the upper portion of the gate trench.

[0012] Optionally, the width of the upper portion of the gate trench is greater than the width of the lower portion of the gate trench.

[0013] Optionally, it further includes an n-type charge storage region located in the n-type semiconductor layer, and the n-type charge storage region is located below the gate.

[0014] Optionally, an n-type collector region is further included, wherein the n-type collector region is located below the n-type semiconductor layer and is alternately arranged with the p-type collector region.

[0015] Optionally, an n-type field stop region is further included, and the n-type field stop region is located between the p-type collector region and the n-type semiconductor layer.

[0016] The IGBT device of the present invention combines a low threshold voltage Vth1 with a large gate charge Qg1, and a high threshold voltage Vth2 with a small gate charge Qg2. During the IGBT device's on-to-off transition, the current channel in the region with the high Vth2 and small Qg2 combination is quickly turned off, while the current channel in the region with the low Vth1 and large Qg1 combination is turned off later. Consequently, when the current channel in the region with the high Vth2 and small Qg2 combination is just turned off, the current channel in the region with the low Vth1 and large Qg1 combination remains on. As the gate voltage Vg further decreases, the current channel in the region with the low Vth1 and large Qg1 combination is turned off. Consequently, the IGBT device exhibits turn-off losses in the region with the low Vth1 and large Qg1 combination, while reducing the turn-off losses in the region with the high Vth2 and small Qg2 combination, thereby reducing the turn-off losses of the IGBT device as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0018] Figure 1 1 is a schematic cross-sectional view of a first embodiment of an IGBT device provided by the present invention;

[0019] Figure 2 It is a schematic cross-sectional structural diagram of a second embodiment of the IGBT device provided by the present invention. DETAILED DESCRIPTION

[0020] The following will fully describe the technical solutions of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a portion of the embodiments of the present invention, not all of them. Furthermore, to clearly illustrate the specific implementation methods of the present invention, the schematic diagrams in the accompanying drawings exaggerate the thicknesses of the layers and regions described in the present invention, and the sizes of the figures do not represent actual sizes.

[0021] Figure 1 FIG. 1 is a schematic cross-sectional view of a first embodiment of an IGBT device provided by the present invention. Figure 1 As shown, the IGBT device of the present invention includes a p-type collector region 20 , an n-type semiconductor layer 21 located above the p-type collector region 20 , a plurality of p-type body regions 22 located in the n-type semiconductor layer 21 , and an n-type emitter region 23 provided in the p-type body region 22 .

[0022] A gate trench is located in the n-type semiconductor layer 21 and between adjacent p-type body regions 22, a gate 25 is located in the upper portion of the gate trench, and a shield gate 27 is located in the lower portion of the gate trench. The shield gate 27 can be located only in the lower portion of the gate trench, so that the gate 25 and the shield gate 27 form a top-bottom structure. Optionally, the shield gate 27 can also be located in the lower portion of the gate trench and extend upward to the upper portion of the gate trench. Figure 1 The shield gate 27 is located in the lower part of the gate trench and extends upward to the upper part of the gate trench. At the same time, the width of the upper part of the gate trench can be greater than, equal to, or less than the width of the lower part of the gate trench. Figure 1 In the figure, the width of the upper portion of the gate trench is shown to be greater than the width of the lower portion of the gate trench.

[0023] The gate 25, the shielding gate 27 and the n-type semiconductor layer 21 are insulated from each other. Figure 1 In the embodiment, the gate 25 is insulated and isolated from the n-type semiconductor layer 21 by the gate dielectric layer 24 , and the shielding gate 27 is isolated from the gate 25 and the n-type semiconductor layer 21 by the field oxide layer 26 .

[0024] Among the several p-type body regions 22 of the present invention, four p-type body regions 22 are exemplarily shown in the embodiment of the present invention, wherein at least one p-type body region 22 has a first doping concentration and is defined as a first p-type body region 22a, and at least one p-type body region 22 has a second doping concentration and is defined as a second p-type body region 22b, and the first doping concentration of the first p-type body region 22a is less than the second doping concentration of the second p-type body region 22b. Figure 1 exemplarily shown in FIG. 1 , one first p-type body region 22 a and three second p-type body regions 22 b are shown.

[0025] In the IGBT device of the present invention, at least one shield gate 27 in a gate trench adjacent to the first p-type body region 22a is connected to an external gate voltage, and the shield gates 27 in the remaining gate trenches are connected to an external emitter voltage. Figure 1 In the embodiment, the shield gate 27 in the gate trench close to the right side of the first p-type body region 22a is connected to the gate voltage (G) together with the gate 25, and the shield gate 27 in the remaining gate trenches is connected to the emitter voltage ( Figure 1 not shown).

[0026] In the IGBT device of the present invention, the threshold voltage Vth1 of the current channel within the first p-type body region 22a having a first doping concentration is lower than the threshold voltage Vth2 of the current channel within the second p-type body region 22b having a second doping concentration. When a gate voltage is applied to the shielded gate 27, the gate 25 within the gate trench has a larger gate charge Qg1. When an emitter voltage is applied to the shielded gate 27, the gate 25 within the gate trench has a smaller gate charge Qg2. By connecting the shield gate 27 in at least one gate trench adjacent to the first p-type body region 22a to a gate voltage, and connecting the shield gates 27 in the remaining gate trenches to an emitter voltage, a low Vth1 and a large Qg1 combination, and a high Vth2 and a small Qg2 combination can be achieved. As a result, during the process from on-state to off-state of the IGBT device, the current channel in the region where the high Vth2 and small Qg2 are combined will be quickly turned off, while the current channel in the region where the low Vth1 and large Qg1 are combined will be turned off later. As a result, when the current channel in the region where the high Vth2 and small Qg2 are combined is just turned off, the current channel in the region where the low Vth1 and large Qg1 are combined is still in the on state. As the gate voltage Vg further decreases, the current channel in the region where the low Vth1 and large Qg1 are combined is turned off. Therefore, the IGBT device shows externally the turn-off loss in the area of ​​low Vth1 and large Qg1 combination, reduces the turn-off loss in the area of ​​high Vth2 and small Qg2 combination, and reduces the turn-off loss of the IGBT device as a whole.

[0027] Figure 2 FIG. 1 is a schematic cross-sectional view of a second embodiment of an IGBT device provided by the present invention. Figure 2 As shown, in Figure 1Based on the illustrated IGBT device structure, the IGBT device of the present invention further includes an n-type charge storage region 32 located within the n-type semiconductor layer 21, and the n-type charge storage region 32 is located below the gate 25. The IGBT device of the present invention further includes an n-type collector region 30, which is located below the n-type semiconductor layer 21 and alternately spaced with the p-type collector region 20. Optionally, the IGBT device of the present invention may further include an n-type field-stop region 31, which is located between the p-type collector region 20 and the n-type semiconductor layer 21. The n-type charge storage region 32, the n-type field-stop region 31, and the n-type collector region 30 are all known in the art and will not be described in detail in the present embodiment.

[0028] The above specific implementation methods and examples are specific support for the technical ideas of the present invention and cannot be used to limit the scope of protection of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. IGBT device, characterized in that include: p-type collector region; an n-type semiconductor layer located above the p-type collector region; a plurality of p-type body regions located in the n-type semiconductor layer, wherein n-type emitter regions are provided in the p-type body regions; a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a shield gate located in a lower portion of the gate trench, and a gate located in an upper portion of the gate trench, wherein the gate, the shield gate, and the n-type semiconductor layer are insulated from each other; Among the plurality of p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region, wherein the first doping concentration of the first p-type body region is less than the second doping concentration of the second p-type body region; The shielding gate in at least one of the gate trenches adjacent to the first p-type body region is externally connected to a gate voltage, and the shielding gates in the remaining gate trenches are externally connected to an emitter voltage.

2. The IGBT device according to claim 1, wherein: The shielding gate extends upward from the lower portion of the gate trench to the upper portion of the gate trench.

3. The IGBT device according to claim 2, wherein: The width of the upper portion of the gate trench is greater than the width of the lower portion of the gate trench.

4. The IGBT device according to claim 3, wherein: The device further includes an n-type charge storage region located in the n-type semiconductor layer, wherein the n-type charge storage region is located below the gate.

5. The IGBT device according to claim 1, wherein: The device further comprises an n-type collector region, which is located below the n-type semiconductor layer and is alternately spaced with the p-type collector region.

6. The IGBT device according to claim 1, wherein: The invention also includes an n-type field stop region, wherein the n-type field stop region is located between the p-type collector region and the n-type semiconductor layer.

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