Synchronization of receiver and transmitter local oscillators for ranging applications

Abstract

A system and method for accurately determining the distance between two network devices using channel sounding is disclosed. Each network device ensures a fixed phase relationship between the transmit and receive circuits. In one embodiment, this is accomplished by configuring a frequency divider outside the phase locked loop and using the output of the frequency divider to generate the clocks for the transmit and receive circuits. In another embodiment, one or more frequency dividers are configured outside the phase locked loop, each frequency divider having a reset so that the frequency dividers can be initialized to a predetermined state. Furthermore, by utilizing frequency dividers with a reset, the clocks for the transmit and receive circuits that the quadrature signal generator outputs are ensured to have a constant phase relationship.

Description

TECHNICAL FIELD

[0001] The present disclosure describes systems and methods for determining a distance between network devices, and more specifically for determining a distance by guaranteeing a constant phase delay between a transmit clock and a receive clock. BACKGROUND

[0002] Currently, there is interest in extending current network protocols to enable network devices to determine a distance to another network device. For example, the Bluetooth specification is being modified to include distance measurement through a Channel Sounding (CS) feature. As currently proposed, Channel Sounding discloses a basic measurement technique for two-way ranging. Two-way ranging requires establishing and maintaining a network connection between a initiator and a reflector. Because a network connection is established, security can be provided.

[0003] Figure 1 Two network devices are shown that can be used to perform distance measurements for positioning using Channel Sounding. The first network device 100 can be referred to as a localizer or initiator, while the second network device 110 can be referred to as a tag or reflector. In operation, the first network device 100 transmits a first data packet to the second network device 110. Upon receiving the first data packet from the initiator, the second network device 110 responds by transmitting a second data packet to the first network device 110.

[0004] The second network device 110 can determine the phase of the signal received by the second network device from the first network device. This phase has three components: a phase related to the transmit circuitry of the initiator, a phase related to the receive circuitry of the reflector, and a phase delay related to the distance between the two network devices. In other words, the phase received by the reflector can be expressed as:

[0005] θ1= θ I，T - θ R，R + 2πf1t p

[0006] where θ I，T is the phase of the transmit circuitry of the initiator;

[0007] θ R，R is the phase of the receive circuitry of the reflector;

[0008] f1is the frequency of the transmitted signal; and

[0009] t p is the time it takes for the signal to travel from the initiator to the reflector.

[0010] Similarly, the phase of the second data packet received by the initiator can be expressed as:

[0011] θ2= θ I，T - θ I，R + 2πf1t p

[0012] where θ R，T is the phase of the transmit circuit of the reflector;

[0013] θ I，R is the phase of the receive circuit of the initiator;

[0014] f1is the frequency of the transmitted signal; and

[0015] t p is the time it takes for the signal to travel from the reflector to the initiator.

[0016] Adding these values together gives:

[0017]

[0018] If this sequence is performed at a second frequency, the result can be expressed as:

[0019]

[0020] Subtracting these two expressions gives:

[0021]

[0022] where d is the distance between the two network devices; and

[0023] c is the speed of light.

[0024] Note that the above equations assume that (θ I，T - θ I，R ) + (θ R，T - θ R，R ) is constant for these two frequencies. This relationship must hold for any frequencies that the channel sounding algorithm can use. In other words, for the two network devices, the phase of the transmit circuit minus the phase of the receive circuit, or θ T - θ R must be constant. For example, if this quantity changes, it can be difficult or impossible to accurately determine the distance between the two network devices. Similar constraints can also exist for one-way ranging applications and any other phase-based ranging applications.

[0025] Accordingly, it would be beneficial if there were a system that could use channel sounding with predictable results for distance measurement. SUMMARY

[0026] A system and method for accurately determining the distance between two network devices using channel sounding is disclosed. Each network device guarantees a fixed phase relationship between the transmit and receive circuits. In one embodiment, this is achieved by configuring a frequency divider outside of a phase locked loop (PLL) and using the output of the frequency divider to generate the clocks for the transmit and receive circuits. In another embodiment, one or more frequency dividers are configured outside of a phase locked loop, each frequency divider having a reset such that the frequency divider can be initialized to a predetermined state. Furthermore, by utilizing frequency dividers with a reset, the clocks for the transmit and receive circuits that the quadrature signal generator outputs are guaranteed to have a constant phase relationship.

[0027] According to one embodiment, a clock generation circuit is disclosed. The clock generation circuit includes a signal source to provide a reference clock (REFCLK) signal; a phase-locked loop including a detector to determine a difference between the REFCLK signal and a feedback signal and provide an output based on the difference; a loop filter to filter the output to produce a filtered output; an oscillator to generate a clock signal having a frequency related to the filtered output; a buffer to buffer the clock signal; and a multiple modulus divider in communication with an output of the buffer to divide the output of the oscillator and provide the feedback signal to the detector; and a frequency divider in communication with an output of the buffer to divide the clock signal by an amount; wherein the frequency divider includes a reset signal to initialize the frequency divider to a known state. In some embodiments, the clock generation circuit includes a quadrature signal generator in communication with an output of the frequency divider. In some embodiments, the quadrature signal generator outputs a transmit clock and a receive clock, and wherein a phase difference between the transmit clock and the receive clock is constant. In certain embodiments, the quadrature signal generator includes a shift register. In some embodiments, the quadrature signal generator includes combinational logic, wherein the shift register and the combinational logic are used to generate the receive clock and the transmit clock. In some embodiments, the receive clock output by the quadrature signal generator has a duty cycle of 12.5%, 25%, or 50%. In some embodiments, the shift register is used to generate the transmit clock, and the transmit clock output by the quadrature signal generator has a duty cycle of 12.5%, 25%, or 50%. In certain embodiments, the clock generation circuit includes a second frequency divider in communication with an output of the buffer to divide the clock signal by a second amount, wherein the second frequency divider includes a reset signal to initialize the second frequency divider to a known state. In certain embodiments, an output of the frequency divider is used as an input to a transmit quadrature signal generator, and an output of the second frequency divider is used as an input to a receive quadrature signal generator. In some embodiments, the detector includes a phase / frequency detector and a charge pump; and the oscillator includes a voltage controlled oscillator, and outputs from the phase / frequency detector and charge pump and the loop filter are voltages. In some embodiments, the detector includes a time-to-digital converter, an output from the loop filter includes a digital word, and the oscillator includes a digitally controlled oscillator.

[0028] According to another embodiment, a method of performing a distance measurement between a first network device and a second network device is disclosed. The method includes transmitting a first data packet from the first network device to the second network device using a first frequency, responding to the first data packet by transmitting a second data packet from the second network device to the first network device using the first frequency, transmitting a third data packet from the first network device to the second network device using a second frequency different from the first frequency, responding to the third data packet by transmitting a fourth data packet from the second network device to the first network device using the second frequency, and calculating a distance based on a phase of each data packet received by the first network device and the second network device, the first frequency, and the second frequency, wherein the first network device and the second network device each include a clock generation circuit having a phase-locked loop and at least one frequency divider configured outside the phase-locked loop for generating a receive clock and a transmit clock such that a phase difference between the transmit clock and the receive clock of each network device is constant. In some embodiments, the clock generation circuit includes a signal source for providing a REFCLK signal, the phase-locked loop including a detector for determining a difference between the REFCLK signal and a feedback signal and providing an output based on the difference, a loop filter for filtering the output to produce a filtered output, an oscillator for generating a clock signal having a frequency related to the filtered output, a buffer for buffering the clock signal, and a plurality of modulus dividers in communication with an output of the buffer for dividing the output of the oscillator and providing the feedback signal to the detector, and the at least one frequency divider in communication with the output of the buffer for dividing the clock signal by an amount. In some embodiments, the at least one frequency divider includes a reset signal to initialize the frequency divider to a known state. In some embodiments, the detector includes a phase / frequency detector and a charge pump, and the oscillator includes a voltage-controlled oscillator and the output from the phase / frequency detector and charge pump and the loop filter is a voltage. In some embodiments, the detector includes a time-to-digital converter, the output from the loop filter includes a digital word, and the oscillator includes a digitally-controlled oscillator. In certain embodiments, the clock generation circuit further includes a quadrature signal generator in communication with an output of the at least one frequency divider for generating the receive clock and the transmit clock.

[0029] According to another embodiment, a clock generation circuit is disclosed. The clock generation circuit includes a receive clock generation circuit; and a transmit clock generation circuit; and a signal source for providing a REFCLK signal; wherein the receive clock generation circuit and the transmit clock generation circuit each include a phase-locked loop including a detector for determining a difference between the REFCLK signal and a feedback signal and providing an output based on the difference; a loop filter for filtering the output to produce a filtered output; an oscillator for generating a clock signal having a frequency related to the filtered output; a buffer for buffering the clock signal; a multi-modulus divider in communication with an output of the buffer and for dividing the output of the oscillator by an integer and providing the feedback signal to the detector; and a frequency divider in communication with an output of the buffer and for dividing the clock signal by a certain amount; wherein the frequency divider includes a reset signal to initialize the frequency divider to a known state; wherein the transmit clock is generated based on the output of the frequency divider in the transmit clock generation circuit, and the receive clock is generated based on the output of the frequency divider in the receive clock generation circuit, and wherein the phase difference between the transmit clock and the receive clock is constant. In some embodiments, at least one of the detectors of the receive clock generation circuit or the transmit clock generation circuit comprises a phase / frequency detector and a charge pump; the oscillator comprises a voltage-controlled oscillator, and the outputs from the phase / frequency detector and the charge pump and the loop filter are voltages. In some embodiments, at least one of the detectors of the receive clock generation circuit or the transmit clock generation circuit comprises a time-to-digital converter, the output from the loop filter comprises a digital word, and the oscillator comprises a digitally controlled oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] For a better understanding of the present disclosure, reference is made to the accompanying drawings, wherein like elements are designated by like numerals, and wherein:

[0031] Figure 1 Shown are a first network device and a second network device transmitting range detection packets to each other;

[0032] Figure 2 is a block diagram of a network device that can be used to perform distance detection as described herein;

[0033] Figures 3A-3B Two different embodiments are shown. Figure 2 A block diagram of a transmitting circuit of a network device;

[0034] Figure 4 yes Figure 2 a block diagram of a radio receiver of a network device;

[0035] Figure 5A shows the architecture of a phase-locked loop according to one embodiment;

[0036] Figure 5B shows the architecture of a phase-locked loop according to a second embodiment;

[0037] Figure 5C shows the architecture of a phase-locked loop according to a third embodiment;

[0038] Figure 6A shows a quadrature signal generator according to one embodiment;

[0039] Figure 6B Shown with Figure 6A a timing diagram associated with a quadrature signal generator; and

[0040] Figure 7A shows a quadrature signal generator according to a second embodiment;

[0041] Figure 7B Shown with Figure 7A The timing diagram associated with the quadrature signal generator;

[0042] Figure 8A shows a quadrature signal generator according to a third embodiment;

[0043] Figure 8B Shown with Figure 8A a timing diagram associated with a quadrature signal generator; and

[0044] Figure 9 The architecture of a phase-locked loop according to a fourth embodiment is shown. DETAILED DESCRIPTION

[0045] Figure 2A network device that can be used to perform the distance detection algorithms described herein is shown. The network device 10 has a processing unit 20 and an associated memory device 25. The processing unit 20 can be any suitable component, such as a microprocessor, embedded processor, application specific circuit, programmable circuit, microcontroller, or other similar device. The memory device 25 contains instructions that, when executed by the processing unit 20, enable the network device 10 to perform the functions described herein. The memory device 25 can be a non-volatile memory, such as a flash read-only memory (ROM), electrically erasable read-only memory, or other suitable device. In other embodiments, the memory device 25 can be a volatile memory, such as a random access memory (RAM) or dynamic random access memory (DRAM). The instructions contained within the memory device 25 can be referred to as a software program, which is configured on a non-transitory storage medium.

[0046] The network device 10 also includes a network interface 30, which can be a wireless network interface that includes an antenna 37. The network interface 30 can support any wireless network protocol that supports distance detection, such as Bluetooth. The network interface 30 is used to allow the network device 10 to communicate with other devices configured on a network 39.

[0047] The network interface 30 can include a radio circuit 31. The radio circuit 31 is used to process incoming signals and convert wireless signals to digital signals. The radio circuit 31 is also used to transmit outgoing signals. The components within the radio circuit 31 are described in more detail below.

[0048] The radio circuit 31 includes a receive circuit 36. The receive circuit 36 is used to receive, synchronize, and decode digital signals received from the antenna 37. In particular, the receive circuit 36 has a preamble detector for identifying the beginning of an incoming data packet. The receive circuit 36 also has a sync detector for identifying a particular bit sequence known as a sync character. In addition, the receive circuit 36 has a decoder for converting the digital signals into properly aligned data bytes.

[0049] The radio circuit 31 also includes a transmit circuit 38. The transmit circuit 38 can include a power amplifier for providing a signal to be transmitted to the antenna 37.

[0050] The network device 10 can include a second memory device 40. Data received from or to be sent via the network interface 30 can also be stored in the second memory device 40. The second memory device 40 is traditionally a volatile memory.

[0051] While a memory device 25 is disclosed, any computer readable medium can be employed to store the instructions. For example, a read only memory (ROM), a random access memory (RAM), a magnetic storage device such as a hard disk drive, or an optical storage device such as a Compact Disk (CD) or a Digital Video Disc (DVD) can be employed. In addition, the instructions can be downloaded to the memory device 25 from the Internet, for example, via a network connection (not shown), via a CD ROM, or through other means. The instructions can be executed by the processing unit 20 in any programming language, but are not limited thereto. Thus, in some embodiments, there can be a plurality of computer readable non-transitory media containing the instructions described herein. As Figure 2 indicated, a first computer readable non-transitory medium can be in communication with the processing unit 20. A second computer readable non-transitory medium can be a CD ROM or a different storage device located remotely from the network device 10. Instructions contained in this second computer readable non-transitory medium can be downloaded to the memory device 25 to allow the network device 10 to execute the instructions.

[0052] While the processing unit 20, the memory device 25, the network interface 30 and the second memory device 40 are shown in Figure 2 as separate components, it is understood that some or all of these components can be integrated into a single electronic component. More precisely, Figure 2 are used to illustrate the functionality of the network device 10, and not its physical configuration.

[0053] Although not shown, the network device 10 also has a power source, which can be a battery or a connection to a permanent power source, such as a wall outlet.

[0054] Figure 3A A first embodiment of the transmit circuit 38 is shown, which can be used to generate two signals at two different frequencies, with phase continuity between these signals during frequency switching. The transmit circuit 38 includes a baseband signal generator 60, which is common to all Radio Frequency (RF) transmitters. The output of the baseband signal generator 60 can include two outputs, an in-phase output Ibb and a quadrature output Qbb. Each of these outputs can enter an interpolation filter 63 for upsampling the waveform. The interpolation filter 63 is followed by a digital to analog converter (DAC) 64, which converts the digital data to an analog waveform. The DAC 64 can be followed by a lowpass filter (LPF) 65. The output of the LPF 65 then enters a mixer 66, which multiplies the LPF 65 output by I lo and Qlo The carrier frequency can be generated by a transmit phase locked loop (PLL) 69. These two components are then added together. The composite signal then enters a power amplifier (PA) 68 and is transmitted by an antenna 37.

[0055] Figure 3A A linear I-Q based up-conversion architecture is shown for amplitude and constant envelope modulation schemes. Direct transmit modulation with a PLL is another architecture, as shown in Figure 3B The same components are given the same reference numerals in Figure 3B In this embodiment, a baseband signal generator 61 provides an input to a phase locked loop. Figure 3B A phase locked loop is shown that includes a signal source 200, a phase / frequency detector and charge pump (PFDCP) 210, a loop filter (LF) 220, a voltage-controlled oscillator (VCO) 230, a frequency divider 240, and a multi-modulus divider (MMD) 250. Each of these components is described in more detail below. The baseband signal generator 61 drives the MMD 250 for single port modulation. The output of the phase locked loop is connected to a power amplifier (PA) 68 and works well for constant envelope modulation schemes.

[0056] Figure 4 A block diagram of the receive circuit 36 is shown. A wireless signal first enters the receive circuit 36 through an antenna 37. The antenna 37 is in electrical communication with a low noise amplifier (LNA) 51. The LNA 51 receives a very weak signal from the antenna 37 and amplifies the signal while maintaining the signal-to-noise ratio (SNR) of the input signal. The amplified signal is then passed to a mixer 52. The mixer is also in communication with a receive phase locked loop 53 that provides two phases to the mixer. The cosine of the frequency can be referred to as the I o signal, while the sine of the frequency can be referred to as the Q o signal. The I o signal is then multiplied by the input signal to produce an in-phase signal I m . The Q o signal, which is delayed by 90° with respect to the I o signal, is then multiplied by the input signal to produce a quadrature signal Q m . The in-phase signal I m and the quadrature signal Qm are fed into a programmable gain amplifier (PGA) 54. The PGA 54 amplifies the I m and Q m signals by a programmable amount, and can provide low pass filtering. These amplified and filtered signals are referred to as I g and Q g . The amplified and filtered signals I g and Q g are then fed from the PGA 54 to an analog to digital converter (ADC) 55. The ADC 55 converts these analog signals to digital signals I d and Q d . These digital signals can pass through a channel filter 56, and then exit the radio circuit 31 as I and Q. In some embodiments, the I and Q values can be considered to be complex numbers, where the I value is the real component and the Q value is the imaginary component.

[0057] The I and Q signals then enter a Coordination Rotation Digital Computer (CORDIC) or similar circuit, which determines the amplitude and phase of the signal. The amplitude is given by the square root of I 2 and Q 2 , and the phase is given by tan -1 (Q / I). The CORDIC can be configured in the radio circuit 31, or elsewhere within the network interface 30.

[0058] As noted above, in order to accurately perform the channel sounding calculations, (θ I，T - θ I，R 0 + (θ R，T - θ R，R ) must remain constant for both frequencies. This can be accomplished by ensuring a known relationship between the phase of the transmitter transmit clock and the phase of the transmitter receive clock, and between the phase of the reflector transmit clock and the phase of the reflector receive clock. The transmit clock can be the output of a transmit phase locked loop 69. The receive clock can be the output of a receive phase locked loop 53.

[0059] Unfortunately, in most current implementations, there is a phase ambiguity between the transmit circuit 38 and the receive circuit 36. This is typically a result of independent frequency dividers used in the transmit circuit 38 and the receive circuit 36, which divide the clock output of the phase locked loops for use within these respective blocks. Specifically, each time the network device is powered up, these frequency dividers can power up in different states, which results in an unknown phase relationship between the transmit clock and the receive clock.

[0060] One mechanism that can be used to achieve a known phase relationship is to use the same clock generation circuit for the transmit phase-locked loop 69 in the transmit circuit 38 and the receive phase-locked loop 53 in the receive circuit 36.

[0061] Figure 5A One such clock generation circuit 500 is shown in FIG. 5. The circuit includes a signal source 200 that generates an input signal for a phase / frequency detector and charge pump (PFDCP) 210. Various devices, circuits, or blocks can be used to implement the signal source 200. Examples include a crystal (XTAL) oscillator, a resistor capacitor (RC) oscillator, an inductor capacitor (LC) oscillator, and other suitable devices. Generally, the signal source 200 outputs a REFCLK signal to the PFDCP 210. The PFDCP 210 receives a second input signal from a multimode divider (MMD) 250.

[0062] The PFDCP 210 provides an output signal to a loop filter (LF) 220. The loop filter (LF) 220 filters the signal received from the PFDCP 220 and provides the resulting filtered signal to a VCO 230. In other words, the output signal of the loop filter (LF) 220 is used as a voltage control signal for the VCO 230.

[0063] The voltage controlled oscillator (VCO) 230 generates an output signal having a particular frequency based on the input from the loop filter (LF) 220. In other words, the frequency of the output signal of the VCO 230 depends on the voltage level of the control signal from the loop filter 220. Thus, changes in the control signal from the loop filter (LF) 220 cause corresponding changes in the frequency of the output signal of the VCO 230.

[0064] While Figures 5A-5CA VCO 230 is shown, but other embodiments are possible. For example, a digitally controlled oscillator can also be used for a digital PLL implementation. In this embodiment, the phase / frequency detector and charge pump are replaced by a time-to-digital converter (TDC), and the loop filter has a digital output. In other words, the VCO is replaced by an L-C oscillator that has a digital word from the loop filter to replace the control voltage. In a general sense, this also applies to ring oscillator applications, and can be a voltage controlled oscillator or a current controlled oscillator. Thus, in this embodiment, the voltage controlled oscillator is replaced by an L-C oscillator, and the output of the loop filter is changed accordingly. In all embodiments, there is a detector that compares the phase of the REFCLK and the feedback signal and produces an output based on the difference. This detector can be a phase / frequency detector and charge pump in an analog PLL or a TDC in a digital PLL. Further, in these embodiments, there is a loop filter that receives the output from the detector and generates a filtered output. This loop filter can output a voltage for use with a VCO, or it can output a digital word for use with a digitally controlled oscillator.

[0065] Further, other embodiments are possible. For example, the phase / frequency detector and charge pump can be used with a digitally controlled oscillator by inserting an analog-to-digital converter before the digitally controlled oscillator. Further, the TDC can be used with a voltage controlled oscillator by inserting a digital-to-analog converter before the voltage controlled oscillator.

[0066] The output signal of the VCO 230 is then provided to a buffer 270. The output signal of the buffer 270 is used as an input to a multi-modulus divider (MMD) 250. In some embodiments, the output from the buffer 270 can be further buffered before reaching the multi-modulus divider 250. The multi-modulus divider 250 can be implemented in a number of ways. Further, various types of multi-modulus dividers (MMDs) 250 can be used, such as dividers suitable for use in a fractional-N frequency synthesizer. In other embodiments, different types or architectures of multi-modulus dividers (MMDs) 250 can be used. As described above, the multi-modulus divider (MMD) 250 divides the VCO 230 by a desired factor, which can be fractional or integer, to generate an output signal that is provided as a second input to the PFDCP 210. Further, in some embodiments, the multi-modulus divider (MMD) 250 is simply an integer divider.

[0067] PFDCP 210, loop filter (LF) 220, VCO 230, buffer 270, and multi-mode divider (MMD) 250 form a phase-locked loop. As described above, the phase-locked loop can also be a digitally controlled loop. In each embodiment, the phase-locked loop can include a detector, a loop filter, an oscillator, and a multi-mode divider (MMD) 250.

[0068] In operation, the clock generation circuit attempts to minimize the phase difference between the REFCLK signal from the signal source 200 and the output of the multi-mode divider (MMD) 250 (also known as the feedback signal). Thus, the output of the VCO 230, also known as F VCO , may be equal to Q*REFCLK, where Q is a factor used by the multi-modulus divider (MMD) 250 .

[0069] The output of buffer 270 is also provided to divider 240, which divides the output signal of VCO 230 by a desired amount. This amount can be an integer or N.5, where N is an integer. For example, in some embodiments, divider 240 can divide the output signal of VCO 230 by 4 or by 2.5. In other embodiments, different integer factors can be used. In some embodiments, using an N.5 divider can help couple the power amplifier (PA) to the VCO because the frequencies are not harmonically related.

[0070] The output from the frequency divider 240 is provided as an input to a quadrature signal generator 260, which generates one or more signals as output signals of the quadrature signal generator. In the illustrated embodiment, the quadrature signal generator 260 provides two sets of output signals, one set provided to the receive circuit 36 ​​and the second set provided to the transmit circuit 38, although other numbers of output signals may be generated and used. For example, the first set of output signals may be shown as Figure 4 The output of the receiving phase-locked loop 53 is I o and Q o The second set of output signals can be shown as Figure 3A The output of the transmit phase-locked loop 69 is I lo and Q lo Signal.

[0071] The input to the quadrature signal generator 260 is phase ambiguous because the frequency divider 240 can be initialized in one of several possible states. The quadrature signal generator 260 utilizes only shift registers and combinatorial logic, therefore, the output of the quadrature signal generator 260 will always have a known phase difference between the clock used by the receive circuitry 36 and the clock used by the transmit circuitry 38, however, the phase difference can vary from activation to activation. In other words, the transmit and receive quadrature generation circuitry configured in the quadrature signal generator 260 and using the same shift registers can provide local oscillators for the transmit and receive mixers for upconversion and downconversion. In the present embodiment, the clocks used by the receive circuitry 36 and the transmit circuitry 38 must utilize the same shift registers within the quadrature signal generator 260.

[0072] As described in greater detail below, the quadrature generation circuitry can provide a 2 / 4 / 8 way mixer with a signal that employs a 50 / 25 / 12.5% duty cycle where F VCO is equal to twice or four times the local oscillator frequency (F LO ). Of course, other embodiments are possible depending on the relationship between F VCO and F LO . Generally, F VCO = N*F LO , where N can be an integer or fractional relationship. For example, if N is equal to 3, then the quadrature generation circuitry produces a duty cycle of 33%. Similarly, if N is 2.5, then the quadrature generation circuitry produces a duty cycle of 40%. Thus, the present disclosure is not limited to a particular relationship between F VCO and F LO or a particular duty cycle.

[0073] Figure 5B A second embodiment of the clock generation circuitry 501 is shown. All like elements are given the same reference number and therefore are not described again. In the present embodiment, the frequency divider 241 has a reset signal. In the present embodiment, the phase of the frequency divider 241 is deterministic after the reset is released.

[0074] The use of the reset signal of the frequency divider 241 allows for the use of separate shift registers in the quadrature signal generator 260 if desired. When the reset signal is asserted, a known value is shifted through the shift registers in the quadrature signal generator 260 such that when the reset is released, the two shift registers will have the same state. In this way, the frequency of the clock signal of the receive circuitry 36 can be different from the frequency of the clock signal of the transmit circuitry 38. For example, the clock of the transmit circuitry 38 can be twice the frequency of the receive circuitry 36.

[0075] Figure 5CA third embodiment of a clock generation circuit 502 is shown. All similar components are given the same reference numerals and will not be described again. In this embodiment, the output of buffer 270 serves as the input to two different frequency dividers 241a and 241b. These frequency dividers 241a and 241b can utilize the same factor or different factors. As described above, the factor can be an integer or N.5, where N is an integer. The output of frequency divider 241a serves as the input to a transmit quadrature signal generator 260a for generating a transmit clock. The output of frequency divider 241b serves as the input to a receive quadrature signal generator 260b for generating a receive clock. Both frequency dividers 241a and 241b include a reset signal so that each frequency divider can be initialized to a known state. This creates a known phase relationship between the transmit and receive clocks. The transmit and receive quadrature circuits can be any of the circuits described below.

[0076] Figure 6A A first embodiment of a quadrature signal generator 260 is shown. In this embodiment, a buffer 270 is also shown. The output of the VCO (clk) is used to alternately clock a shift register 261. The input to this shift register is the output from the frequency divider 241, which in this embodiment is a divide-by-4 circuit. The output of each stage of the shift register 261 also serves as the first input to an AND gate 262, where the second input is the output from a different stage of the shift register 261. The result is a set of signals that are spaced 90° apart and have a 25% duty cycle. Figure 6B A timing diagram associated with this circuit is shown in Thus, in this embodiment, VCO 230 operates at four times the transmit and receive clock frequencies.

[0077] Note that if eight latches are used that are clocked alternately with the clk signal and its complement, an output with a 12.5% ​​duty cycle can be produced.

[0078] The quadrature signal generator 260 may have other configurations. For example, the frequency divider 241 may be a divide-by-2 circuit. Figure 7A One such configuration is shown in FIG. In this configuration, the shift register 263 includes four latches that are alternately clocked by the output of the VCO 230 (clk) and the complement of that signal (clkb). In this embodiment, the output from the latches in the shift register 263 is used directly as the transmit clock; specifically, as Figure 3A I shown lo and Q lo Signals and the complement of these signals. A plurality of AND gates 264 are used to generate signals for the receiving circuit, said signals including Figure 4 I shown o and Q oand complements thereof. Each signal has a 25% duty cycle. A timing diagram of this configuration is shown in Figure 7B

[0079] Thus, as shown in Figures 7A-7B the duty cycle of the transmit clock and the receive clock can be different. For example, the transmit clock can be generated without the use of an AND gate 264 and thus have a duty cycle twice that of the receive clock.

[0080] Further, as shown in Figure 8A the transmit clock can be generated without the use of a shift register. In this embodiment, the divider 241 is a 2x divider. The transmit clock can be generated directly from the output of the divider 241 while the receive clock utilizes a shift register 263 and an AND gate 264 as shown in Figure 8A Figure 8B A timing diagram of this configuration is shown in FIG. 3. As shown in Figure 3B this technique is useful for direct transmission of a PLL architecture.

[0081] Note that other embodiments are possible. While an AND gate 264 is shown, note that other combinational logic can be used. However, in all embodiments, a non-ambiguous implementation using a shift register and combinational logic is possible.

[0082] Figures 5A-5C The clock generation circuits shown in FIG. 3 can be used in time-division multiplexed applications such that the transmit circuit 38 is active at certain points in time or the receive circuit is active at certain points in time. Further, these clock generation circuits are suitable for continuous operation mode and packet operation mode. For completeness, Figures 5A-5C the circuits in FIG. 3 can also be suitable for full-duplex operation where both the receive circuit 36 and the transmit circuit 38 are active at the same time and at the same carrier frequency.

[0083] However, in certain embodiments, the network protocol can utilize a frequency-division multiplexing scheme where both the receive circuit 36 and the transmit circuit 38 are active at the same time but at different frequencies. Further, in certain embodiments, the network protocol can utilize a simultaneous dual-radio operation where there is no restriction on the transmit and receive frequencies. All of these modes are supported by the clock generation circuits shown in Figure 9 and described below.

[0084] Unfortunately, in most frequency-division multiplexed implementations, there is a phase ambiguity between the transmit circuit 38 and the receive circuit 36. This is a result of utilizing two different phase-locked loops with dividers that can power up in any of a number of different states. Specifically, each time a network device powers up, these dividers can power up in different states, which results in an unknown relationship between the transmit clock and the receive clock.

[0085] ​​Figure 9 A clock generation circuit 503 that can be used in a frequency division multiplexing application is shown. In this embodiment, the signal source 200 is used to drive two separate clock generation circuits, each of which is similar to the clock generation circuit 501 shown in Figure 5B The transmit clock generation circuit includes the PFDCP 210a, the loop filter (LF) 220a, the VCO 230a, the buffer 270a, the frequency divider 241a, and the MMD 250a. These components are as described above. The output of the frequency divider 241a is also used as an input to the transmit quadrature signal generator 260a.

[0086] Similarly, the receive clock generation circuit includes the PFDCP 210b, the loop filter (LF) 220b, the VCO 230b, the buffer 270b, the frequency divider 241b, and the MMD 250b. The output of the frequency divider 241b is also used as an input to the receive quadrature signal generator 260b.

[0087] Note that in some embodiments, both circuits can utilize phase-locked loops having the same architecture. However, in other embodiments, the architecture of the two circuits can be different. For example, one can implement an analog PLL, while the other implements a digital PLL. Thus, one can include a phase / frequency detector and a charge pump, while the other includes a TDC.

[0088] In this embodiment where there are separate clock generation circuits, the MMDs 250a, 250b are both integer dividers. The frequency dividers 241a and 241b can both be reset using the same reset signal at initialization. In other embodiments, separate reset signals can be used, so long as they ensure that the phases of the dividers are aligned. In this way, the outputs of the dividers have a known relationship to each other. In addition, the frequency dividers 241a and 241b can divide the signals from the respective VCOs by the same integer or by different integers. For example, the frequency divider 241a can divide the VCO output by M, while the frequency divider 241b can divide the VCO output by N, where M and N can be the same or different quantities, such as an integer or N.5, where N is an integer.

[0089] The two quadrature signal generators can be configured according to any of the embodiments described above. For example, the receive quadrature signal generator 260b can generate a signal having a 12.5%, 25%, or 50% duty cycle. The transmit quadrature signal generator 260a can generate a signal having a 12.5%, 25%, or 50% duty cycle. In general, depending on the relationship F VCO = N*F LOOther implementations of the duty cycle generation are possible, where N can be an integer or even a fractional relationship, for example, N = 2.5. However, in all embodiments, a non-ambiguous implementation using shift registers and combinational logic is possible.

[0090] Each of the configurations shown herein ensures a constant offset between the clocks used in the transmit circuit 38 and the receive circuit 36. In this way, the channel sounding process can be performed with the assurance of accuracy in the calculations. Thus, in one embodiment, the channel sounding calculations are performed using two network devices, both of which contain Figures 5A-5C or Figure 9 the clock generation circuit described. The first network device transmits a first data packet to the second network device using a first frequency. The second network device then responds to the first data packet by transmitting a second data packet to the first network device using the first frequency. The first network device then transmits a third data packet to the second network device using a second frequency that is different from the first frequency. The second network device then responds to the third data packet by transmitting a fourth data packet to the first network device using the second frequency. Due to the use of the clock generation circuit described herein, (θ I，T - θ I，R ) is constant for the first network device and (θ R，T - θ R，R ) is constant for the second network device. Thus, the distance between the two devices can be reliably calculated.

[0091] The scope of the disclosure is not limited to the specific embodiments described herein. Indeed, other various embodiments and modifications of the disclosure, apart from those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Accordingly, such other embodiments and modifications are intended to fall within the scope of the disclosure. Further, although the disclosure is described herein in the context of particular implementations for particular purposes in a particular environment, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that it can be beneficially implemented in any number of environments for any number of purposes. Thus, the claims set forth below are to be construed in accordance with the full scope and spirit of the disclosure as described herein.

[0092] This application claims priority to U.S. Patent Application 17 / 550,417, filed December 14, 2021, the disclosure of which is incorporated in its entirety herein.

Claims

1. A clock generation circuit for measuring the distance between two devices, comprising: A signal source, used for providing a reference clock REFCLK signal; Phase-locked loop, including: a detector for determining a difference between the reference clock REFCLK signal and a feedback signal and providing an output based on the difference; a loop filter for filtering the output to generate a filtered output; an oscillator for generating a clock signal having a frequency related to the filtered output; a buffer for buffering the clock signal; and a multi-mode frequency divider in communication with an output of the buffer for dividing the frequency of the output of the oscillator and providing the feedback signal to the detector; a frequency divider in communication with an output of the buffer for dividing the clock signal by a certain amount; and a quadrature signal generator in communication with an output of the frequency divider; wherein the quadrature signal generator outputs a transmit clock and a receive clock, and wherein a phase difference between the transmit clock and the receive clock is constant; and The frequency divider includes a reset signal to initialize the frequency divider to a known state.

2. The clock generation circuit according to claim 1, wherein: The quadrature signal generator includes a shift register.

3. The clock generation circuit according to claim 2, wherein: The quadrature signal generator includes combinational logic, wherein the shift register and the combinational logic are used to generate the receiving clock and the transmitting clock.

4. The clock generation circuit according to claim 3, wherein: The receiving clock output by the quadrature signal generator has a duty cycle of 12.5%, 25% or 50%.

5. The clock generation circuit according to claim 2, wherein: The shift register is used to generate the transmit clock, and the transmit clock output by the quadrature signal generator has a duty cycle of 12.5%, 25% or 50%. The clock generation circuit according to claim 1 , wherein: The detector includes a phase / frequency detector and a charge pump; and the oscillator includes a voltage controlled oscillator, and the output from the phase / frequency detector and charge pump and the loop filter is a voltage.

7. The clock generation circuit according to claim 1, wherein: The detector comprises a time-to-digital converter, the output from the loop filter comprises a digital word, and the oscillator comprises a numerically controlled oscillator.

8. A clock generation circuit for measuring the distance between two devices, comprising: A signal source, used for providing a reference clock REFCLK signal; Phase-locked loop, including: a detector for determining a difference between the reference clock REFCLK signal and a feedback signal and providing an output based on the difference; a loop filter for filtering the output to generate a filtered output; an oscillator for generating a clock signal having a frequency related to the filtered output; a buffer, configured to buffer the clock signal; a multi-mode frequency divider in communication with an output of the buffer for dividing the frequency of the output of the oscillator and providing the feedback signal to the detector; a frequency divider in communication with an output of the buffer for dividing the clock signal by an amount; wherein the frequency divider includes a reset signal to initialize the frequency divider to a known state; and a second frequency divider in communication with an output of the buffer for dividing the clock signal by a second amount, wherein the second frequency divider includes a reset signal, so as to initialize the second frequency divider to a known state; and The output of the frequency divider is used as an input of a transmit quadrature signal generator to generate a transmit clock, and the output of the second frequency divider is used as an input of a receive quadrature signal generator to generate a receive clock, so that the phase difference between the transmit clock and the receive clock is constant.

9. The clock generation circuit according to claim 8, wherein: The detector includes a phase / frequency detector and a charge pump; and the oscillator includes a voltage controlled oscillator, and the output from the phase / frequency detector and charge pump and the loop filter is a voltage.

10. The clock generation circuit according to claim 8, wherein: The detector comprises a time-to-digital converter, the output from the loop filter comprises a digital word, and the oscillator comprises a numerically controlled oscillator.

11. A method for performing distance measurement between a first network device and a second network device, comprising: transmitting a first data packet from the first network device to the second network device using a first frequency; responding to the first data packet by transmitting a second data packet from the second network device to the first network device using the first frequency; transmitting a third data packet from the first network device to the second network device using a second frequency different from the first frequency; responding to the third data packet by transmitting a fourth data packet from the second network device to the first network device using the second frequency; as well as calculating a distance based on a phase, the first frequency, and the second frequency for each data packet received by the first network device and the second network device, The first network device and the second network device each include a clock generation circuit, which has a phase-locked loop and at least one frequency divider configured outside the phase-locked loop to generate a receiving clock and a transmitting clock, so that the phase difference between the transmitting clock and the receiving clock of each network device is constant.

12. The method according to claim 11, wherein The clock generation circuit comprises: A signal source, used for providing a reference clock REFCLK signal; The phase-locked loop comprises: a detector for determining a difference between the reference clock REFCLK signal and a feedback signal and providing an output based on the difference; a loop filter for filtering the output to generate a filtered output; an oscillator for generating a clock signal having a frequency related to the filtered output; a buffer for buffering the clock signal; and a multi-mode frequency divider in communication with an output of the buffer for dividing the frequency of the output of the oscillator and providing the feedback signal to the detector; and The at least one frequency divider is in communication with an output of the buffer and is configured to divide the clock signal by a certain amount.

13. The method according to claim 12, wherein: The at least one frequency divider includes a reset signal to initialize the frequency divider to a known state.

14. The method according to claim 12, wherein: The detector includes a phase / frequency detector and a charge pump; and the oscillator includes a voltage controlled oscillator, and the output from the phase / frequency detector and charge pump and the loop filter is a voltage.

15. The method according to claim 12, wherein: The detector comprises a time-to-digital converter, the output from the loop filter comprises a digital word, and the oscillator comprises a numerically controlled oscillator.

16. The method according to claim 11, wherein The clock generation circuit further includes a quadrature signal generator in communication with an output of the at least one frequency divider for generating the receive clock and the transmit clock.

17. A clock generation circuit for measuring the distance between two devices, comprising: a receiving clock generation circuit; as well as Transmit clock generation circuit; as well as A signal source, used for providing a reference clock REFCLK signal; The receiving clock generating circuit and the transmitting clock generating circuit each include: Phase-locked loop, including: a detector for determining a difference between the reference clock REFCLK signal and a feedback signal and providing an output based on the difference; a loop filter for filtering the output to generate a filtered output; an oscillator for generating a clock signal having a frequency related to the filtered output; a buffer for buffering the clock signal; and a multi-modulus frequency divider in communication with an output of the buffer for dividing the output of the oscillator by an integer and providing the feedback signal to the detector; and a frequency divider in communication with an output of the buffer and configured to divide the clock signal by a certain amount; wherein the frequency divider includes a reset signal to initialize the frequency divider to a known state; The transmit clock is generated based on the output of the frequency divider in the transmit clock generation circuit, and the receive clock is generated based on the output of the frequency divider in the receive clock generation circuit, and the phase difference between the transmit clock and the receive clock is constant.

18. The clock generation circuit according to claim 17, wherein: At least one of the detector of the receive clock generation circuit or the detector of the transmit clock generation circuit includes a phase / frequency detector and a charge pump; and the oscillator includes a voltage-controlled oscillator, and the output from the phase / frequency detector and charge pump and the loop filter is a voltage.

19. The clock generating circuit according to claim 17, wherein: At least one of the detector of the receive clock generation circuit or the detector of the transmit clock generation circuit comprises a time-to-digital converter, the output from the loop filter comprises a digital word, and the oscillator comprises a digitally controlled oscillator.

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