Image sensor, readout circuit therefor, and electronic device

Abstract

The application discloses an image sensor, a readout circuit thereof and electronic equipment, wherein the readout circuit of the image sensor comprises: a conversion circuit which converts a received reset signal and an image signal into corresponding current signals, and takes a difference between the current signals of the reset signal and the image signal as a discharge current of an output terminal; the conversion circuit also generates a bias reference current according to a bias reference voltage signal, and the bias reference current is taken as a charging current of the output terminal of the conversion circuit; a comparison circuit compares a charging voltage generated by the charging current and the discharge current output by the conversion circuit with a comparison reference voltage signal; and a feedback circuit outputs a feedback signal to the conversion circuit according to a comparison result of the comparison circuit, so as to control the output or non-output of the bias reference current, thereby determining the intensity of an effective image signal according to the charge conservation and the duty cycle of the feedback signal output by the feedback circuit. The application can improve the image readout speed of the image sensor and has low power consumption.

Description

Technical Field

[0001] This application relates to the field of image technology, and in particular to an image sensor, its readout circuit, and electronic equipment. Background Technology

[0002] Image sensors are a crucial component of digital cameras, converting optical images into electrical signals. They are widely used in digital cameras, mobile terminals, portable electronic devices, and other electronic equipment. Image sensors are broadly classified into two categories: CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors. CMOS image sensors, with their advantages of high integration, low power consumption, high speed, and low cost, are widely used in many products, including mobile phones, tablets, automobiles, and security monitoring systems.

[0003] As smartphones demand increasingly diverse functionalities from their front-facing cameras, particularly in situations where the front camera is always on to detect and process gestures and facial movements, CMOS image sensors are required to not only transmit images but also meet design requirements such as high processing speed and low power consumption. Currently, the analog-to-digital converter (ADC) readout circuit of CMOS image sensors requires subtracting the quantized signals of the reset signal and the image signal twice to complete the relevant double sampling process.

[0004] The ADC readout circuit with the above structure has a slow processing speed, and the two quantization processes increase power consumption.

[0005] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0006] The purpose of this application is to provide an image sensor, its readout circuit and electronic device, which can improve the image readout speed of the image sensor and has low power consumption.

[0007] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0008] In a first aspect, embodiments of this application provide an image sensor, including: a conversion circuit, a comparison circuit, and a feedback circuit, wherein;

[0009] The conversion circuit has a first input terminal for receiving a reset signal and an image signal, and a second input terminal for receiving a bias reference voltage signal. The conversion circuit converts the received reset signal and image signal into corresponding current signals, and uses the difference between the current signals corresponding to the reset signal and the image signal as the discharge current at its output terminal. The conversion circuit also generates a bias reference current based on the bias reference voltage signal, and the bias reference current serves as the charging current at the output terminal of the conversion circuit.

[0010] The first input terminal of the comparator circuit is connected to the output terminal of the conversion circuit, and the second input terminal of the comparator circuit receives a comparison reference voltage signal. The comparator circuit compares the charging voltage generated by the charging current and the discharging current output by the conversion circuit with the comparison reference voltage signal.

[0011] The feedback circuit is connected to the output of the comparison circuit and is used to output a feedback signal to the conversion circuit according to the comparison result of the comparison circuit, so as to control the output or non-output of the bias reference current, thereby determining the strength of the effective image signal based on charge conservation and the duty cycle of the feedback signal output by the feedback circuit.

[0012] Optionally, the conversion circuit further includes:

[0013] A current difference generation circuit receives the reset signal and the image signal through the first input terminal of the conversion circuit, converts the received reset signal and image signal into corresponding current signals, and generates the difference between the current signals corresponding to the reset signal and the image signal; and

[0014] A bias reference current generating circuit is connected to the current difference generating circuit. The bias reference current generating circuit receives the bias reference voltage signal through the second input terminal of the conversion circuit and generates the bias reference current according to the bias reference voltage signal.

[0015] Optionally, the current difference generating circuit further includes:

[0016] The mirror input circuit receives the reset signal and the image signal through the first input terminal of the conversion circuit, converts the received reset signal and the image signal into corresponding current signals, and then converts them into corresponding voltage signals through mirror bias.

[0017] The switch selection circuit receives the reset signal and image signal output by the mirror input circuit in sequence through the switch control signal;

[0018] A mirror sampling circuit is connected to the mirror input circuit and the switch selection circuit. The mirror sampling circuit samples and stores the reset signal output by the switch selection circuit, and converts the difference between the reset signal and the image signal subsequently output by the switch selection circuit into the difference of the corresponding current signal through mirror bias, so as to serve as the discharge current at the output of the conversion circuit.

[0019] Optionally, the mirror input circuit includes a signal input transistor, an input load, and a first mirror bias circuit, wherein:

[0020] The signal input transistor has a first terminal for receiving the reset signal and the image signal in sequence, and the second terminal of the signal input transistor is connected to the first mirror bias circuit.

[0021] The input load is connected between the third terminal of the signal input transistor and ground; and

[0022] The first mirror bias circuit is used to mirror the reset signal and the image signal, so as to output the mirror-biased reset signal and the image signal to the switch selection circuit.

[0023] Optionally, the first mirror bias circuit includes a plurality of first transistors, the plurality of first transistors including a first PMOS transistor (P0), a second PMOS transistor (P1), a third PMOS transistor (P2), and a fourth PMOS transistor (P3). The first terminal of the first PMOS transistor (P0) receives a first bias voltage, the second terminal of the first PMOS transistor (P0) is connected to the first terminal of the second PMOS transistor (P1), and the third terminal of the first PMOS transistor (P0) is connected to the second terminal of the second PMOS transistor (P1). The third terminal of the second PMOS transistor (P1) is connected to a power supply. The first terminal of the third PMOS transistor (P2) receives the first bias voltage, the second terminal of the third PMOS transistor (P2) is connected to the switch selection circuit, and the third terminal of the third PMOS transistor (P2) is connected to the second terminal of the fourth PMOS transistor (P3). The first terminal of the fourth PMOS transistor (P3) receives the first bias voltage, and the third terminal of the fourth PMOS transistor (P3) is connected to a power supply.

[0024] Optionally, the switch selection circuit includes:

[0025] A reset signal switching transistor is used to control the input of a reset signal. The first terminal of the reset signal switching transistor receives a reset switch signal, the second terminal of the reset signal switching transistor is connected to the mirror sampling circuit, and the third terminal of the reset signal switching transistor is connected to the mirror input circuit.

[0026] An image signal switching transistor is used to control the input of an image signal. The first terminal of the image signal switching transistor receives an image switching signal, the second terminal of the image signal switching transistor is connected to a comparator circuit, and the third terminal of the image signal switching transistor is connected to the third terminal of the reset signal switching transistor.

[0027] Optionally, the mirror sampling circuit includes:

[0028] A sampling circuit, connected to the switch selection circuit, is used to sample the reset signal; and

[0029] The second mirror bias circuit, connected to the switch selection circuit and the sampling circuit, is used to convert the reset signal sampled by the sampling circuit and the image signal subsequently output by the switch selection circuit into the difference between the current signals corresponding to the reset signal and the image signal through mirror bias.

[0030] Optionally, the second mirror bias circuit includes a plurality of second transistors, the plurality of second transistors including a first NMOS transistor (N0), a second NMOS transistor (Nirst0), a third NMOS transistor (N1), and a fourth NMOS transistor (Nirst1). The first terminal of the first NMOS transistor (N0) receives a second bias voltage, the second terminal of the first NMOS transistor (N0) is connected to a sampling circuit, and the third terminal of the first NMOS transistor (N0) is connected to the second terminal of the second NMOS transistor (Nirst0). The first terminal of the third NMOS transistor (N1) receives the second bias voltage, the second terminal of the third NMOS transistor (N1) is connected to a comparator circuit, and the third terminal of the third NMOS transistor (N1) is connected to the second terminal of the fourth NMOS transistor (Nirst1). The first terminal of the second NMOS transistor (Nirst0) is connected to the first terminal of the fourth NMOS transistor (Nirst1), the third terminal of the second NMOS transistor (Nirst0) is grounded, and the third terminal of the fourth NMOS transistor (Nirst1) is grounded.

[0031] Optionally, the sampling circuit includes a sampling switch and a sampling capacitor. The first terminal of the sampling switch receives the sampling voltage, the second terminal of the sampling switch is connected to a second mirror bias circuit, and the third terminal of the sampling switch is connected to the first terminals of the second NMOS transistor (Nirst0) and the fourth NMOS transistor (Nirst1) and grounded through the sampling capacitor.

[0032] Optionally, the bias reference current generating circuit further includes:

[0033] A plurality of first transistors are configured to receive the bias reference voltage signal and generate the bias reference current; and

[0034] A reference current switching transistor is used to receive feedback signals from the feedback circuit to control the output of the bias reference current.

[0035] Optionally, the plurality of first transistors includes a fifth PMOS transistor (P4) and a sixth PMOS transistor (Prist). The first terminal of the fifth PMOS transistor (P4) receives a first bias voltage, the second terminal of the fifth PMOS transistor (P4) is connected to the third terminal of a reference current switching transistor, and the third terminal of the fifth PMOS transistor (P4) is connected to the second terminal of the sixth PMOS transistor (Prist). The first terminal of the sixth PMOS transistor (Prist) receives a bias reference voltage signal, the third terminal of the sixth PMOS transistor (Prist) is connected to a power supply, the first terminal of the reference current switching transistor is connected to a feedback circuit, the second terminal of the reference current switching transistor is connected to a comparator circuit, and the third terminal of the reference current switching transistor is connected to the second terminal of the fifth PMOS transistor (P4).

[0036] Optionally, the conversion circuit further includes: a compensation current generating circuit for generating a compensation current as the discharge current at the output terminal of the conversion circuit.

[0037] Optionally, the compensation current generating circuit further includes: a plurality of second transistors for receiving a compensation voltage signal to generate the compensation current, the plurality of second transistors including a fifth NMOS transistor (N2) and a sixth NMOS transistor (Niofs), the first terminal of the fifth NMOS transistor (N2) receiving a second bias voltage, the second terminal of the fifth NMOS transistor (N2) being connected to a comparator circuit, the third terminal of the fifth NMOS transistor (N2) being connected to the second terminal of the sixth NMOS transistor (Niofs); the first terminal of the sixth NMOS transistor (Niofs) receiving the compensation voltage, and the third terminal of the sixth NMOS transistor (Niofs) being grounded.

[0038] Optionally, the comparison circuit includes:

[0039] A comparator, whose first input is connected to the output of the conversion circuit, whose second input receives the comparison reference voltage signal, and whose output is connected to the feedback circuit; and

[0040] A first capacitor is connected between the first input terminal of the comparator and ground, and is used to store the charge generated by the charging current and discharging current output by the conversion circuit to generate a charging voltage at the first input terminal of the comparator.

[0041] Optionally, the comparison circuit further includes a second capacitor connected between the output terminal of the comparator and the feedback circuit, for storing the voltage signal output by the comparator to control the feedback circuit to flip.

[0042] Optionally, the feedback circuit includes a flip-flop connected to the comparator circuit, used to sample the output signal of the comparator circuit according to the clock signal and output the feedback signal. The input terminal of the flip-flop is connected to the comparator circuit, the clock terminal of the flip-flop receives the clock signal, and the output terminal of the flip-flop is connected to the conversion circuit.

[0043] Optionally, the feedback circuit further includes several inverters connected to the output of the comparator circuit and / or the output of the flip-flop, for pulse shaping of the output signal of the comparator circuit and / or the feedback signal output by the flip-flop.

[0044] Optionally, the plurality of inverters includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The input terminal of the first inverter is connected to the output terminal of a flip-flop, and the output terminal of the first inverter is connected to a conversion circuit. The input terminal of the second inverter is connected to a comparator circuit, and the output terminal of the second inverter is connected to the input terminal of the flip-flop. The input terminal of the third inverter is connected to the output terminal of the flip-flop, and the output terminal of the third inverter is connected to the input terminal of the fourth inverter.

[0045] Secondly, embodiments of this application provide an image sensor, which includes: a pixel array comprising a plurality of pixels arranged in rows and columns;

[0046] A control circuit, connected to the pixel array, is used to control the pixel array to output a reset signal and an image signal; and

[0047] The readout circuit described above is connected to the pixel array and is used to read the reset signal and image signal output by the pixel array to determine the strength of the valid image signal.

[0048] Thirdly, embodiments of this application provide an electronic device, including the image sensor described above.

[0049] The beneficial effects of the technical solutions provided in this application are:

[0050] The image sensor, readout circuit, and electronic device provided in this application embodiment convert the received reset signal and image signal into corresponding current signals through a conversion circuit. The difference between the current signals corresponding to the reset signal and the image signal is used as the discharge current at the output terminal. The conversion circuit also generates a bias reference current based on a bias reference voltage signal, which serves as the charging current at the output terminal of the conversion circuit. A comparison circuit compares the charging current and the charging voltage generated by the discharge current output by the conversion circuit with the comparison reference voltage signal. A feedback circuit outputs a feedback signal based on the comparison result of the comparison circuit and feeds it back to the conversion circuit to control the output or non-output of the bias reference current. Thus, the strength of the effective image signal is determined based on charge conservation and the duty cycle of the feedback signal output by the feedback circuit. This allows the reset signal and image signal to be converted into current signals for sampling. Furthermore, only one quantization process is needed to achieve the same effect as two quantization processes in traditional structures, accelerating the signal quantization speed, improving the image readout speed of the image sensor, and reducing power consumption. Attached Figure Description

[0051] Figure 1 This is a structural block diagram of an image sensor provided in an embodiment of this application;

[0052] Figure 2 for Figure 1 Block diagram of the readout circuit;

[0053] Figure 3 for Figure 1 The circuit diagram of the readout circuit;

[0054] Figure 4 for Figure 1 Image sensor control timing diagram. Detailed Implementation

[0055] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to limit this application.

[0056] Figure 1 This is a structural block diagram of an image sensor provided in an embodiment of this application. Figure 2 for Figure 1 The block diagram of the readout circuit. Figure 3 for Figure 1 The circuit diagram of the readout circuit. Figure 4 for Figure 1 The image sensor control timing diagram is shown below. Please refer to it. Figures 1 to 4The image sensor in this embodiment includes a pixel array 101, a readout circuit 102 connected to the pixel array 101, and a control circuit 103.

[0057] Pixel array 101 includes multiple pixels arranged in rows and columns. Each column of pixels in pixel array 101 is connected by a column select line, and each row of pixels is connected by a row select line. Each pixel has a row address and a column address. Control circuit 103 controls the appropriate rows and columns in pixel array 101 to selectively output corresponding pixel output signals. The pixel signals output by pixel array 101 are output to readout circuit 102 via column lines. The pixel output signals include a pixel reset signal and a pixel image signal. The pixel reset signal represents the signal obtained by the floating diffusion region of the photosensitive device (such as a photodiode) during reset. The pixel image signal represents the signal obtained after the charge representing the image acquired by the photosensitive device is transferred to the floating diffusion region. Both the pixel reset signal and the pixel image signal are read and processed by readout circuit 102 to obtain a valid image signal.

[0058] like Figure 2 as well as Figure 3 As shown, the readout circuit of the image sensor includes a conversion circuit 100, a comparison circuit 200, and a feedback circuit 300.

[0059] The conversion circuit 100 has a first input terminal, vin, for receiving a reset signal and an image signal, and a second input terminal for receiving a bias reference voltage signal, pbias_ref. The conversion circuit 100 converts the received reset signal and image signal into corresponding current signals, and uses the difference between the current signals corresponding to the reset signal and the image signal as the discharge current at its output terminal. The conversion circuit 100 also generates a bias reference current, Iref, based on the bias reference voltage signal pbias_ref, and this bias reference current Iref serves as the charging current at the output terminal of the conversion circuit 100.

[0060] The first input terminal of the comparator circuit 200 is connected to the output terminal of the conversion circuit 100. The second input terminal of the comparator circuit 200 receives a comparison reference voltage signal vref. The comparator circuit 200 compares the charging voltage generated by the charging current and the discharging current output by the conversion circuit 100 with the comparison reference voltage signal vref.

[0061] The feedback circuit 300 is connected to the output of the comparator circuit 200 and is used to output a feedback signal to the conversion circuit 100 based on the comparison result of the comparator circuit 200, so as to control the output or non-output of the bias reference current Iref, thereby determining the strength of the effective image signal based on the charge conservation and the duty cycle of the feedback signal output by the feedback circuit 300.

[0062] In one embodiment, the conversion circuit 100 further includes a current difference generation circuit 110 and a bias reference current generation circuit 120.

[0063] The current difference generation circuit 110 receives a reset signal and an image signal through the first input terminal of the conversion circuit 100, converts the received reset signal and image signal into corresponding current signals, and generates the difference between the current signals corresponding to the reset signal and the image signal.

[0064] The bias reference current generating circuit 120 is connected to the current difference generating circuit 110. The bias reference current generating circuit 120 receives the bias reference voltage signal through the second input terminal of the conversion circuit 100 and generates the bias reference current according to the bias reference voltage signal.

[0065] In one embodiment, the current difference generating circuit 110 includes: a mirror input circuit 112, a switch selection circuit 114, and a mirror sampling circuit 116.

[0066] The mirror input circuit 112 receives the reset signal and the image signal through the first input terminal of the conversion circuit 100, converts the received reset signal and the image signal into corresponding current signals, and then converts them into voltage signals through mirror bias.

[0067] The switch selection circuit 114 receives the reset signal and image signal output from the mirror input circuit 114 in sequence through the switch control signal;

[0068] The mirror sampling circuit 116 is connected to the mirror input circuit 112 and the switch selection circuit 114. The mirror sampling circuit 116 samples and stores the reset signal output by the switch selection circuit 114, and converts the difference between the reset signal and the image signal subsequently output by the switch selection circuit 114 into the difference of the corresponding current signal through mirror bias, so as to serve as the discharge current at the output of the conversion circuit 100.

[0069] In one embodiment, the mirror input circuit 112 includes: a signal input transistor Nin, an input load R0, and a first mirror bias circuit.

[0070] The signal input transistor Nin has a first terminal for receiving a reset signal and an image signal in sequence, and a second terminal for connecting to a first mirror bias circuit. The input load R0 is connected between the third terminal of the signal input transistor Nin and ground. The first mirror bias circuit is used to mirror the reset signal and the image signal so as to output the reset signal and the image signal to the switch selection circuit 114.

[0071] The first mirror bias circuit includes several first transistors, such as Figure 3The plurality of first transistors shown include a first PMOS transistor P0, a second PMOS transistor P1, a third PMOS transistor P2, and a fourth PMOS transistor P3. The first terminal (e.g., the gate) of the first PMOS transistor P0 receives a first bias voltage pcasc. The second terminal (e.g., the drain) of the first PMOS transistor P0 is connected to the first terminal of the second PMOS transistor P1. The third terminal (e.g., the source) of the first PMOS transistor P0 is connected to the second terminal of the second PMOS transistor P1. The third terminal of the second PMOS transistor P1 is connected to the power supply Vc. The first terminal of the third PMOS transistor P2 receives the first bias voltage pcasc. The second terminal of the third PMOS transistor P2 is connected to the switch selection circuit 114. The third terminal of the third PMOS transistor P2 is connected to the second terminal of the fourth PMOS transistor P3. The first terminal of the fourth PMOS transistor P3 receives the first bias voltage pcasc. The third terminal of the fourth PMOS transistor P3 is connected to the power supply Vc.

[0072] In one embodiment, the switch selection circuit 114 includes a reset signal switch transistor P5 and an image signal switch transistor P6.

[0073] Reset signal switch transistor P5 is used to control the input of the reset signal. The first terminal of reset signal switch transistor P5 receives the reset switch signal sw_rst, the second terminal of reset signal switch transistor P5 is connected to the mirror sampling circuit 116, and the third terminal of reset signal switch transistor P5 is connected to the second terminal of transistor P2 of mirror input circuit 112. Image signal switch transistor P6 is used to control the input of the image signal. The first terminal of image signal switch transistor P6 receives the image switch signal sw_pix, the second terminal of image signal switch transistor P6 is connected to the comparator circuit 200, and the third terminal of image signal switch transistor P6 is connected to the third terminal of reset signal switch transistor P5.

[0074] In one embodiment, the mirror sampling circuit 116 includes a sampling circuit and a second mirror bias circuit.

[0075] The sampling circuit, connected to the switch selection circuit, is used to sample the reset signal; the second mirror bias circuit, connected to the switch selection circuit and the sampling circuit, is used to convert the reset signal sampled by the sampling circuit and the image signal subsequently output by the switch selection circuit into the difference between the current signals corresponding to the reset signal and the image signal through mirror bias.

[0076] In one embodiment, the sampling circuit includes a sampling switch N3 and a sampling capacitor C0.

[0077] The first terminal of sampling switch N3 receives the sampling voltage sw_samp, the second terminal of sampling switch N3 is connected to the second mirror bias circuit, and the third terminal of sampling switch N3 is connected to the first terminal of bias transistor Nirst0 and bias transistor (Nirst1) and grounded through sampling capacitor C0.

[0078] The second mirror bias circuit includes a plurality of second transistors, namely a first NMOS transistor N0, a second NMOS transistor Nirst0, a third NMOS transistor N1, and a fourth NMOS transistor Nirst1.

[0079] The first terminal of the first NMOS transistor N0 receives the second bias voltage ncasc, the second terminal of the first NMOS transistor N0 is connected to the second terminal of the sampling switch N3 of the sampling circuit, and the third terminal of the first NMOS transistor N0 is connected to the second terminal of the second NMOS transistor Nirst0; the first terminal of the third NMOS transistor N1 receives the second bias voltage ncasc, the second terminal of the third NMOS transistor N1 is connected to the comparator circuit 200, and the third terminal of the third NMOS transistor N1 is connected to the second terminal of the fourth NMOS transistor Nirst1; the first terminal of the second NMOS transistor Nirst0 is connected to the first terminal of the fourth NMOS transistor Nirst1, the third terminal of the second NMOS transistor Nirst0 is grounded; and the third terminal of the fourth NMOS transistor Nirst1 is grounded.

[0080] In one embodiment, the bias reference current generating circuit further includes: a plurality of first transistors and a reference current switching transistor P7.

[0081] A plurality of first transistors, including, for example, a fifth PMOS transistor P4 and a sixth PMOS transistor Prist, are used to receive a bias reference voltage signal and generate a bias reference current. The first terminal of the fifth PMOS transistor P4 receives a first bias voltage pcasc, and the second terminal of the fifth PMOS transistor P4 is connected to the third terminal of a reference current switching transistor P7. The third terminal of the fifth PMOS transistor P4 is connected to the second terminal of the sixth PMOS transistor Prist. The first terminal of the sixth PMOS transistor Prist receives a bias reference voltage signal pbias_ref, and the third terminal of the sixth PMOS transistor Prist is connected to a power supply Vc. The reference current switching transistor P7 is used to receive a feedback signal from a feedback circuit to control the output of the bias reference current. The first terminal of the reference current switching transistor P7 is connected to a feedback circuit 300, the second terminal of the reference current switching transistor P7 is connected to a comparator circuit, and the third terminal of the reference current switching transistor P7 is connected to the second terminal of the fifth PMOS transistor P4.

[0082] In one embodiment, the conversion circuit 100 further includes a compensation current generating circuit for generating a compensation current as the discharge current at the output terminal of the conversion circuit 100.

[0083] The compensation current generating circuit further includes: a plurality of second transistors for receiving a compensation voltage signal to generate a compensation current. The plurality of second transistors includes a fifth NMOS transistor N2 and a sixth NMOS transistor Niofs. The first terminal of the fifth NMOS transistor N2 receives a second bias voltage ncasc, the second terminal of the fifth NMOS transistor N2 is connected to a comparator circuit, and the third terminal of the fifth NMOS transistor N2 is connected to the second terminal of the sixth NMOS transistor Niofs. The first terminal of the sixth NMOS transistor Niofs receives a compensation voltage nbias_iofs, and the third terminal of the sixth NMOS transistor Niofs is grounded.

[0084] Among them, transistors P0, P1, P2, P3, P4, Pirst, P5, P6, and P7 are all PMOS field-effect transistors. The first terminal of the transistor can be the gate, the second terminal can be the drain or source, and the third terminal can be the source or drain. Transistors Nin, N0, N1, N2, N3, Nirst0, Nirst1, and Niofs are all NMOS field-effect transistors, etc. The first terminal of the transistor can be the gate, the second terminal can be the drain or source, and the third terminal can be the source or drain.

[0085] In one embodiment, the comparator circuit 200 includes a comparator CMP and a first capacitor C1.

[0086] The comparator CMP has its first input terminal connected to the output terminal imeas of the conversion circuit 100, its second input terminal receiving the comparison reference voltage signal vref, and its output terminal connected to the feedback circuit 300. The first capacitor C1 is connected between the first input terminal of the comparator CMP and ground, and is used to store the charge generated by the charging current and discharging current output by the conversion circuit to generate a charging voltage at the first input terminal of the comparator.

[0087] In one embodiment, the comparator circuit 200 further includes a second capacitor C2, which is connected between the output of the comparator CMP and the feedback circuit 300 to store the voltage signal output by the comparator CMP to control the feedback circuit 300 to flip.

[0088] The feedback circuit 300 includes a flip-flop 203 connected to the comparator circuit 200, which is used to sample the output signal of the comparator circuit 200 according to the clock signal and output a feedback signal.

[0089] In one embodiment, the flip-flop 203 may include an input terminal D, an output terminal Q, and a clock terminal clk. The input terminal D of the flip-flop is connected to a comparator circuit and is also connected to the output terminal of the inverter INV1 of the feedback circuit 300. The clock terminal clk of the flip-flop 203 receives a clock signal (clk signal). The output terminal Q of the flip-flop is connected to a conversion circuit and is also connected to the input terminal of the inverter INV2 of the feedback circuit 300.

[0090] The feedback circuit 300 further includes several inverters connected to the output terminals of the comparator circuit and / or the flip-flops, for pulse shaping of the output signal of the comparator circuit 200 and / or the feedback signal output by the flip-flop 203.

[0091] In this embodiment of the application, the plurality of inverters includes a first inverter INV0, a ​​second inverter INV1, a third inverter INV2, and a fourth inverter INV3.

[0092] The input of the first inverter INV0 is connected to the output Q of the flip-flop, and the output of the first inverter INV0 is connected to the first terminal of transistor P7 in the conversion circuit 100; the input of the second inverter INV1 is connected to the output of comparator CMP in the comparator circuit 200, and the output of the second inverter INV1 is connected to the input D of the flip-flop; the input of the third inverter INV2 is connected to the output Q of the flip-flop, and the output of the third inverter INV2 is connected to the input of the fourth inverter INV3, and the output of the fourth inverter INV3 is the output of the image sensor.

[0093] The readout circuit of the image sensor in this application is a dual sampling circuit at the analog domain input. By implementing dual sampling of the reset signal and the image signal at the analog domain input, the reset signal and the image signal can be converted into current signals. Corresponding sampling can be implemented at the analog domain input through relevant timing control. Moreover, only one quantization process is needed to achieve the same effect as the two quantizations of the traditional structure, which speeds up the signal quantization speed and has low power consumption.

[0094] like Figure 3 and Figure 4 As shown, the operation of the image sensor's readout circuit is as follows:

[0095] When the first input terminal vin of the conversion circuit 100 receives the reset signal Vrst, and the reset switch signal sw_rst and the sampling signal sw_samp are at high levels, the reset signal Vrst can be sampled on the capacitor C0 connected to the gates of transistors Nirst0 and Nirst1. After sampling, the reset switch signal sw_rst and the sampling signal sw_samp are turned off, and the image switch signal sw_pix becomes high, waiting for the image signal Vpix to be input from the first input terminal vin. The reset signal Vrst is converted into a discharge current Irst for node capacitor C1, and the image signal Vpix is ​​converted into a charging current Ipix for node capacitor C1. Therefore, by timing control, the voltage signals corresponding to the reset signal Vrst and the image signal Vpix are converted into corresponding current signals, that is, the function of correlation double sampling is realized at the analog domain input terminal.

[0096] In addition, capacitor C1 at node imeas also has a reference current Iref as the charging current and a compensation current Iofs as the discharging current. According to charge conservation, the charge flowing into and out of node imeas is equal, satisfying the formula: Iref*T1=(Irst-Ipix+Iofs)*T2, where T1 is the on-time of the reference current Iref and T2 is the total operating time. The voltage of node imeas fluctuates around the comparison reference voltage signal vref. When the voltage of node imeas is greater than the comparison reference voltage signal vref, comparator CMP charges capacitor C2 until it rises to the inverting voltage of the inverter, and the output of feedback circuit 300 jumps to a low level; the trigger samples the low-level signal and feeds it back to the reference current switch to turn off the reference current Iref. When the voltage of node imeas is less than the comparison reference voltage signal vref, the operating state is the opposite. Ultimately, the voltage of node imeas exhibits a sawtooth wave shape that periodically fluctuates around the comparison reference voltage signal vref. The reference current Iref must be greater than the sum of the difference between the reset signal current Irst and the image signal current Ipix, and the compensation current Iofs. The duty cycle of the inverter output signal is T1 / T2, i.e., (Irst - Ipix + Iofs) / Iref. Since the reference current Iref and the compensation current Iofs are given known values, the magnitude of (Irst - Ipix) can be determined by judging the duty cycle (T1 / T2) of the feedback signal output by the inverter, thereby determining the strength of the effective image signal (Vrst - Vpix).

[0097] Since the comparator CMP charges and discharges capacitor C2 to achieve the switching, the switching time is directly proportional to the size of capacitor C2. During the waiting time for the switching, capacitor C2 at the node is charged or discharged, and the voltage rises or falls in a sawtooth pattern as described above. However, the voltage of the node imeas cannot be too high, otherwise it will affect the normal operation of transistor Pirst or transistor P4, nor can it be too low, otherwise it will affect the normal operation of transistor N2 or transistor Niofs. In addition, capacitor C1 needs to be large enough to ensure that the fluctuation range of the node imeas is not too large. Usually, the capacitance of capacitor C1 should be approximately such that the voltage fluctuation of the node imeas during the waiting time of the comparator CMP can meet the normal operating conditions of transistors P7 and N2 at the node imeas. In another implementation, capacitor C2 can also be omitted, but if capacitor C2 is omitted, the inverter switching will be faster, thus making the T2 period shorter.

[0098] The current Iofs is used to ensure that when the currents Irst and Ipix are equal (i.e., in the absence of light), the node imeas still has a discharge path, allowing the circuit to discharge and function normally. Under normal circumstances, when the currents Ipix and Irst are not equal, the compensation current generation circuit 130 composed of transistors N2 and Niofs can be omitted. In this case, according to charge conservation, the charge flowing into and out of the node imeas satisfies the formula: Iref*T1=(Irst-Ipix)*T2. Since the reference current Iref is a given known value, the magnitude of (Irst-Ipix) can be determined by judging the duty cycle (T1 / T2) of the feedback signal output from the inverter, thus determining the strength of the effective image signal (Vrst-Vpix).

[0099] Furthermore, this readout circuit is also compatible with the normal mode, which requires double quantization for dual sampling. This can be achieved by simply turning off the reset switch signal sw_rst and the sampling signal sw_samp, while keeping the image switch signal sw_pix constantly open. Specifically, the voltage signals of the reset signal Vrst and the image signal Vpix are alternately input from the input terminal vin. The image signal switching transistor P6 and the comparator CMP sequentially quantize the reset signal and the image signal twice. The effective image signal (Vrst - Vpix) is obtained by subtracting the voltage of the image signal from the reset signal.

[0100] Based on the same concept as the foregoing embodiments, this application provides an electronic device that includes the image sensor described in the above embodiments. The electronic device can be, for example, a camera, a mobile phone, a personal digital assistant, a computer, a monitoring device, a machine vision device, etc.

[0101] In summary, the image sensor, its readout circuit, and electronic device provided in this application convert the received reset signal and image signal into corresponding current signals through a conversion circuit. The difference between the current signals corresponding to the reset signal and the image signal is used as the discharge current at the output terminal. The conversion circuit also generates a bias reference current based on a bias reference voltage signal, which serves as the charging current at the output terminal of the conversion circuit. The comparison circuit compares the charging current and the charging voltage generated by the discharge current output by the conversion circuit with the comparison reference voltage signal. The feedback circuit outputs a feedback signal based on the comparison result of the comparison circuit and feeds it back to the conversion circuit to control the output or non-output of the bias reference current. Thus, the strength of the effective image signal is determined based on charge conservation and the duty cycle of the feedback signal output by the feedback circuit. This allows the reset signal and image signal to be converted into current signals for sampling. Furthermore, only one quantization process is needed to achieve the same effect as two quantization processes in traditional structures, accelerating the signal quantization speed, improving the image readout speed of the image sensor, and reducing power consumption.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0104] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0105] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0106] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A readout circuit for an image sensor, characterized in that, include: The circuit includes a conversion circuit, a comparison circuit, and a feedback circuit; The conversion circuit has a first input terminal for receiving a reset signal and an image signal, and a second input terminal for receiving a bias reference voltage signal. The conversion circuit converts the received reset signal and image signal into corresponding current signals, and uses the difference between the current signals corresponding to the reset signal and the image signal as the discharge current at its output terminal. The conversion circuit also generates a bias reference current based on the bias reference voltage signal, and the bias reference current serves as the charging current at the output terminal of the conversion circuit. The first input terminal of the comparator circuit is connected to the output terminal of the conversion circuit, and the second input terminal of the comparator circuit receives a comparison reference voltage signal. The comparator circuit compares the charging voltage generated by the charging current and discharging current output by the conversion circuit with the comparison reference voltage signal. The feedback circuit is connected to the output of the comparison circuit and is used to output a feedback signal to the conversion circuit according to the comparison result of the comparison circuit, so as to control the output or non-output of the bias reference current, thereby determining the strength of the effective image signal based on charge conservation and the duty cycle of the feedback signal output by the feedback circuit.

2. The readout circuit of the image sensor as described in claim 1, characterized in that, The conversion circuit further includes: A current difference generation circuit receives the reset signal and the image signal through the first input terminal of the conversion circuit, converts the received reset signal and image signal into corresponding current signals, and generates the difference between the current signals corresponding to the reset signal and the image signal; and A bias reference current generating circuit is connected to the current difference generating circuit. The bias reference current generating circuit receives the bias reference voltage signal through the second input terminal of the conversion circuit and generates the bias reference current according to the bias reference voltage signal.

3. The readout circuit of the image sensor as described in claim 2, characterized in that, The current difference generating circuit further includes: The mirror input circuit receives the reset signal and the image signal through the first input terminal of the conversion circuit, converts the received reset signal and the image signal into corresponding current signals, and then converts them into corresponding voltage signals through mirror bias. The switch selection circuit receives the reset signal and image signal output by the mirror input circuit in sequence through the switch control signal; A mirror sampling circuit is connected to the mirror input circuit and the switch selection circuit. The mirror sampling circuit samples and stores the reset signal output by the switch selection circuit, and converts the difference between the reset signal and the image signal subsequently output by the switch selection circuit into the difference of the corresponding current signal through mirror bias, so as to serve as the discharge current at the output of the conversion circuit.

4. The readout circuit of the image sensor as described in claim 3, characterized in that, The mirror input circuit includes a signal input transistor, an input load, and a first mirror bias circuit, wherein: The signal input transistor has a first terminal for receiving the reset signal and the image signal in sequence, and the second terminal of the signal input transistor is connected to the first mirror bias circuit. The input load is connected between the third terminal of the signal input transistor and ground; and The first mirror bias circuit is used to mirror the reset signal and the image signal, so as to output the mirror-biased reset signal and the image signal to the switch selection circuit.

5. The readout circuit of the image sensor as described in claim 4, characterized in that, The first mirror bias circuit includes a plurality of first transistors, including a first PMOS transistor (P0), a second PMOS transistor (P1), a third PMOS transistor (P2), and a fourth PMOS transistor (P3). The first terminal of the first PMOS transistor (P0) receives a first bias voltage, the second terminal of the first PMOS transistor (P0) is connected to the first terminal of the second PMOS transistor (P1), and the third terminal of the first PMOS transistor (P0) is connected to the second terminal of the second PMOS transistor (P1). The third terminal of the second PMOS transistor (P1) is connected to a power supply. The first terminal of the third PMOS transistor (P2) receives the first bias voltage, the second terminal of the third PMOS transistor (P2) is connected to the switch selection circuit, and the third terminal of the third PMOS transistor (P2) is connected to the second terminal of the fourth PMOS transistor (P3). The first terminal of the fourth PMOS transistor (P3) receives the first bias voltage, and the third terminal of the fourth PMOS transistor (P3) is connected to a power supply.

6. The readout circuit of the image sensor as described in claim 3, characterized in that, The switch selection circuit includes: A reset signal switching transistor is used to control the input of a reset signal. The first terminal of the reset signal switching transistor receives a reset switch signal, the second terminal of the reset signal switching transistor is connected to the mirror sampling circuit, and the third terminal of the reset signal switching transistor is connected to the mirror input circuit. An image signal switching transistor is used to control the input of an image signal. The first terminal of the image signal switching transistor receives an image switching signal, the second terminal of the image signal switching transistor is connected to a comparator circuit, and the third terminal of the image signal switching transistor is connected to the third terminal of the reset signal switching transistor.

7. The readout circuit of the image sensor as described in claim 3, characterized in that, The mirror sampling circuit includes: A sampling circuit, connected to the switch selection circuit, is used to sample the reset signal; and The second mirror bias circuit, connected to the switch selection circuit and the sampling circuit, is used to convert the reset signal sampled by the sampling circuit and the image signal subsequently output by the switch selection circuit into the difference between the current signals corresponding to the reset signal and the image signal through mirror bias.

8. The readout circuit of the image sensor as described in claim 7, characterized in that, The second mirror bias circuit includes a plurality of second transistors, including a first NMOS transistor (N0), a second NMOS transistor (Nirst0), a third NMOS transistor (N1), and a fourth NMOS transistor (Nirst1). The first terminal of the first NMOS transistor (N0) receives a second bias voltage, the second terminal of the first NMOS transistor (N0) is connected to a sampling circuit, and the third terminal of the first NMOS transistor (N0) is connected to the second terminal of the second NMOS transistor (Nirst0). The first terminal of the third NMOS transistor (N1) receives the second bias voltage, the second terminal of the third NMOS transistor (N1) is connected to a comparator circuit, and the third terminal of the third NMOS transistor (N1) is connected to the second terminal of the fourth NMOS transistor (Nirst1). The first terminal of the second NMOS transistor (Nirst0) is connected to the first terminal of the fourth NMOS transistor (Nirst1), the third terminal of the second NMOS transistor (Nirst0) is grounded, and the third terminal of the fourth NMOS transistor (Nirst1) is grounded.

9. The readout circuit of the image sensor as described in claim 7, characterized in that, The sampling circuit includes a sampling switch and a sampling capacitor. The first terminal of the sampling switch receives the sampling voltage, the second terminal of the sampling switch is connected to a second mirror bias circuit, and the third terminal of the sampling switch is connected to the first terminals of the second NMOS transistor (Nirst0) and the fourth NMOS transistor (Nirst1) and grounded through the sampling capacitor.

10. The readout circuit of the image sensor as described in claim 2, characterized in that, The bias reference current generating circuit further includes: A plurality of first transistors are configured to receive the bias reference voltage signal and generate the bias reference current; and A reference current switching transistor is used to receive feedback signals from the feedback circuit to control the output of the bias reference current.

11. The readout circuit of the image sensor as described in claim 10, characterized in that, The plurality of first transistors include a fifth PMOS transistor (P4) and a sixth PMOS transistor (Prist). The first terminal of the fifth PMOS transistor (P4) receives a first bias voltage, the second terminal of the fifth PMOS transistor (P4) is connected to the third terminal of a reference current switching transistor, and the third terminal of the fifth PMOS transistor (P4) is connected to the second terminal of the sixth PMOS transistor (Prist). The first terminal of the sixth PMOS transistor (Prist) receives a bias reference voltage signal, the third terminal of the sixth PMOS transistor (Prist) is connected to a power supply, the first terminal of the reference current switching transistor is connected to a feedback circuit, the second terminal of the reference current switching transistor is connected to a comparator circuit, and the third terminal of the reference current switching transistor is connected to the second terminal of the fifth PMOS transistor (P4).

12. The readout circuit of the image sensor as described in claim 2, characterized in that, The conversion circuit further includes: a compensation current generating circuit for generating a compensation current as the discharge current at the output terminal of the conversion circuit.

13. The readout circuit of the image sensor as described in claim 12, characterized in that, The compensation current generating circuit further includes: a plurality of second transistors for receiving a compensation voltage signal to generate the compensation current, the plurality of second transistors including a fifth NMOS transistor (N2) and a sixth NMOS transistor (Niofs), the first terminal of the fifth NMOS transistor (N2) receiving a second bias voltage, the second terminal of the fifth NMOS transistor (N2) being connected to a comparator circuit, the third terminal of the fifth NMOS transistor (N2) being connected to the second terminal of the sixth NMOS transistor (Niofs); the first terminal of the sixth NMOS transistor (Niofs) receiving the compensation voltage, and the third terminal of the sixth NMOS transistor (Niofs) being grounded.

14. The readout circuit of the image sensor as described in claim 1, characterized in that, The comparison circuit includes: A comparator, whose first input is connected to the output of the conversion circuit, whose second input receives the comparison reference voltage signal, and whose output is connected to the feedback circuit; and A first capacitor is connected between the first input terminal of the comparator and ground, and is used to store the charge generated by the charging current and discharging current output by the conversion circuit to generate a charging voltage at the first input terminal of the comparator.

15. The readout circuit of the image sensor as described in claim 14, characterized in that, The comparator circuit further includes a second capacitor connected between the output terminal of the comparator and the feedback circuit, for storing the voltage signal output by the comparator to control the feedback circuit to flip.

16. The readout circuit of the image sensor as described in claim 1, characterized in that, The feedback circuit includes a flip-flop connected to the comparator circuit, used to sample the output signal of the comparator circuit according to the clock signal and output the feedback signal. The input terminal of the flip-flop is connected to the comparator circuit, the clock terminal of the flip-flop receives the clock signal, and the output terminal of the flip-flop is connected to the conversion circuit.

17. The readout circuit of the image sensor as described in claim 16, characterized in that, The feedback circuit further includes several inverters connected to the output terminal of the comparator circuit and / or the output terminal of the flip-flop, for pulse shaping of the output signal of the comparator circuit and / or the feedback signal output by the flip-flop.

18. The readout circuit of the image sensor as described in claim 17, characterized in that, The plurality of inverters includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The input terminal of the first inverter is connected to the output terminal of a flip-flop, and the output terminal of the first inverter is connected to a conversion circuit. The input terminal of the second inverter is connected to a comparator circuit, and the output terminal of the second inverter is connected to the input terminal of the flip-flop. The input terminal of the third inverter is connected to the output terminal of the flip-flop, and the output terminal of the third inverter is connected to the input terminal of the fourth inverter.

19. An image sensor, characterized in that, include: A pixel array, comprising multiple pixels arranged in rows and columns; A control circuit, connected to the pixel array, is used to control the pixel array to output a reset signal and an image signal; as well as The readout circuit as described in any one of claims 1-18 is connected to the pixel array and is used to read the reset signal and image signal output by the pixel array to determine the strength of the valid image signal.

20. An electronic device, characterized in that, Including the image sensor as described in claim 19.

Images