A preparation method for improving junction isolation characteristics of N-type piezoresistive sensor
By using P-type silicon wafer, photolithography, doping and insulating layers to form an isolation ring structure in the N-type piezoresistive sensor, the electron aggregation problem caused by positive charge of the oxide layer is solved, and the junction isolation characteristics and reliability of the sensor are improved.
Patent Information
- Application Number
- CN202211515863.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-30
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2042-11-30
AI Technical Summary
During the preparation process of the N-type piezoresistive sensor, due to the presence of positive charge in the oxide layer, electrons gather at the interface between silicon and silicon oxide, forming an electron-rich layer, resulting in a decrease in junction isolation characteristics and leakage.
A P-type silicon wafer is used as the chip substrate, and an N+ implantation region, N-varistor and P-type isolation ring structure are formed through photolithography and doping, combined with annealing and insulating layers, and finally, metal leads are formed in the contact hole to block the electron migration channel.
It effectively improves the junction isolation characteristics of the N-type piezoresistive sensor, reduces leakage current, and improves product performance and reliability.
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Figure CN116295542B_ABST
Abstract
Description
Technical field:
[0002] The present invention relates to the field of micro-electromechanical technology, and in particular to a preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor. Background technology:
[0004] Piezoresistive sensors are devices created by implanting diffused resistors onto a semiconductor substrate based on the piezoresistive effect of semiconductor materials. These diffused resistors are connected within the substrate to form a bridge structure, acting directly as measurement sensing elements. When the substrate is deformed by external forces, the resistance values change, and the bridge generates a correspondingly unbalanced output. These sensors are widely used in pressure sensors, accelerometers, and MEMS scanning mirror angle feedback sensors.
[0005] Piezoresistive sensors typically use an oxide layer as an insulating layer during fabrication. However, because the oxide layer is not an ideal insulator during fabrication, a small amount of positive charge is present within the oxide layer. When the substrate material is P-type, this charge affects the spatial distribution of charge on the silicon substrate. At the interface between silicon and silicon oxide, electrons are attracted by the positive charge and accumulate there. N-type piezoresistive sensors use a P-type silicon substrate. This phenomenon causes an electron-rich layer to form on the surface of the P-type substrate, resulting in poor junction isolation and varying degrees of leakage. To address this issue, a method to improve the junction isolation characteristics of N-type piezoresistive sensors is urgently needed. Summary of the invention:
[0007] The present invention aims to overcome the deficiencies in the prior art and provides a method for preparing an N-type piezoresistive sensor with improved junction isolation characteristics.
[0008] This application provides the following technical solutions:
[0009] A preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor, characterized in that it comprises the following steps S1: selecting a P-type silicon wafer as a chip substrate, performing photolithography on the P-type silicon wafer to form a pattern, then implanting phosphorus, and then stripping the resist to form a heavily doped region, which becomes an N+ implantation region;
[0010] S2. Patterning is performed on the P-type silicon wafer between the N+ implantation regions by photolithography, followed by secondary phosphorus implantation and stripping to form an N-type varistor between the two N+ implantation regions.
[0011] S3, patterning is performed on the P-type silicon wafer outside the N+ implantation area by photolithography, followed by boron implantation and debonding, to form a P-type isolation ring structure 6 outside all N+ implantation areas;
[0012] S4 forms an insulating layer on the substrate wafer by annealing, oxidation or CVD growth;
[0013] S5 forms a contact hole communicating with the N+ implantation region on the insulating layer through photolithography, etching, and resist stripping;
[0014] S6 forms a metal lead connected to the N+ injection area in the contact hole through sputtering, photolithography, etching, and desizing. One end of the metal lead extends out of the insulating layer for a distance and extends to the outside of the contact hole for a distance.
[0015] On the basis of the above technical solutions, the following further technical solutions can be provided:
[0016] In step S1, the phosphorus is implanted with an injection energy of 50 kev, an injection angle of 7°, and an injection dose of 5e15-5e16 atom / cm 2 .
[0017] In the second phosphorus implantation in step S2, the implantation energy is 50keV, the implantation angle is 7°, and the implantation dose is 5e13-5e14atom / cm 2 .
[0018] In step S3, the boron is implanted at an energy of 50 kev, an angle of 7°, and an implantation dose of 1e14-5e16 atom / cm 2 .
[0019] In step S4, the thickness of the insulating layer is 200 nm to 300 nm.
[0020] The sputtering in S5 is magnetron sputtering, and the sputtered metal is Al, Ti, W, Au, or Pt.
[0021] Advantages of the invention:
[0022] The present invention has simple steps and is easy to implement. It effectively blocks the electron migration channel between the N-type piezoresistive sensor and other functional ports through the isolation ring, reduces leakage current, and improves product performance and reliability. Description of the drawings:
[0024] Figure 1 This is a schematic diagram of the structure of the present invention after completion;
[0025] Figure 2 It is a schematic diagram of the distribution of the N+ implantation region 2, the N-varistor 3 and the P-type isolation ring structure 6 after the present invention is completed. Specific implementation method:
[0027] Example 1;
[0028] like Figure 1 and 2As shown, a preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor includes the following steps: S1. A P-type silicon wafer 1 is selected as a chip substrate, and patterning is performed on the P-type silicon wafer 1 by photolithography. Then, phosphorus is implanted, and then the resist is removed to form a heavily doped region, thereby obtaining a set of N+ implanted regions 2. The phosphorus implantation is performed at an injection energy of 50 keV, an injection angle of 7°, and an implantation dose of 5e15 atoms / cm 2 .
[0029] S2. Patterning is performed on the P-type silicon wafer 1 between the N+ implant regions, followed by a second phosphorus implantation and stripping. N-varistor 3 is formed between two adjacent N+ implant regions 2, thereby connecting all N+ implant regions 2 into a closed loop structure through the N-varistor 3. The second phosphorus implantation has an implantation energy of 50keV, an implantation angle of 7°, and an implantation dose of 5e13atom / cm 2 .
[0030] S3, the P-type silicon wafer outside the N+ implantation area is patterned by photolithography, and then boron implantation and debonding are performed to form a P-type isolation ring structure 6 outside all N+ implantation areas. When performing boron implantation, the implantation energy is 50keV, the angle is 7°, and the implantation dose is 1e14atom / cm 2 .
[0031] S4 forms an insulating layer 5 on the substrate wafer by annealing, oxidation or CVD growth. The annealing temperature is 1000° C., the time is 30 minutes, and the thickness of the insulating layer is 200 nm.
[0032] S5: forming a contact hole 4 communicating with the N+ implantation region on the insulating layer by photolithography, etching, and resist stripping;
[0033] S6 forms a metal lead 7 in contact hole 4 that is connected to the N+ implantation region by sputtering, photolithography, etching, and resist removal. One end of the metal lead 7 extends a distance out of the insulating layer and extends a distance outside the contact hole. The metal lead is Pt.
[0034] Example 2:
[0035] like Figure 1 and 2 As shown, a preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor includes the following steps S1: selecting a P-type silicon wafer 1 as a chip substrate, performing photolithography on the P-type silicon wafer 1 to form a pattern, then implanting phosphorus, and then stripping to form a heavily doped region, thereby obtaining a set of N+ implanted regions 2. During the phosphorus implantation, the implantation energy is 50keV, the implantation angle is 7°, and the implantation dose is 5e16atom / cm 2 .
[0036] S2. Patterning is performed on the P-type silicon wafer 1 between the N+ implant regions, followed by a second phosphorus implantation and stripping. N-varistor 3 is formed between two adjacent N+ implant regions 2, thereby connecting all N+ implant regions 2 into a closed loop structure through the N-varistor 3. The second phosphorus implantation has an injection energy of 50keV, an injection angle of 7°, and an implant dose of 5e14atom / cm 2 .
[0037] S3, the P-type silicon wafer outside the N+ implantation area is patterned by photolithography, and then boron implantation and debonding are performed to form a P-type isolation ring structure 6 outside all N+ implantation areas. When performing boron implantation, the implantation energy is 50keV, the angle is 7°, and the implantation dose is 5e16atom / cm 2 .
[0038] S4 forms an insulating layer 5 on the substrate wafer by annealing, oxidation or CVD growth. The annealing temperature is 1000° C., the time is 30 minutes, and the thickness of the insulating layer is 300 nm.
[0039] S5: forming a contact hole 4 communicating with the N+ implantation region on the insulating layer by photolithography, etching, and resist stripping;
[0040] S6 forms a metal lead 7 in contact hole 4 that is connected to the N+ implantation region by sputtering, photolithography, etching, and resist removal. One end of the metal lead 7 extends a distance beyond the insulating layer and outward of the contact hole. The metal lead is made of Al.
[0041] Example 3:
[0042] like Figure 1 and 2 As shown, a preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor includes the following steps S1: selecting a P-type silicon wafer 1 as a chip substrate, performing photolithography on the P-type silicon wafer 1 to form a pattern, then implanting phosphorus, and then stripping to form a heavily doped region, thereby obtaining a set of N+ implanted regions 2. During the phosphorus implantation, the implantation energy is 50keV, the implantation angle is 7°, and the implantation dose is 5e16atom / cm 2 .
[0043] S2. Patterning is performed on the P-type silicon wafer 1 between the N+ implant regions, followed by a second phosphorus implantation and stripping. N-varistor 3 is formed between two adjacent N+ implant regions 2, thereby connecting all N+ implant regions 2 into a closed loop structure through the N-varistor 3. The second phosphorus implantation has an implantation energy of 50keV, an implantation angle of 7°, and an implantation dose of 5e13atom / cm 2 .
[0044] S3, the P-type silicon wafer outside the N+ implantation area is patterned by photolithography, and then boron implantation and debonding are performed to form a P-type isolation ring structure 6 outside all N+ implantation areas. When performing boron implantation, the implantation energy is 50keV, the angle is 7°, and the implantation dose is 5e16atom / cm 2 .
[0045] S4 forms an insulating layer 5 on the substrate wafer by annealing, oxidation or CVD growth. The annealing temperature is 1000° C., the time is 30 minutes, and the thickness of the insulating layer is 300 nm.
[0046] S5: forming a contact hole 4 communicating with the N+ implantation region on the insulating layer by photolithography, etching, and resist stripping;
[0047] S6 forms a metal lead 7 in contact hole 4 that is connected to the N+ implantation region by sputtering, photolithography, etching, and resist removal. One end of the metal lead 7 extends a distance beyond the insulating layer and outward of the contact hole. The metal lead is made of Ti.
[0048] Example 4:
[0049] like Figure 1 and 2 As shown, a preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor includes the following steps: S1. A P-type silicon wafer 1 is selected as a chip substrate, and patterning is performed on the P-type silicon wafer 1 by photolithography. Then, phosphorus is implanted, and then the resist is removed to form a heavily doped region, thereby obtaining a set of N+ implanted regions 2. The phosphorus implantation is performed at an injection energy of 50 keV, an injection angle of 7°, and an implantation dose of 5e15 atoms / cm 2 .
[0050] S2. Patterning is performed on the P-type silicon wafer 1 between the N+ implant regions, followed by a second phosphorus implantation and stripping. N-varistor 3 is formed between two adjacent N+ implant regions 2, thereby connecting all N+ implant regions 2 into a closed loop structure through the N-varistor 3. The second phosphorus implantation has an injection energy of 50keV, an injection angle of 7°, and an implant dose of 5e14atom / cm 2 .
Claims
1. A method for improving the junction isolation characteristics of an N-type piezoresistive sensor, characterized by: The method comprises the following steps S1: selecting a P-type silicon wafer as a chip substrate, performing photolithography on the P-type silicon wafer to form a pattern, then implanting phosphorus, and then stripping the resist to form a heavily doped region, which becomes an N+ implantation region; S2. Patterning is performed on the P-type silicon wafer between the N+ implantation regions by photolithography, followed by secondary phosphorus implantation and stripping to form an N-type varistor between the two N+ implantation regions. S3, patterning is performed on the P-type silicon wafer outside the N+ implantation area by photolithography, followed by boron implantation and debonding, so that a P-type isolation ring structure (6) is formed outside all N+ implantation areas; S4 forms an insulating layer on the substrate wafer by annealing, oxidation or CVD growth; S5 forms a contact hole communicating with the N+ implantation region on the insulating layer through photolithography, etching, and resist stripping; S6 forms a metal lead connected to the N+ implantation region in the contact hole through sputtering, photolithography, etching, and debonding.
2. A method for improving the junction isolation characteristics of an N-type piezoresistive sensor according to claim 1, characterized in that: In step S1, the phosphorus is implanted with an injection energy of 50 kev, an injection angle of 7°, and an injection dose of 5e15-5e16 atom / cm 2 .
3. The method for improving the junction isolation characteristics of an N-type piezoresistive sensor according to claim 1, characterized in that: In the second phosphorus implantation in step S2, the implantation energy is 50keV, the implantation angle is 7°, and the implantation dose is 5e13-5e14atom / cm 2 .
4. A method for improving the junction isolation characteristics of an N-type piezoresistive sensor according to claim 1, characterized in that: In step S3, the boron is implanted at an energy of 50 kev, an angle of 7°, and an implantation dose of 1e14-5e16 atom / cm 2 .
5. The method for improving the junction isolation characteristics of an N-type piezoresistive sensor according to claim 1, characterized in that: In step S4, the thickness of the insulating layer is 200 nm to 300 nm.
6. A method for improving the junction isolation characteristics of an N-type piezoresistive sensor according to claim 1, characterized in that: The sputtering in S5 is magnetron sputtering, and the sputtered metal is Al, Ti, W, Au, or Pt.
Citation Information
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