A signal acquisition and imaging system applicable to an array superconducting single-photon detector

Abstract

The present invention discloses a signal acquisition and imaging system applicable to an array superconducting single-photon detector, comprising: an optical circuit, a readout circuit, a time-to-digital converter, and an image generation system; an optical circuit is built to adjust the direction of a laser pulse and converge the optical pulse to the nanowire detection region; through the readout circuit, the response signals of the array superconducting single-photon detector are acquired, and the row and column circuits connected to the pixels generate two pulses with opposite polarities on the row and column respectively after amplification; the time-to-digital converter obtains the arrival time of each pulse signal and transmits the information with time stamps to the image generation system; the image generation system analyzes based on the received signals, calculates the actual optical response count values of each pixel, and outputs a visualized image through a gray-scale normalization algorithm. The present invention can read out the time interval and spatial position of the response and perform real-time imaging display on the object to be measured.

Description

Technical Field

[0001] The present invention relates to the technical field of superconducting single - photon detection, and in particular to a signal acquisition and imaging system applicable to an array of superconducting single - photon detectors. Background Art

[0002] The superconducting nanowire single - photon detector (SNSPD) is a new type of single - photon detector. Compared with traditional semiconductor detectors, it has advantages such as high detection efficiency, low dark - count rate, low time jitter, high count rate, and broad - spectrum response. This enables it to be applied in many fields, such as quantum communication, quantum light - source characterization, laser ranging, imaging radar, etc. The photosensitive part of the SNSPD is a nanowire meandering structure made of superconducting thin - film material. When the SNSPD device operates at a specific temperature (hundreds of mK to several K), the nanowire is in the superconducting state. At the same time, a bias current I lower than its critical superconducting current is applied across the two ends of the nanowire. B When the SNSPD detects a photon, the energy of the photon will disrupt the "electron - Cooper pair" inside the superconductor, generating a hot spot in the central region of the nanowire. The nanowire begins to change from the superconducting state to the resistive state, and a very obvious voltage signal is generated in the circuit. By amplifying this pulse signal, we can identify a single photon.

[0003] With the continuous improvement of the performance of single - pixel detectors, the design and research of array - type detectors have become a hot topic. Compared with single - pixel SNSPDs, array - type SNSPDs have significantly improved performance in terms of detection speed, detection efficiency, and noise suppression, greatly expanding the application range of SNSPDs. However, as the scale of the SNSPD array gradually increases, the difficulty of data acquisition also rises. During various application tests, it is necessary to collect and transmit the signals generated by the detector after receiving photons to a computer for subsequent data processing. For an array of superconducting nanowire single - photon detectors, the data - acquisition process has the following difficulties: extremely high measurement accuracy requirements, and the delays and instabilities existing in each part of the system will have a greater impact on the data - processing results; a large amount of data, with data volumes of dozens to hundreds of MHz per second bringing difficulties to real - time processing and gray - scale imaging. In a general data - acquisition system, there is data transfer between the single - chip microcomputer and the A / D conversion during each data - acquisition process. Due to the limitation of the instruction - execution time of the single - chip microcomputer, it takes dozens to hundreds of microseconds to acquire one data, and such a system obviously cannot meet the requirements of high - speed data acquisition.

[0004] The time - to - digital converter (TDC for short) is often used to measure time intervals and is widely used in the field of time - of - flight measurement. The TDC based on a delay chain does not require an analog - to - digital conversion process and can achieve direct conversion from time to digital, with advantages such as a large measurement range, high time resolution, and good scalability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a signal acquisition and imaging system applicable to an array superconducting single photon detector, which can read out the response time interval and spatial position and perform real-time imaging display on the object to be measured.

[0006] To solve the above technical problem, the present invention provides a signal acquisition and imaging system applicable to an array superconducting single photon detector, including: an optical circuit, a readout circuit, a time-to-digital converter, and an image generation system; an optical circuit is built to adjust the direction of the laser pulse and focus the light pulse on the nanowire detection area; through the readout circuit, the response signal of the array superconducting single photon detector is obtained, and the row and column circuits connected to the pixels generate two pulses with opposite polarities on the row and column respectively after amplification; the arrival time of each pulse signal is obtained through the time-to-digital converter, and the information with time stamps is transmitted to the image generation system through Gigabit Ethernet; the image generation system analyzes based on the received signal, calculates the actual light response count value of each pixel, and generates a visual image through a gray normalization algorithm.

[0007] Preferably, the optical circuit includes a laser, a collimator, an attenuator, a convex lens, a reflector, a beam splitter cube, a CCD, and a spatial light source; the laser and the spatial light source provide reference light; the collimator is used to collimate the light beam and reduce the laser divergence angle; the attenuator attenuates the light to prevent the nanowire from quenching due to excessive light intensity; the convex lens is responsible for focusing the spatial light; the reflector is responsible for reflecting the light onto the SNSPD photosensitive surface; the beam splitter cube introduces the laser and the visible light source into the CCD camera, and the CCD camera monitors the light coupling situation.

[0008] Preferably, the readout circuit includes 64 T-type biasers and 64 RF amplifiers; the output end of the detector is connected to the RF and DC ports of the T-type biaser, and the DC bias ports of 32 T-type biasers are connected to the bias circuit, and the other 32 DC bias ports are grounded; the RF port of the T-type biaser is connected to the input end of the RF amplifier; the output end of the RF amplifier is connected to the trigger signal input of the time-to-digital converter, and the digital converter is used to accurately measure the arrival time of the pulse signal.

[0009] Preferably, the bias circuit is obtained by connecting a bias resistor and an adjustable voltage source in series, and by controlling the adjustable voltage source, the detector is placed in a state below its critical current.

[0010] Preferably, the time-to-digital converter includes a system clock module, a coarse counting module, a fine measurement module, a data storage module, and a data transmission module; the system clock module multiplies the input clock signal through an internal clock multiplier chip of the FPGA and outputs a 250 MHz reference clock; the coarse counting module measures the interval time that is an integer multiple of the reference clock cycles between the Start signal and the Stop signal; the fine measurement module measures the time information less than one clock cycle; the data storage module is stored using a synchronous FIFO; the data transmission module performs high-speed data transmission through the PCIe protocol.

[0011] Preferably, the time-to-digital converter is implemented by combining "coarse counting" and "fine measurement"; the coarse counting module uses a binary counter; the fine measurement module cascades a series of dedicated carry chain Carry 4 delay units to form a delay chain, and then introduces the Start signal into the delay chain for time interpolation, and finely quantifies the time interval between adjacent clock pulses using the propagation delay of the delay unit.

[0012] Preferably, the time-to-digital converter calculates the time difference of the signal according to the following formula:

[0013] ΔT = T1 + T - T2 = (W1 - W2)LSB + W3t

[0014] Where N1 is the interpolation result of the Start signal, N2 is the interpolation result of the Stop signal, N3 is the count value of the counter, t is the reference clock cycle, and LSB represents the delay time of one delay unit in the tapped delay line.

[0015] Preferably, the image generation system is executed concurrently by three threads. Thread 1 is responsible for pulling data from the TDC to the computer and storing it in the current data cache queue; Thread 2 is responsible for periodically taking out the data at the head of the queue for processing and calculation; Thread 3 converts the calculated response count into a grayscale value at fixed intervals according to the imaging frame rate. Let the maximum pixel count value within the current time interval be N max , and the minimum pixel count value be N min , then for a pixel with a count value of M, according to the grayscale normalization algorithm, the corresponding grayscale value G is:

[0016] G = 255 * (1 - (M - N min ) / (N max - N min ))

[0017] Take the photon count of each pixel as its pixel intensity to form a new two-dimensional matrix, and convert this matrix into a grayscale value image.

[0018] The beneficial effects of the present invention are as follows: (1) The present invention effectively combines the direct counting method with a large measurement range and the tapped delay line method with high precision. This implementation scheme can make the advantages of these two methods complementary, achieving a high measurement accuracy of the order of 14 ps while having a relatively wide time measurement range; (2) During the real-time acquisition process, the amount of data is large. The present invention has been optimized at the software level, manually managing memory to avoid the lag caused by frequent garbage collection in the system, and efficiently processing the large amount of data generated by multiple channels through concurrent programming to achieve real-time array imaging with a maximum frame rate exceeding 30 frames, solving the disadvantages of slow scanning imaging and low efficiency of conventional single-photon systems; (3) The present invention uses a high-speed time-to-digital converter implemented based on FPGA. By optimizing the layout and wiring, 64 channels can be integrated. Each channel is independent of each other, and the maximum counting rate can reach hundreds of megahertz. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is a schematic structural diagram of the system of the present invention.

[0020] Figure 2 FIG. is a schematic diagram of the time interval measurement principle of the present invention.

[0021] Figure 3 FIG. is a schematic diagram of the "fine time" measurement of the present invention.

[0022] Figure 4 FIG. is a schematic diagram of the structure of the time-to-digital converter of the present invention.

[0023] Figure 5 FIG. is the final imaging result diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] As Figure 1 shown, a signal acquisition and imaging system applicable to an array of superconducting single-photon detectors includes: an optical circuit, a readout circuit, a time-to-digital converter, and an image generation system; an optical circuit is built to adjust the direction of the laser pulse and focus the light pulse on the nanowire detection area; through the readout circuit, the response signals of the array of superconducting single-photon detectors are obtained. The row and column circuits connected to the pixels are amplified to generate two pulses with opposite polarities on the row and column respectively; the arrival time of each pulse signal is obtained through the time-to-digital converter, and the information with time stamps is transmitted to the image generation system through Gigabit Ethernet; the image generation system analyzes the received signals, calculates the actual light response count values of each pixel, and generates a visual image through a gray-scale normalization algorithm.

[0025] By adjusting the optical circuit, the power of the current laser is controlled to a specified power, and the position of the mirror is moved along the set path, thereby changing the position of the light spot coupled to the detector to make it focus within the photosensitive area of the detector.

[0026] At low temperatures, the nanowires are biased slightly below the superconducting critical current of the nanowires. When the SNSPD detects photons, only one pixel in the array is triggered by the photons. The nanowires absorb the photons, the superconducting state in the absorption region is destroyed, the thermal island effect appears, and resistance is generated. The row and column circuits connected to this pixel are amplified to generate two pulses with opposite polarities on the row and column respectively, and then recognizable positive and negative pulse signals are output through the amplifier.

[0027] The arrival time of each pulse signal is obtained through a time-to-digital converter, and the information of each channel with a timestamp is transmitted to the image generation system through Gigabit Ethernet.

[0028] The image generation system analyzes the received signals to calculate the actual light response count values of each pixel, and outputs a visual image through a gray normalization algorithm.

[0029] Among them, the optical circuit includes a laser, a collimator, an attenuator, a convex lens, a reflector, a beam splitter cube, a CCD, and a spatial light source; the visible light source provides reference light that is coupled with the laser emitted by the laser through the attenuator and the beam splitter cube. One path is directed to the CCD camera for monitoring, and the other path is focused by the convex lens and then reflected by the reflector to the photosensitive area of the SNSPD. After the output signal of the detector is transmitted through the coaxial cable, it is read out and amplified by the row-column multiplexed readout circuit, then transmitted to the time-to-digital converter, and the time information is recorded, and then transmitted to the image generation system through the PCIe interface. Each optical component is fixed on the optical bracket and installed on the optical rail to ensure adjustability and stability.

[0030] The detector selects an array superconducting nanowire single photon detector operating in the 1064nm near-infrared band. The atmospheric transmittance of light with a near-infrared wavelength is higher than that of visible light, the atmospheric transmission attenuation is smaller, and it is not easily absorbed by the human eye, having high eye safety.

[0031] The readout circuit includes 64 T-type biasers and 64 RF amplifiers. A positive and negative alternating bias current is added in the row direction, and the current is distributed to each pixel in each row, and then grounded through the column direction output line. The RF amplifier is used to read photon detection events. When there is no photon absorption, no corresponding pulses are detected on the row and column readout lines of the entire array. When a certain pixel absorbs photons, its superconducting state is destroyed, and at this time, two pulses with opposite polarities are generated on its row and column.

[0032] The time-to-digital converter is implemented based on the Xilinx Kintex-7 series FPGA and includes the following modules:

[0033] The system clock module multiplies the input clock signal by the internal clock multiplier chip of the FPGA and outputs a 250MHz reference clock.

[0034] The coarse counting module is implemented using a binary counter. The counter latches a count value each time the Start signal and each Stop signal arrive. The count latch values of the Start signal and the Stop signal corresponding to the channel are the signal time intervals.

[0035] The fine counting module has a core that uses a tapped delay line and cascades internal Carry 4 as a delay unit to form a delay chain. Its measurement accuracy can reach about 14 ps. Then, the signal to be measured is introduced into the delay chain for time interpolation. The specific implementation method is to lead out taps after each delay unit and connect them to the input of a D flip-flop. The state of the delay chain is sampled by the D flip-flop and the result is latched.

[0036] The data storage module is implemented using a synchronous FIFO, and the system clock of 250 MHz controls the data writing and reading of each channel of the FIFO.

[0037] The data transmission module uses a gigabit Ethernet data transmission solution and is completed based on the TCP / IP protocol that is most widely used in current computers. The TCP / IP protocol part uses the SiTcp IP core to implement the physical layer of Ethernet inside the FPGA and achieve gigabit data reading.

[0038] The measurement principle of the time-to-digital converter is as Figure 2 shown. It is implemented by combining "coarse counting" and "fine measurement". After the system is powered on, the reference clock counter starts to perform addition counting on the externally input reference clock signal. At the same time, the tapped delay line method is used to delay and measure each clock pulse in turn, and the propagation delay of the delay unit is used to finely quantify the time interval between adjacent clock pulses. "Coarse counting" realizes the measurement of the integer multiple interval of the reference clock period between the Start signal and the Stop signal, and "fine measurement" realizes the measurement of the time information less than one clock cycle. The obtained time interval is:

[0039] ΔT = T1 + T - T2

[0040] In the formula: T is the result of "coarse counting", which starts coarse counting with the rising edge of the signal Start and stops coarse counting with the falling edge of the Start signal, that is, an integer multiple of the reference clock period. T1 and T2 are the results of "fine measurement". As Figure 3As shown in the figure, a delay chain is formed by cascading a series of dedicated carry chain Carry 4 delay units, and then the Start signal is introduced into the delay chain for time interpolation. Theoretically, it is considered that the signal propagation delay through each delay unit is the same, which is a fixed value of 14 ps. Thus, the propagation delay of the delay unit can be used to finely quantify the time interval between adjacent clock pulses. After the Start signal enters the delay chain, a series of signals with different delays are obtained. The clock terminals of each D flip-flop in the flip-flop group are connected to the Start signal. When the rising edge of the global clock signal appears, each D flip-flop in the flip-flop group samples the state after each delay unit through the taps. The number of delay units that the Start signal passes through in the delay chain can be judged by the sampling results of the flip-flop group. Let the interpolation result of the Start signal be N1, the interpolation result of the Stop signal be N2, the count value of the counter be, the reference clock period be t, and the delay time of one delay unit in the tapped delay chain be LSB. It can be further expressed as:

[0041] ΔT = T1 + T - T2 = (W1 - W2)LSB + W3t

[0042] The processing flow is as Figure 4 shown. ΔT is the sum of the coarse count result and the fine count result, which is stored in the channel synchronous FIFO buffer of this channel and waits for the processor to read the measurement result.

[0043] In order to make the delay units evenly distributed in a chain, position constraints need to be added to determine the position of the first stage, and the next-stage units will be placed at the nearest positions. By replicating the single-channel TDC circuit, a 64-channel TDC can be integrated to meet the imaging requirements of the array system. The Start and Stop signals of each channel are independent of each other, and each channel corresponds to a delay chain and a decoding circuit.

[0044] The measured time data is transmitted to the image generation system through the PCIe interface. This system converts the received binary data into a byte-type channel array and a long-type time array, which respectively represent the channel numbers where the response occurs and the corresponding time tags.

[0045] The image generation system includes a parameter setting module, a data processing module, and an image display module, which improves the data processing speed through multi-threading and shared memory. First, the threshold values of the voltages collected by each channel of the TDC can be set. Since we use a row-column multiplexed readout circuit, the threshold voltages of all row responses are set to positive values, and the threshold voltages of all column responses are set to negative values. Then, the imaging frame rate is set, with an optional range of 1 to 30 frames, as well as the coincidence time window size T. Then, three threads execute concurrently. Thread 1 is responsible for pulling data from the TDC to the computer and storing it in the current data cache queue. Since new data will continuously be added to the cache queue during the real-time imaging process, to ensure the system stability, when the queue length is greater than the threshold, the reading of new data will automatically pause; Thread 2 is responsible for periodically taking out the data at the head of the queue for processing. For the i-th data, let A = Min(channel[i], channel[i + 1]), B = Max(channel[i], channel[i + 1]). If A < 33, 32 < B and time[i + 1] - time[i] < T are satisfied, then it can be determined that a response occurs at the corresponding row A and column B, and the pixel count value at the corresponding position is incremented by one. For the processed data, the Dispose method needs to be manually called in a timely manner to release resources and reduce the memory pressure; Thread 3 converts the calculated response count into a gray value at fixed intervals according to the imaging frame rate and generates a statistical graph with gray scale. Let the maximum pixel count value within the current time interval be N max , the minimum pixel count value is N min , then for the pixel with a count value of M, according to the gray scale normalization algorithm, the corresponding gray value G is:

[0046] G = 255 * (1 - (M - N min )) / (N max - N min ))

[0047] Taking the photon count of each pixel as its pixel intensity forms a new two-dimensional matrix, and this matrix is converted into a gray value image. The imaging result is as Figure 5 shown. The horizontal and vertical coordinates in the figure represent the column and row numbers respectively, preliminarily verifying the imaging performance of the system.

Claims

1. A signal acquisition and imaging system applicable to an array superconducting single photon detector, characterized in that, Including: An optical circuit, a readout circuit, a time-to-digital converter, and an image generation system; Construct an optical circuit for adjusting the direction of a laser pulse and focusing the optical pulse on the nanowire detection area; Through the readout circuit, obtain the response signals of the array of superconducting single-photon detectors. The row and column circuits connected to the pixels are amplified to generate two pulses with opposite polarities on the row and column respectively. Obtain the arrival time of each pulse signal through the time-to-digital converter, and transmit the information with timestamps to the image generation system through Gigabit Ethernet; The image generation system analyzes based on the received signals, calculates the actual optical response count values of each pixel, and generates the final visualized image through a gray-scale normalization algorithm. The time-to-digital converter includes a system clock module, a coarse counting module, a fine measurement module, a data storage module, and a data transmission module. The system clock module multiplies the input clock signal by frequency through an internal clock multiplier chip of the FPGA and outputs a 250 MHz reference clock. The coarse counting module measures the interval time that is an integer multiple of the reference clock period between the Start signal and the Stop signal. The fine measurement module measures the time information less than one clock cycle. The data storage module uses a synchronous FIFO for storage; The data transmission module performs high-speed data transmission through the PCIe protocol.

2. The signal acquisition and imaging system applicable to the array superconducting single-photon detector according to claim 1, characterized in that, The optical circuit includes a laser, a collimator, an attenuator, a convex lens, a mirror, a beam-splitting cube, a CCD, and a spatial light source. The laser and the spatial light source provide reference light. The collimator is used to collimate the light beam and reduce the laser divergence angle. The attenuator attenuates the light to prevent the nanowire from quenching due to excessive light intensity. The convex lens is responsible for focusing the spatial light. The mirror is responsible for reflecting the light onto the photosensitive surface of the SNSPD. The beam-splitting cube introduces the laser and the visible light source into the CCD camera, and the CCD camera monitors the light coupling situation.

3. The signal acquisition and imaging system applicable to the array superconducting single-photon detector according to claim 1, characterized in that, The readout circuit includes 64 T-type biasers and 64 RF amplifiers. The output end of the detector is connected to the RF and DC ports of the T-type biasers. The DC bias ports of 32 T-type biasers are connected to the bias circuit, and the other 32 DC bias ports are grounded. The RF port of the T-type biasers is connected to the input end of the RF amplifier. The output end of the RF amplifier is connected to the trigger signal input of the time-to-digital converter, and the digital converter is used to accurately measure the arrival time of the pulse signal.

4. The signal acquisition and imaging system applicable to the array superconducting single-photon detector according to claim 3, wherein The bias circuit is obtained by connecting a bias resistor and an adjustable voltage source in series. By controlling the adjustable voltage source, the detector is placed in a state below its critical current.

5. The signal acquisition and imaging system applicable to the array superconducting single-photon detector according to claim 1, wherein The time-to-digital converter is implemented by combining "coarse counting" and "fine measurement". The coarse counting module uses a binary counter. The fine measurement module uses a series of dedicated carry chain Carry 4 delay units to form a delay chain in cascade, and then introduces the Start signal into the delay chain for time interpolation, and finely quantifies the time interval between adjacent clock pulses using the propagation delay of the delay unit.

6. The signal acquisition and imaging system applicable to the array superconducting single-photon detector according to claim 1, characterized in that The time-to-digital converter calculates the time difference of the signal according to the following formula: ΔT = T1 + T - T2 = (N1 - N2)LSB + N3t Where N1 is the interpolation result of the Start signal, N2 is the interpolation result of the Stop signal, N3 is the count value of the counter, t is the reference clock period, and LSB represents the delay time of a delay unit in the tapped delay line.

7. The signal acquisition and imaging system applicable to the array superconducting single-photon detector according to claim 1, characterized in that, The image generation system is executed concurrently by three threads. Thread 1 is responsible for pulling data from the TDC into the computer and storing it in the current data cache queue. Thread 2 is responsible for periodically taking out the data at the head of the queue for processing and calculation. Thread 3 converts the calculated response count into grayscale values at fixed intervals according to the imaging frame rate. Let the maximum pixel count value within the current time interval be N max , and the minimum pixel count value be N min . Then, for a pixel with a count value of M, according to the grayscale normalization algorithm, the corresponding grayscale value G is: G = 255 * (1 - (M - N min ) / (N max - N min )) The photon count of each pixel is used as its pixel intensity to form a new two-dimensional matrix, and this matrix is converted into a grayscale image.

Images