Verification method and processing system for integrated circuits

Abstract

The present disclosure provides a verification method of an integrated circuit, a processing system and a computer readable storage medium. The integrated circuit comprises a plurality of modules, and the verification method comprises: for each module of the integrated circuit, obtaining power consumption values corresponding to a plurality of simulation windows based on signal value change data simulation corresponding to the module; selecting key data in the signal value change data of the module according to the size of the power consumption values corresponding to the simulation windows; and running top-level simulation of the integrated circuit based on the key data to obtain a voltage drop simulation result, which is used for comparison with a signature standard to confirm whether the verification is passed. The embodiments of the present disclosure can efficiently, accurately and at low cost realize analysis and verification of voltage drop.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to integrated circuit verification methods, processing systems, and computer-readable storage media. Background Technology

[0002] Before integrated circuit design data is delivered to chip manufacturers for production, a series of analyses and verifications are usually required to ensure that the design data meets delivery standards. This series of analyses and verifications is collectively called signoff, which helps relevant technical personnel to correct any deficiencies in the design data before tape-out, thereby saving costs.

[0003] In order for the chip to work properly, we need to provide a uniform and stable power supply to each unit of the chip. Each unit in the chip may be affected by voltage drop (IR drop), and the wires may also be affected by electron migration, which may cause the chip to malfunction.

[0004] As chip manufacturing processes become increasingly advanced, the width of metal lines in power and ground networks is narrowing, leading to a continuous increase in resistance per unit length of line while the supply voltage decreases. Therefore, the impact of voltage drop on chip performance becomes increasingly significant. Consequently, verifying whether the chip's power consumption and voltage drop analysis results meet the signoff standard is a necessary step before mass production. How to efficiently and accurately obtain power consumption and voltage drop analysis results and determine whether they meet the signoff standard has become an important issue in this technical field. Summary of the Invention

[0005] To address the problems existing in the prior art, this disclosure provides a verification method, processing system, and computer-readable storage medium for integrated circuits. The solutions according to the embodiments of this disclosure can improve the efficiency and accuracy of voltage drop simulation and the utilization rate of storage space, while reducing the consumption of storage space, time costs, and labor costs.

[0006] According to one aspect of the present invention, a verification method for an integrated circuit is provided. The integrated circuit includes multiple modules, wherein the verification method includes: for each module, simulating power consumption values ​​corresponding to multiple simulation windows based on signal value change data corresponding to that module; selecting key data from the signal value change data of that module according to the magnitude of the power consumption value corresponding to each simulation window; and running a top-level simulation of the integrated circuit based on the key data to obtain voltage drop simulation results, wherein the voltage drop simulation results are used to compare with an approval standard to confirm whether the verification is successful.

[0007] In some embodiments, the step of selecting key data from the signal value change data of a module based on the power consumption value corresponding to each of the simulation windows includes: for each module, determining the simulation window corresponding to the maximum power consumption value among the plurality of simulation windows as the key window of the module; and limiting the signal value change data corresponding to the maximum power consumption value according to the key window to obtain a key data segment of the module, and obtaining the key data of the module according to the key data segment.

[0008] In some embodiments, each module corresponds to at least one of the signal value change data under different test cases. For each module, the step of simulating and obtaining the power consumption value corresponding to multiple simulation windows based on the signal value change data corresponding to the module includes: for each module, running the module-level simulation based on each of the signal value change data corresponding to the module to obtain the power consumption value corresponding to each of the signal value change data under the multiple simulation windows.

[0009] In some embodiments, the step of running a top-level simulation of the integrated circuit based on the key data to obtain voltage drop simulation results includes: for each test case of each module, running the top-level simulation based on the key data corresponding to the signal value change data of the test case and the non-vector data of each module other than the module in the integrated circuit to obtain the voltage drop simulation results of the module under each test case. The key window corresponding to the signal value change data of each test case is a simulation window in which the signal value change data provides the maximum power consumption value within the plurality of simulation windows. The key data corresponding to the signal value change data of each test case is determined based on the key data segment of the signal value change data defined by the simulation window.

[0010] In some embodiments, the step of selecting key data from the signal value change data of the module based on the power consumption value corresponding to each simulation window includes: determining the key data segment with the maximum power consumption value among the key data segments of each branch of signal value change data corresponding to the module by comparing the power consumption values ​​corresponding to all the signal value change data of the module under each simulation window; and determining the key data of the module based on the key data segment with the maximum power consumption value, wherein the key data of the module includes at least the key data segment with the maximum power consumption value.

[0011] In some embodiments, the step of running a top-level simulation of the integrated circuit based on the key data to obtain voltage drop simulation results includes: determining a data base for the top-level simulation, the data base including combinations of the key data respectively corresponding to the plurality of modules; and loading the data base into a simulation environment and running the top-level simulation of the integrated circuit in the simulation environment to obtain the voltage drop simulation results.

[0012] In some embodiments, for each module, the step of obtaining power consumption values ​​corresponding to multiple simulation windows based on the signal value change data corresponding to the module includes: aligning the signal value change data corresponding to the multiple modules in time and running the power consumption simulation as a whole to obtain the overall power consumption value corresponding to the multiple simulation windows; the step of selecting key data in the signal value change data of the module according to the magnitude of the power consumption value corresponding to each simulation window includes: selecting the simulation window corresponding to the maximum power consumption value in the overall power consumption value as the key window of the multiple modules, and limiting the signal value change data of each module based on the key window to obtain the key data of each module.

[0013] In some embodiments, the time widths of the plurality of simulation windows are consistent; and / or the time difference between any two simulation windows that are adjacent in time sequence is consistent.

[0014] In some embodiments, the time difference corresponds to the reciprocal of the maximum value of each signal frequency used by the integrated circuit.

[0015] In some embodiments, the plurality of modules includes: a plurality of sub-modules, each having a circuit structure for implementing a corresponding function; and a top-level module that calls the plurality of sub-modules.

[0016] According to a second aspect of the present disclosure, a processing system is provided, comprising: a processor for executing a verification tool; and a storage device for providing runtime space and data storage space for the verification tool. The verification tool is configured to execute a verification method according to any embodiment of the present disclosure.

[0017] According to a third aspect of the present disclosure, a computer-readable storage medium is also provided, having instructions stored thereon, wherein the instructions are executed by one or more processing units to implement the verification method of any embodiment of the present disclosure.

[0018] According to the various embodiments provided in this disclosure, signal value change data corresponding to each module can be simulated based on multiple simulation windows to obtain the corresponding power consumption values. A portion of the signal value change data is selected as key data based on the magnitude of the power consumption values, serving as the data foundation for the top-level simulation. The amount of key data selected based on power consumption values ​​is less than the total amount of signal value change data, thus significantly improving the efficiency of voltage drop simulation, reducing the storage space requirements, and increasing storage space utilization. Simultaneously, the key data selected based on the magnitude of power consumption values ​​can represent the worst-case voltage drop scenario corresponding to the corresponding signal value change data, thereby ensuring the accuracy of voltage drop verification.

[0019] In some preferred embodiments, module-level power consumption simulations can be performed on each module of the integrated circuit to obtain power consumption values ​​corresponding to multiple simulation windows. Based on these power consumption values, key data for each module is determined. Then, a top-level flattening voltage drop simulation is run based on the key data of each module in the integrated circuit to obtain voltage drop simulation results for comparison with the approval standard. Module-level simulation allows for the determination of key data for each module based on its power consumption, rather than basing the data on the overall power consumption of the integrated circuit, thus ensuring the accuracy of voltage drop verification. Furthermore, running a top-level flattening simulation based on the key data of each module in the voltage drop simulation helps cover the worst-case voltage drop scenarios for each module and improves the efficiency of the voltage drop simulation.

[0020] In some preferred embodiments, for each module, the key data segment with the maximum power consumption value among the key data segments of each VCD data corresponding to that module can be determined by comparing power consumption values, and the key data of that module at least includes the key data segment with the maximum power consumption value. Based on this, the key data of that module corresponds to the key data segment with the maximum power consumption value under all test cases and simulation scenarios. Therefore, the key data of each module determined based on this example is sufficient to characterize the worst voltage drop scenario of the integrated circuit, and valuable voltage drop simulation results can be obtained by performing voltage drop simulation at least once. This further improves the verification efficiency of the integrated circuit, saves the running time and number of runs of voltage drop simulation, and improves the utilization of storage space while ensuring verification accuracy.

[0021] Furthermore, based on this preferred embodiment, since the module-level simulation runtime is very short and the top-level voltage drop simulation is only run based on key data corresponding to the maximum power consumption value in each scenario, the voltage drop simulation runtime is basically unrelated to the number of VCD data and test cases provided by the front end. This allows the front end to provide corresponding VCD data based on more comprehensive and more test cases, further improving the accuracy of voltage drop verification. Attached Figure Description

[0022] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0023] Figure 1 A schematic diagram of an integrated circuit structure is shown.

[0024] Figure 2 This diagram illustrates the relationship between the running time required for voltage drop simulation in traditional methods, the simulation duration corresponding to the VCD data used for voltage drop simulation, and the scale of the integrated circuit.

[0025] Figure 3 A schematic diagram of a simulation setup for a verification method of integrated circuits is shown.

[0026] Figure 4 A simulation setup diagram illustrating another verification method for integrated circuits is shown.

[0027] Figure 5 Show Figure 4 A schematic diagram illustrating the steps involved in obtaining the critical data segment using the verification method shown.

[0028] Figure 6 A flowchart illustrating a verification method for an integrated circuit according to an embodiment of the present disclosure is shown.

[0029] Figure 7 A schematic diagram illustrating the steps for obtaining key data for voltage drop simulation according to an embodiment of the present disclosure;

[0030] Figure 8 This diagram illustrates an exemplary implementation of voltage drop verification based on key data from each module, according to an embodiment of this disclosure.

[0031] Figure 9 A schematic diagram showing an example of data setup for simulating the voltage drop at the top-level flattening stage according to an embodiment of this disclosure;

[0032] Figure 10 A schematic diagram showing another example of data setup for simulating the voltage drop at the top-level flattening stage according to an embodiment of this disclosure;

[0033] Figure 11 A schematic diagram of the structure of a processing system provided according to an embodiment of the present disclosure is shown. Detailed Implementation

[0034] The present invention is described below based on embodiments, and many specific details of the invention are described in the hereinafter to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details, i.e., the invention is not limited to these embodiments. To avoid obscuring the essence of the invention, well-known methods, processes, procedures, chip devices, and chip circuits are not described in detail.

[0035] The same chip devices are represented by similar reference numerals in the various figures. Furthermore, those skilled in the art should understand that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0036] Before introducing exemplary embodiments of this application, the terms used in this application will be explained in order to help those skilled in the art to better understand this application.

[0037] Voltage drop (IR drop): This generally refers to the voltage loss caused by the traces from the power supply voltage and ground voltage to the circuit unit in an integrated circuit. Each unit in an integrated circuit can be affected by voltage drop. A high voltage drop slows down the signal propagation to the next unit. When the voltage drop exceeds a certain level, it can lead to insufficient settling time, preventing the chip from achieving the required performance, or even failure due to insufficient retention time. To ensure the proper functioning of an integrated circuit, we need to provide a uniform and stable power supply to each unit. Therefore, before the integrated circuit is delivered for production, voltage drop simulation and verification of each unit are required to ensure that the voltage drop of each unit meets the signoff standard. Voltage drop can be divided into static voltage drop and dynamic voltage drop. Static voltage drop is usually the product of constant current and equivalent resistance, calculated given the total power consumption and the equivalent resistance of the power network. Dynamic voltage drop usually refers to the voltage drop caused by current fluctuations due to logic transitions in digital circuits; that is, dynamic voltage drop mainly depends on the digital logic transition activities. Unless otherwise specified, the voltage drop simulation described in this disclosure includes at least the simulation of dynamic voltage drop, and may also include the simulation of static voltage drop.

[0038] Value change dump (VCD) data refers to simulation waveform data that characterizes the actual operating state of the signal values ​​of all gate cells, obtained by simulating the integrated circuit design data based on the chip's real operating scenarios. This data, as the output of the front-end simulation, can be generated based on a place and route (PR) database. Because VCD data contains signal change information, it essentially records the entire simulation information. Therefore, during the signoff process, the simulation can be reproduced based on VCD data to analyze and verify power consumption, voltage drop, etc. Based on different test cases (e.g., setting constraints such as temperature, power supply voltage, and input signal states to test performance under different scenarios), the same circuit cell can be simulated to obtain VCD data under multiple test cases. VCD data is generally stored in VCD files, which typically contain header information, predefined variables, and variable value change information. As an example, a VCD file can be an ASCII file defined based on the IEEE 1364 standard (Verilog HDL language standard).

[0039] The conventional techniques and embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0040] Figure 1 A schematic diagram of an integrated circuit is shown.

[0041] like Figure 1 As shown, in integrated circuit 100, the modules that can be used as block-level simulation objects can be the n sub-modules Block1 to Blockn (n is a natural number greater than 1) within integrated circuit 100, or the top-level module Top0 that calls these n sub-modules Block1 to Blockn. Top-level module Top0 is used to establish signal relationships between different sub-modules and may include parts outside the n sub-modules Block1 to Blockn (such as interface units, etc.). Furthermore, in voltage drop simulation, it is usually necessary to run a top-level flattening simulation of the integrated circuit, that is, to import all components in the integrated circuit to fully verify the various functions and performance of the entire integrated circuit.

[0042] During the front-end simulation phase, each sub-module (Blocks 1 through 1) and the top-level module can be simulated under different test cases based on information such as layout and routing. This yields VCD data (including simulation waveform information of various related signals) for each sub-module and the top-level module under multiple test cases. This series of VCD data can be stored separately as VCD files, meaning that each sub-module and the top-level module can correspond to multiple VCD files (each corresponding to a different test case).

[0043] Since VCD data reflects signal value changes under various test cases, power consumption and voltage drop simulations can be performed based on it. Analyzing and verifying the voltage drop of integrated circuit design data is a crucial step in the signoff stage, primarily used to determine whether the voltage drop simulation results meet the signoff criteria. To ensure signoff quality and the performance of the final chip, the accuracy and appropriateness of the signoff environment settings are particularly important.

[0044] Figure 2 This diagram illustrates the relationship between the runtime required for voltage drop simulation in traditional methods, the simulation duration corresponding to the VCD data used for voltage drop simulation, and the scale of the integrated circuit. The horizontal axis represents the simulation duration T corresponding to the VCD data used for voltage drop simulation. VCD (Units are, for example, ns), the vertical axis of the coordinate system represents the running time T required for the voltage drop simulation. run (Units, for example, days), and Figure 1 The figure roughly illustrates the runtime T required for voltage drop simulation of small-scale, medium-scale, and large-scale designs. run The simulation duration T corresponding to the VCD data used for voltage drop simulation. VCD The correspondence.

[0045] from Figure 2 It can be seen that the simulation duration T corresponding to the VCD data used for voltage drop simulation VCD The longer the duration, the longer the running time T required for voltage drop simulation. run The longer the duration, the longer the running time T required for voltage drop simulation. run The simulation duration T, roughly corresponding to the VCD data on which the voltage drop simulation is based. VCD The increase in voltage drop is exponential; simultaneously, as the scale of integrated circuits increases, the running time T required for voltage drop simulation also increases. run The simulation duration T corresponding to the VCD data used for voltage drop simulation VCD All of these increased accordingly.

[0046] In practical applications, to ensure the accuracy of VCD data and / or to ensure that the VCD data sufficiently describes the waveforms of various signal values ​​of the integrated circuit in real-world operating scenarios, the simulation duration corresponding to the VCD data in the VCD file provided by the front-end engineer is generally higher than a certain value, such as 100ns, 200ns, or even 1000ns. When analyzing and verifying the voltage drop during the signoff phase, if the simulation is performed directly based on the complete VCD file provided by the front-end engineer, a very long simulation runtime T is required. run For example, for an integrated circuit design with 10 million instances using TSMC's 7ns process, it would take at least 7 days to simulate the voltage drop during the signoff stage directly based on a 100ns VCD file.

[0047] Therefore, in traditional verification methods, in order to improve accuracy and cover the worst-case simulation scenarios, voltage drop simulations require a relatively long runtime T. run This also leads to a significant increase in memory and hard drive space usage. If the running time T is shortened... run Reducing the number of test cases may result in the worst-case scenario not being verified to meet the signoff criterion, thus reducing the accuracy of the environment settings for voltage drop simulation.

[0048] According to various embodiments of this disclosure, considering the iteration time, during the signoff phase, voltage drop simulation is typically not performed based on the complete VCD file provided by the front end. Instead, a VCD data segment from the VCD file provided by the front end is selected based on the time axis as the key data segment for voltage drop simulation (e.g., corresponding to simulation duration T). VCD =20ns).

[0049] Figure 3 This diagram illustrates a simulation setup for a verification method of an integrated circuit.

[0050] To ensure comprehensive voltage drop simulation coverage (i.e., to cover the worst-case scenario), this example employs a mixed dynamic VCD simulation mode based on the key data segments of each module. The mixed dynamic VCD simulation mode combines a VCD data-based simulation mode with a vectorless simulation mode that does not require VCD data.

[0051] In practice, the hybrid dynamic VCD simulation mode can be applied, for example, when the VCD data of the top-level module is generated at the front end, for verification based on the VCD data of each sub-module Block1 to Blockn. However, based on actual needs, this hybrid dynamic VCD simulation mode can also be implemented based on the VCD data of each sub-module Block1 to Blockn and the top-level module Top0, and this disclosure does not limit it in this way.

[0052] Specifically, for example Figure 3 As shown, for one of the n sub-modules Block1 to Blockn, the target module ( Figure 3 Taking submodule Block1 as the target module as an example, when simulating power consumption and voltage drop, other modules besides the target module can be set to non-vector mode (no need to load the corresponding VCD data, only the non-vector data related to the module needs to be loaded). At the same time, based on the VCD data of the target module under each test case, the top-level flattening power consumption simulation is run separately to obtain the power consumption value corresponding to the VCD data of each test case under multiple simulation windows.

[0053] For each test case's VCD data, the simulation window corresponding to the maximum power consumption value in multiple simulation windows can be determined as the critical window for that VCD data. The VCD data segment defined by this critical window is considered the critical data segment for that VCD data. Since voltage drop typically increases with power consumption, and a larger voltage drop indicates a more severe voltage drop, the VCD data segment defined by the simulation window corresponding to the maximum power consumption value can be used as the critical data segment for signoff verification of the voltage drop. In other words, if the voltage drop simulation result based on this critical data segment meets the signoff criterion, it means that the target module can also meet the signoff criterion in other data segments of the VCD data besides the critical data segment. Therefore, it is not necessary to perform voltage drop simulation based on the entire complete VCD data; only the voltage drop simulation based on the critical data segment of the VCD data is needed for signoff verification.

[0054] Similarly, in this example, when running voltage drop simulation for the target module, other modules besides the target module are still set to non-vector mode. Simultaneously, top-level flattened voltage drop simulation is run sequentially based on the key data segments of the target module under each test case to obtain the voltage drop simulation results for the key data segments of each test case. Based on the above principle, it can be seen that by determining whether the voltage drop simulation results corresponding to each test case meet the signoff criterion, it can be determined whether the voltage drop of the target module can be verified as acceptable.

[0055] Based on this example, assuming that each module corresponds to k test cases (k is an integer greater than 0), the voltage drop simulation for n sub-modules needs to be run n*k times. This consumes a lot of memory and disk space, time and manpower, and also makes the simulation and verification of voltage drop inefficient.

[0056] Figure 4 A simulation setup diagram illustrating another verification method for integrated circuits is shown. Figure 5 Show Figure 4 The diagram illustrates the steps involved in obtaining the critical data segment using the verification method shown.

[0057] To further optimize the efficiency of voltage drop simulation and reduce cost and storage space consumption, as an example, such as Figure 4 As shown, the power consumption and voltage drop simulation of the top-level flattening stage can be performed using the VCD simulation mode based on the VCD data of each of the n sub-modules Block1 to Blockn and the top-level module Top0, instead of using the non-vector mode in the example above.

[0058] Specifically, such as Figure 4 and 5 As shown in this example, the VCD data of each of the n sub-modules Block1 to Blockn and the top-level module Top0 can be loaded into the simulation environment simultaneously (taking the VCD data with the maximum total power consumption value corresponding to each module, VCD_jmax, as an example, corresponding to the top-level module Top0 and each sub-module Block1 to Blockn, where j is 0 to n respectively). This VCD data can then be time-aligned (start time alignment and / or end time alignment), and a top-level flattening power consumption simulation can be run on the time-aligned n+1 VCD data using multiple simulation windows. This means obtaining the power consumption values ​​corresponding to each simulation window by sequentially scanning through multiple simulation windows. In some examples, the data used to align and run the top-level flattening power consumption simulation may only correspond to the VCD data of the n sub-modules Block1 to Blockn, excluding the VCD data of the top-level module Top0.

[0059] For this VCD data set, the simulation window w[i] = [t1, t2] (where i is an integer greater than 0) corresponding to the maximum power consumption value in multiple simulation windows can be determined as the key window corresponding to this VCD data set. The VCD data segments of the n+1 VCD data sets in this VCD data set that are defined by the key window are taken as the n+1 key data segments corresponding to this VCD data set (e.g., Figure 4The values ​​of VCD_0max[t1,t2] to VCD_nmax[t1,t2] are shown, and subsequent voltage drop simulations are performed based on these n+1 key data segments to determine whether the integrated circuit design data meets the voltage drop signoff standard.

[0060] Based on this example, regardless of how many test cases the front end uses to obtain VCD data for each module, the voltage drop simulation for n sub-modules and the top-level module only needs to be run once at least. Compared with the above example, this greatly reduces the consumption of storage space, time cost and manpower cost, and can significantly improve the utilization of storage space and the verification efficiency of voltage drop.

[0061] The limitation of this example is that, since the critical window is selected based on the overall power consumption value corresponding to the combination of aligned VCD data, the data segments defined by this critical window may not be the data segments that generate the maximum power consumption value in the corresponding VCD data. This means that the critical window selected in this example only limits the n+1 data segments that generate the overall maximum power consumption of the integrated circuit. This maximum power consumption may only be caused by a few modules, and other modules may not be operating in a high-power state. In other words, the n+1 critical data segments defined by the critical window selected in this example cannot cover the scenario where every module is operating under the worst voltage drop condition. Therefore, although the verification method provided in this example can improve efficiency and reduce costs, its accuracy is reduced. Integrated circuits that pass the verification method of this example may have risks related to voltage drop issues in real-world operating scenarios.

[0062] Therefore, this disclosure provides yet another embodiment to further optimize the method for signoff verification of voltage drop in integrated circuits.

[0063] Figure 6 A flowchart illustrating a verification method for an integrated circuit according to an embodiment of the present disclosure is shown. Steps S110 to S140 are illustrated.

[0064] In step S110, for each module of the integrated circuit (each sub-module and the top-level module), the corresponding VCD data is obtained. As mentioned above, as an example, the front end can simulate each module based on different test cases to obtain multiple VCD data under different simulation scenarios, that is, each module can correspond to one or more VCD data.

[0065] In step S120, for each module, a module-level simulation is run based on the corresponding VCD data to obtain power consumption values ​​corresponding to multiple simulation windows. Based on this series of power consumption values, the key data for the module is determined. Specifically, for each module, the simulation window corresponding to the maximum power consumption value among the multiple simulation windows is designated as the key window for that module. Data obtained by limiting the VCD data corresponding to the maximum power consumption value based on this key window is then used as the key data for that module.

[0066] Figure 7 This diagram illustrates the steps for obtaining key data for voltage drop simulation according to an embodiment of the present disclosure. The following explanation is based on a VCD data set VCD_j1 under a test case corresponding to submodule Blockj in integrated circuit 100. The total simulation time corresponding to this VCD data set VCD_j1 is denoted as T. VCD_all .

[0067] like Figure 7 As shown, as an example, in the module-level power consumption simulation for submodule Blockj, m simulation windows w[1] to w[m] can be set sequentially according to time order, and m power consumption values ​​corresponding to the VCD data segment limited by each simulation window can be obtained respectively, where m is a natural number greater than 1. Among them, the start time of the first simulation window w[1] corresponds to the start time of the VCD data VCD_j1, and the end time t of the last simulation window w[m] is... m It may correspond to the end time of the VCD data VCD_j1, or it may be located before the end time of the VCD data VCD_j1.

[0068] To facilitate power consumption comparison, all m simulation windows w[1] to w[m] have the same time width T. w The time width T of each simulation window w This can be set according to the desired simulation accuracy and simulation runtime, for example, it can be set to less than or equal to 100 ns. As a reference example, the time width T for each simulation window... w For example, it can be selected as 10ns or 20ns, etc.

[0069] In this embodiment, for the VCD data VCD_j1, module-level power consumption simulation is run based on simulation windows w[1] to w[m] respectively, and m corresponding power consumption values ​​(e.g., at least dynamic power consumption values) can be obtained. Then, by comparison, the maximum power consumption value Pmax among the m power consumption values ​​is determined, and the VCD data segment VCD_j1[ti-Δts,ti] defined by the simulation window w[i] corresponding to the maximum power consumption value is confirmed. The simulation window w[i] is taken as the key window of the VCD data VCD_j1, and the VCD data segment VCD_j1[ti-Δts,ti] is taken as the key data segment of the VCD data VCD_j1. Where i is an integer greater than or equal to 1 and less than or equal to m.

[0070] As an example, a first storage space can be specified (e.g., provided by memory and / or registers, and storing an initial value of 0). During the module-level power consumption simulation based on simulation windows w[1] to w[m], the power consumption value obtained by the current simulation window through module-level power consumption simulation is compared with the power consumption value stored in the first storage space. The larger of the two power consumption values, along with its corresponding simulation window and / or corresponding VCD data segment, is stored in the first storage space. Thus, after each simulation window w[1] to w[m] has completed module-level power consumption simulation, the power consumption value stored in the first storage space is the maximum power consumption value Pmax among the m power consumption values. Based on the data in the first storage space, the key data segment, key window, and their corresponding power consumption value of the VCD data can be obtained. This example is merely one possible implementation. The embodiments disclosed herein are not limited to this. The maximum power consumption value Pmax and its corresponding key data segment can also be obtained in other ways. For example, the power consumption values ​​corresponding to all simulation windows can be stored in the first storage space first, and then the m power consumption values ​​can be compared to obtain the maximum power consumption value Pmax. Alternatively, the simulation window corresponding to the maximum power consumption value Pmax can be marked as a key window by marking. Subsequently, the key window and key data segment corresponding to the maximum power consumption value can be located based on the marking, and so on.

[0071] In some optional embodiments, the time difference between the start times of any two adjacent simulation windows can be a fixed preset value Δts, which can be less than, greater than, or equal to the time width T of a single simulation window. w As an example, the preset value Δts could be set to the reciprocal of the highest frequency used by the entire integrated circuit system.

[0072] In some alternative embodiments, the end time t of the last simulation window w[m] mThe time difference between the start time of the VCD data VCD_j1 and the end time of the VCD data VCD_j1 can be less than or equal to a preset value Δts. However, the embodiments of this disclosure are not limited to this. For example, in some optional embodiments, the time difference between the start times of adjacent simulation windows can be set as needed (e.g., the time difference between multiple simulation windows close to the start and / or end times of data VCD_j1 is smaller, the time difference between multiple simulation windows far from the start and / or end times of data VCD_j1 is larger, etc.), and is not necessarily a fixed value; and / or, the end time t of the last simulation window w[m] m The time difference between the end time of the VCD data VCD_j1 and the end time of the VCD may also be greater than Δts, etc.

[0073] In some optional embodiments, different simulation windows may overlap. As an example, when the time difference between the start times of any two adjacent simulation windows is a fixed preset value Δts (greater than 0), this preset value Δts is less than the time width T of a single simulation window. w This allows multiple adjacent simulation windows to overlap, which can improve simulation accuracy and comprehensiveness. However, the embodiments disclosed herein are not limited to this. For example, to further reduce simulation runtime and improve storage space utilization, adjacent simulation windows can also be set to not overlap.

[0074] It should be noted that, although Figure 7 The illustrated embodiment is based on only one VCD data set under one test case corresponding to one of multiple submodules. However, in reality, integrated circuits typically include multiple submodules (e.g., Figure 1 As shown, not only can each submodule obtain multiple VCD data sets based on multiple test cases at the front end, but the top-level module used to establish signal relationships between different submodules can also obtain multiple VCD data sets based on multiple test cases at the front end. Those skilled in the art will understand that for the multiple VCD data sets under different test cases corresponding to each submodule and the top-level module, the corresponding key windows and key data segments can be obtained respectively according to the embodiments described above.

[0075] Taking each submodule and top-level module as corresponding to k types of test cases (k being an integer greater than or equal to 1) as an example (i.e., each submodule and top-level module correspond to k VCD data respectively), the information shown in Table 1 below can be stored in a designated second storage space (e.g., provided by memory and / or registers):

[0076] Table 1 shows the modules and their corresponding VCD data, key windows, and power consumption values.

[0077]

[0078]

[0079] Return to reference Figure 6 After completing step S120 for performing module-level power consumption simulation on each sub-module and the top-level module, this embodiment of the present disclosure may further execute steps S130 and S140 to further perform top-level flattening voltage drop simulation based on the above information, thereby verifying whether the voltage drop meets the signoff standard.

[0080] Specifically, in step S130, a top-level simulation (flattened level) is run based on the key data (including corresponding key data segments) of all modules in the integrated circuit to obtain voltage drop simulation results. In step S140, the voltage drop simulation results can be compared with the approval criteria using automated programs or statistical tools to confirm whether the voltage drop of the integrated circuit has passed verification. If the voltage drop simulation results meet the approval criteria, the voltage drop verification of the integrated circuit is confirmed to have passed; otherwise, it indicates that the voltage drop of the integrated circuit does not meet the approval criteria and further debugging is required.

[0081] Step S130 of this disclosure embodiment can be used to verify the voltage drop signoff of the integrated circuit based on key data of each module through various implementation methods.

[0082] Figure 8 This diagram illustrates an exemplary implementation of voltage drop verification based on key data from each module, according to an embodiment of this disclosure. Based on... Figure 8 In the embodiment shown, step S130 may include sub-steps S131 to S133. Figure 9 This diagram illustrates an example of data setup for simulating the voltage drop at the top-level flattening stage, according to an embodiment of this disclosure.

[0083] In step S131, the data basis for voltage drop simulation is determined. Specifically, as an example, for each module, a key data segment provided by one of the corresponding VCD data is selected and loaded into the simulation environment as the data basis for voltage drop simulation.

[0084] As can be seen from the example above, this data foundation includes n+1 key data points corresponding to each sub-module and the top-level module in the integrated circuit.

[0085] As an example, in step S131, for each module, the power consumption values ​​corresponding to the key data segments of each VCD data corresponding to the module can be compared to determine the maximum power consumption value, and the key data of the module can be determined according to the key data segment corresponding to the maximum power consumption value.

[0086] For example, referring to Table 1, taking the submodule Blockj as an example, the key data segments of its corresponding k VCD data VCD_j1 to VCD_jk are VCD_j1[t j1 -Δts,t j1 ]to VCD_jk[t jk -Δts,t jk The power consumption values ​​corresponding to these k key data segments are Pmax_j1 to Pmax_jk, respectively. By comparing these k power consumption values ​​Pmax_j1 to Pmax_jk, the maximum power consumption value Pmaxj among the k power consumption values ​​can be further determined. Assuming that the maximum power consumption value Pmaxj is Pmax_j1, it means that the key data segment VCD_j1[t] corresponds to this power consumption value Pmax_j1. j1 -Δts,t j1 This can characterize the scenario where the submodule Blockj experiences the highest voltage loss under various test cases; therefore, this critical data segment VCD_j1[t] can represent the scenario where the voltage loss of the submodule Blockj is highest under various test cases. j1 -Δts,t j1 This data can be used as key data for submodule Blockj. In other words, if the voltage drop simulation results obtained based on the key data segment corresponding to the maximum power consumption value Pmaxj meet the signoff criterion, it indicates that the VCD data segment corresponding to submodule Blockj can meet the signoff criterion under various scenarios and simulation windows.

[0087] Based on this method, n+1 key data points corresponding to each sub-module and the top-level module of integrated circuit 100 can be selected respectively. Correspondingly, the information shown in Table 2 can be stored in the second storage space:

[0088] Table 2 shows the modules, their corresponding maximum power consumption values, and key data for each module.

[0089]

[0090]

[0091] As shown in Table 2 and Figure 9 As shown, the key data VCD_1x[t] corresponding to each sub-module Block1 to Blockn and the top-level module Top0 of integrated circuit 100 are... 1x -Δts,t 1x ], ..., VCD_0x[t 0x -Δts,t 0xThese data points can be combined to form the data base for voltage drop simulation. These key data points, selected based on power consumption values, can characterize the voltage drop of the corresponding module under worst-case voltage loss scenarios. Therefore, based on this selected data base, the accuracy of voltage drop simulation is high, and the voltage drop verification results are more reliable.

[0092] In step S132, the determined data base is loaded into the simulation environment so that the top-level flattened voltage drop simulation can be run based on the key data in the determined data base, thereby obtaining the voltage drop simulation results.

[0093] If each key data point in the data foundation is obtained based on a simulation window with the same time width, then the simulation duration corresponding to each key data point is consistent. In this case, the key data points in the determined data foundation that correspond to their respective time periods can run the simulation synchronously without needing to be aligned.

[0094] It should be noted that the embodiments disclosed herein are not limited to the examples described above, and many modifications, substitutions, and variations may exist.

[0095] For example, as another example of step S131, the n+1 key data points serving as the data basis can be combined based on the relevance of the corresponding test cases or other conditions, and can be selected without being based on power consumption values. For example, Figure 10 This diagram illustrates another example of data setup for simulating the voltage drop at the top-level flattening stage, according to an embodiment of this disclosure.

[0096] The key data segments with the maximum power consumption corresponding to the first VCD data of each module can be combined into the first data base (e.g., Figure 10 As shown, the key data segments corresponding to the second VCD data of each module are combined into the second data base, and so on, until the key data segments corresponding to the kth VCD data of each module are combined into the kth data base. Based on this example, subsequent steps S132 and S133 can be executed respectively based on the first to k data bases, thereby obtaining multiple voltage drop simulation results by running the voltage drop simulation multiple times. In step S140, these multiple voltage drop simulation results are compared with the voltage drop signoff standard. Based on this example, the voltage drop verification of the integrated circuit 100 is qualified only if all voltage drop simulation results meet the voltage drop signoff standard; otherwise, the verification is unqualified and further debugging and re-verification are required.

[0097] For example, the data basis for voltage drop simulation is not limited to having a duration consistent with the simulation window. The n+1 key data included in the data basis may also include related data beyond the selected n+1 key data segments. As an example, for each key data selected as part of the data basis, it may include not only the key data segment of the corresponding VCD data, but also adjacent data segments located before and / or after it on the time axis. As yet another example, the power consumption values ​​of the key data segments of multiple VCD data corresponding to each module can be sorted, and multiple key data segments with larger power consumption values ​​can be combined as the key data of that module and used as the data basis for performing voltage drop simulation. Those skilled in the art will understand that, inspired by the various examples provided in this disclosure, the selection of the data basis can have various modifications and substitutions, all of which should be limited to the protection scope of this invention.

[0098] According to the various embodiments provided in this disclosure, signal value change data corresponding to each module can be simulated based on multiple simulation windows to obtain the corresponding power consumption values. A portion of the signal value change data is selected as key data based on the magnitude of the power consumption values, serving as the data foundation for the top-level simulation. The amount of key data selected based on power consumption values ​​is less than the total amount of signal value change data, thus significantly improving the efficiency of voltage drop simulation, reducing the storage space requirements, and increasing storage space utilization. Simultaneously, the key data selected based on the magnitude of power consumption values ​​can represent the worst-case voltage drop scenario corresponding to the corresponding signal value change data, thereby ensuring the accuracy of voltage drop verification.

[0099] In some preferred embodiments, module-level power consumption simulations can be performed on each module of the integrated circuit to obtain power consumption values ​​corresponding to multiple simulation windows. Based on these power consumption values, key data for each module is determined. Then, a top-level flattening voltage drop simulation is run based on the key data of each module in the integrated circuit to obtain voltage drop simulation results for comparison with the approval standard. Module-level simulation allows for the determination of key data for each module based on its power consumption, rather than basing the data on the overall power consumption of the integrated circuit, thus ensuring the accuracy of voltage drop verification. Furthermore, running a top-level flattening simulation based on the key data of each module in the voltage drop simulation helps cover the worst-case voltage drop scenarios for each module and improves the efficiency of the voltage drop simulation.

[0100] In some preferred embodiments, for each module, the key data segment with the maximum power consumption value among the key data segments of each VCD data corresponding to that module can be determined by comparing power consumption values, and the key data of that module at least includes the key data segment with the maximum power consumption value. Based on this, the key data of that module corresponds to the key data segment with the maximum power consumption value under all test cases and simulation scenarios. Therefore, the key data of each module determined based on this example is sufficient to characterize the worst voltage drop scenario of the integrated circuit, and valuable voltage drop simulation results can be obtained by performing voltage drop simulation at least once. This further improves the verification efficiency of the integrated circuit, saves the running time and number of runs of voltage drop simulation, and improves the utilization of storage space while ensuring verification accuracy.

[0101] Furthermore, based on this preferred embodiment, since the module-level simulation runtime is very short and the top-level voltage drop simulation is only run based on key data corresponding to the maximum power consumption value in each scenario, the voltage drop simulation runtime is basically unrelated to the number of VCD data and test cases provided by the front end. This allows the front end to provide corresponding VCD data based on more comprehensive and more test cases, further improving the accuracy of voltage drop verification.

[0102] Figure 11 A schematic diagram of the structure of a processing system 200 provided according to an embodiment of the present disclosure is shown.

[0103] like Figure 11 As shown, the processing system 200 mainly includes a storage device 210 and a processor 220, which are used to perform simulation verification of the design data of the integrated circuit to be verified.

[0104] Storage device 210 may be, for example, a storage array, a shared directory, etc., used to store design data of integrated circuit 100, databases required for simulation, VCD data corresponding to each module, and files used to specify signoff standards, etc., and may also provide the first storage space and / or the second storage space mentioned above. This disclosure does not limit the specific hardware implementation of storage device 210, for example, it may be static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, read-only optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices or any other non-transmission medium, which can be used to store information that can be accessed by computing devices.

[0105] Processor 220 is coupled and communicates with storage device 210 to execute verification tool 10 based on information provided by storage device 210. This verification tool is configured to perform simulation and / or verification methods for integrated circuits as described in any embodiment of this disclosure. Storage device 210 provides operating space and data storage space for verification tool 10. Processor 220 may be a variety of general-purpose processors (e.g., central processing unit CPU and / or digital processor), a dedicated processor for performing the methods provided in any embodiment of this disclosure, or a suitable combination of general-purpose and dedicated processors.

[0106] The processing system 200 may also include one or more of the following structures: various input / output units, communication units (for wired and / or wireless communication, such as for receiving VCD data provided by the front end, accessing the cloud to obtain simulation-related databases, etc.), interface units, power supply units, bus units, etc.

[0107] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0109] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0110] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0111] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0112] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0113] Computer-readable storage media include both permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data.

[0114] A computer-readable storage medium can be a tangible device that stores instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of computer-readable storage media, in an inexhaustible manner, include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disks (DVDs), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves on which instructions are recorded), and any suitable combination of the foregoing, which may be used to store information that can be accessed by a computing device.

[0115] The computer-readable program instructions used to perform the above methods can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages) and conventional procedural programming languages. The computer-readable program instructions can be executed entirely on a computer system as a standalone software package, or partially on a first computer and partially on a second computer located remotely from the first computer. In the latter case, the remote second computer can be connected to the first computer via any type of network, including a local area network (LAN) or a wide area network (WAN).

[0116] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0117] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to effectively utilize the present invention and its modifications.

Claims

1. A method for verifying an integrated circuit, the integrated circuit comprising multiple modules, wherein, The verification method includes: For each module, module-level simulation is performed on the module based on the signal value change data corresponding to the module, so as to obtain the power consumption value of the module in multiple simulation windows respectively. Based on the power consumption value corresponding to each simulation window, key data from the signal value change data of that module are selected, such that the key data of different modules correspond to the maximum power consumption value in the module-level simulation of the respective module; and Based on the aforementioned key data, a top-level simulation of the integrated circuit is run to obtain voltage drop simulation results. These results are then compared with the approval criteria to confirm whether the verification has passed. The step of selecting key data from the signal value change data of the module based on the power consumption value corresponding to each simulation window includes: For each module, the simulation window corresponding to the maximum power consumption value among the plurality of simulation windows is determined as the key window for that module; and Based on the key window, the signal value change data corresponding to the maximum power consumption value is limited to obtain the key data segment of the module, and the key data of the module is obtained based on the key data segment.

2. The verification method according to claim 1, wherein, Each module corresponds to at least one of the signal value change data under different test cases. For each module, the step of obtaining the power consumption value corresponding to multiple simulation windows based on the signal value change data corresponding to the module includes: for each module, running the module-level simulation based on each branch of the signal value change data corresponding to the module to obtain the power consumption value corresponding to each branch of the signal value change data under the multiple simulation windows.

3. The verification method according to claim 2, wherein, The steps for running a top-level simulation of the integrated circuit based on the key data to obtain voltage drop simulation results include: For each test case of each module, the top-level simulation is run based on the key data corresponding to the signal value change data of that test case and the non-vector data of each module other than that module in the integrated circuit, to obtain the voltage drop simulation results of that module under each test case. The key window corresponding to the signal value change data of each test case is the simulation window in which the signal value change data provides the maximum power consumption value within the multiple simulation windows. The key data corresponding to the signal value change data of each test case is determined based on the key data segment of the signal value change data defined by the simulation window.

4. The verification method according to claim 2, wherein, The steps for selecting key data from the signal value change data of the module based on the power consumption value corresponding to each simulation window include: By comparing the power consumption values ​​corresponding to all the signal value changes of this module under each simulation window, the key data segment with the maximum power consumption value among the key data segments of each branch of signal value changes corresponding to this module is determined; and The key data of the module is determined based on the key data segment with the maximum power consumption value, and the key data of the module includes at least the key data segment with the maximum power consumption value.

5. The verification method according to claim 4, wherein, The steps for running a top-level simulation of the integrated circuit based on the key data to obtain voltage drop simulation results include: Determine the data foundation for the top-level simulation, the data foundation comprising combinations of the key data corresponding to the plurality of modules respectively; and The data base is loaded into the simulation environment, and the top-level simulation of the integrated circuit is run in the simulation environment to obtain the voltage drop simulation results.

6. The verification method according to claim 1, wherein, The time widths of the multiple simulation windows are consistent; and / or The time difference between any two adjacent simulation windows is consistent in chronological order.

7. The verification method according to claim 6, wherein, The time difference corresponds to the reciprocal of the maximum value of each signal frequency used by the integrated circuit.

8. The verification method according to claim 1, wherein, The plurality of modules includes: Multiple sub-modules, each with its own circuit structure for implementing a corresponding function; and Call the top-level module of the multiple submodules.

9. A processing system, wherein, include: The processor is used to execute verification tools; as well as The storage device provides the operating space and data storage space for the verification tool. The verification tool is configured to perform the verification method according to any one of claims 1 to 8.

10. A computer-readable storage medium having instructions stored thereon, wherein, The instructions are executed by one or more processing units to implement the verification method as described in any one of claims 1 to 8.

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