High-voltage interlock detection circuit, detection method, and vehicle

Abstract

The application discloses a high-voltage interlocking detection circuit, a detection method and a vehicle. The main control chip comprises a first pin end and a second pin end. An input sub-circuit is connected to the first pin end, a first power supply, a common end and one end of a high-voltage device. The first sub-circuit is configured to control the high-voltage device to be electrically conducted or electrically interrupted with the first power supply in response to a first pulse signal. An output sub-circuit is connected to the other end of the high-voltage device, the second pin end and the common end. The output sub-circuit is configured to provide a second pulse signal to the second pin end in response to the first pulse signal. The main control chip is configured to determine the state of the high-voltage device according to the comparison result of the duty cycle of the first pulse signal and the duty cycle of the second pulse signal, so as to detect whether the interlocking state of the high-voltage device is normal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of automobile safety, in particular to a high-voltage interlock detection circuit, a high-voltage interlock state detection method and a vehicle. BACKGROUND

[0002] In recent years, the number of new energy vehicles has increased rapidly, and safety is the first element of a vehicle. New energy vehicles have high-voltage devices, and normal connection of the high-voltage devices can ensure normal driving of the new energy vehicles. If the high-voltage devices are not normally connected, the vehicle will lose power and cause safety problems. The high-voltage interlock (HVIL) circuit is an important circuit for detecting vehicle safety, and the high-voltage interlock detection circuit can detect the on-off state of the high-voltage device, so as to timely prompt or warn the user to ensure the personal safety of the user. Therefore, the high-voltage interlock detection circuit is particularly important for new energy vehicles.

[0003] At present, the state of the high-voltage device is generally detected by an analog circuit detection method. A voltage signal is input to one end of the analog circuit, the amplitudes of the voltage signals at different positions of the analog circuit are detected, and the state of the high-voltage device is determined according to the amplitudes of the voltage signals. However, the analog circuit structure is relatively complex, and the state of the high-voltage device is difficult to determine because detection needs to be performed at multiple positions. SUMMARY

[0004] In view of this, the present application provides a high-voltage interlock detection circuit, a high-voltage interlock state detection method and a vehicle, which has a simple circuit structure and can accurately and reliably detect the interlock state of the high-voltage device.

[0005] In a first aspect, an embodiment of the present application provides a high-voltage interlock detection circuit, which comprises a master control chip, an input sub-circuit, an output sub-circuit, a high-voltage device, a first power supply and a common end.

[0006] The master control chip comprises a first pin end and a second pin end.

[0007] The input sub-circuit is connected to the first pin end, the first power supply, the common end and one end of the high-voltage device, respectively. The first pin end is configured to output a first pulse signal to the input sub-circuit, and the input sub-circuit is configured to control the high-voltage device to be electrically connected or electrically disconnected with the first power supply in response to the first pulse signal.

[0008] The output sub-circuit is connected to the other end of the high-voltage device, the second pin end and the common end, respectively. The output sub-circuit is configured to provide a second pulse signal to the second pin end in response to the first pulse signal.

[0009] The master control chip is configured to compare the duty cycle of the first pulse signal and the duty cycle of the second pulse signal, and determine the state of the high-voltage device according to the comparison result.

[0010] In some embodiments, the master control chip further comprises a third pin end;

[0011] The high-voltage interlock detection circuit further comprises a detection sub-circuit and a second power supply, the detection sub-circuit being connected to the third pin end, the second power supply and a first node between the other end of the high-voltage device and the output sub-circuit, wherein the third pin end is configured to provide a detection signal to the detection sub-circuit, and the detection sub-circuit is configured to control the second power supply to be electrically connected or disconnected with the output sub-circuit in response to the detection signal;

[0012] The master control chip is further configured to determine the fault type of the high-voltage device according to the change of the duty cycle of the second pulse signal.

[0013] In some embodiments, the input sub-circuit comprises a first field effect transistor, a second field effect transistor and a first resistor;

[0014] The gate of the first field effect transistor is connected to the first pin end, the first pole of the first field effect transistor is connected to the common end, and the second pole of the first field effect transistor is connected to one end of the first resistor;

[0015] The other end of the first resistor is connected to the first power supply;

[0016] The gate of the second field effect transistor is connected to a second node between the second pole of the first field effect transistor and one end of the first resistor, the first pole of the second field effect transistor is connected to the first power supply, and the second pole of the second field effect transistor is connected to one end of the high-voltage device.

[0017] In some embodiments, the input sub-circuit further comprises a second resistor and a first diode;

[0018] One end of the second resistor is connected to the second pole of the second field effect transistor, the other end of the second resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to one end of the high-voltage device.

[0019] In some embodiments, the output sub-circuit comprises a third resistor, one end of the third resistor being connected to the other end of the high-voltage device, and the other end of the third resistor being connected to the common end;

[0020] The second pin end is connected to a third node between one end of the third resistor and the other end of the high-voltage device.

[0021] In some embodiments, the detection sub-circuit comprises a third field effect transistor and a fourth resistor.

[0022] The gate of the third field effect transistor is connected to the third pin end, the first pole of the third field effect transistor is connected to the second power supply, and the second pole of the third field effect transistor is connected to the other end of the high-voltage device.

[0023] One end of the fourth resistor is connected to the third pin end, and the other end is connected to the second power supply.

[0024] In some embodiments, the detection sub-circuit further comprises a second diode.

[0025] The anode of the second diode is connected to the second pole of the third field effect transistor, and the cathode of the second diode is connected to the other end of the high-voltage device.

[0026] In a second aspect, the embodiments of the present application also provide a high-voltage interlock state detection method, which is applied to the high-voltage interlock detection circuit of the first aspect and comprises the following steps.

[0027] The master control chip outputs a first pulse signal to the input sub-circuit through the first pin end and acquires a second pulse signal provided by the output sub-circuit through the second pin end of the master control chip.

[0028] When the duty cycle of the first pulse signal is consistent with the duty cycle of the second pulse signal, the master control chip determines that the state of the high-voltage device is normal.

[0029] When the duty cycle of the first pulse signal is inconsistent with the duty cycle of the second pulse signal, the master control chip determines that the state of the high-voltage device is abnormal.

[0030] In some embodiments, the method further comprises:

[0031] When the duty cycle of the second pulse signal is 100%, the master control chip determines that the fault type of the high-voltage device is short-circuit to the first power supply.

[0032] When the duty cycle of the second pulse signal is 0%, the master control chip provides a detection signal of low level to the detection sub-circuit through the third pin end, and the detection signal of low level is configured to turn on the third field effect transistor to electrically turn on the second power supply and the output sub-circuit.

[0033] In a case that the second power supply is electrically conducted with the output sub-circuit, when the duty cycle of the second pulse signal is 100%, the master control chip determines that the fault type of the high-voltage device is open circuit;

[0034] In a case that the second power supply is electrically conducted with the output sub-circuit, when the duty cycle of the second pulse signal is 0%, the master control chip determines that the fault type of the high-voltage device is short circuit to the common terminal.

[0035] In a third aspect, the embodiments of the present application further provide a vehicle, which comprises the high-voltage interlock detection circuit according to the first aspect.

[0036] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0037] The high-voltage interlock detection circuit, the detection method and the vehicle provided by the embodiments of the present application can detect the interlock state of the high-voltage device through a relatively simple circuit. Compared with the traditional high-voltage interlock detection circuit which takes voltage or current as the output signal or detection variable, the high-voltage interlock detection circuit provided by the embodiments of the present application takes the change of the duty cycle of the pulse signal as the judgment condition to detect the high-voltage interlock state, which can avoid the interference of the unstable factors of the voltage or current signal itself on the detection result to a certain extent, so that the interlock state of the high-voltage device can be detected more accurately and reliably. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 The first circuit structure diagram of the high-voltage interlock detection circuit provided by the embodiments of the present application;

[0040] Figure 2 The second circuit structure diagram of the high-voltage interlock detection circuit provided by the embodiments of the present application;

[0041] Figure 3 The method flowchart of the detection method of the high-voltage interlock state provided by the embodiments of the present application. DETAILED DESCRIPTION

[0042] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.

[0043] Figure 1 A circuit structure schematic diagram of a high-voltage interlock detection circuit is provided in the embodiments of the present application. As shown in the figure, Figure 1 The high-voltage interlock detection circuit includes a master control chip 101, an input sub-circuit 102, an output sub-circuit 103, a high-voltage device 105, a first power supply VCC1 and a common terminal GND.

[0044] The master control chip 101 includes a first pin end P1 and a second pin end P2.

[0045] The input sub-circuit 102 is connected to the first pin end P1, the first power supply VCC1, the common terminal GND and one end of the high-voltage device 105, respectively. The first pin end P1 is configured to output a first pulse signal to the input sub-circuit 102. The input sub-circuit 102 is configured to control the high-voltage device 105 to be electrically conducted or electrically interrupted with the first power supply VCC1 in response to the first pulse signal.

[0046] The output sub-circuit 103 is connected to the other end of the high-voltage device 105, the second pin end P2 and the common terminal GND, respectively. The output sub-circuit 103 is configured to provide a second pulse signal to the second pin end P2 in response to the first pulse signal. The master control chip 101 is configured to compare the duty cycle of the first pulse signal and the duty cycle of the second pulse signal, and determine the state of the high-voltage device 105 according to the comparison result.

[0047] In other words, the high-voltage interlock detection circuit provided by the embodiment of the application is connected to the first power supply VCC1 and the common terminal GND through the input sub-circuit 102 and the output sub-circuit 103, so that the input sub-circuit 102, the high-voltage device 105 and the output sub-circuit 103 can be connected to form a closed loop. The first pulse signal provided by the first pin end P1 of the master control chip 101 to the input sub-circuit 102 can be used as a detection signal to control the electrical conduction or electrical resistance of the high-voltage device 105 and the first power supply VCC1. The electrical conduction or electrical resistance of the high-voltage device 105 and the first power supply VCC1 will affect the second pulse signal provided by the output sub-circuit 103 to the second pin end P2 of the master control chip 101. Therefore, the master control chip 101 can determine whether the high-voltage interlock state of the high-voltage device 105 is normal according to the comparison result between the duty cycle of the first pulse signal and the duty cycle of the second pulse signal. If the duty cycle of the first pulse signal is consistent with the duty cycle of the second pulse signal, it can be considered that the state of the high-voltage device 105 is normal. If the duty cycle of the first pulse signal is inconsistent with the duty cycle of the second pulse signal, it can be considered that the state of the high-voltage device 105 is abnormal.

[0048] Therefore, the high-voltage interlock detection circuit provided by the embodiment of the application has a relatively simple structure, and compared with the traditional high-voltage interlock detection circuit which uses voltage or current as an output signal or a detection variable, the high-voltage interlock detection circuit provided by the embodiment of the application uses the change of the duty cycle of the pulse signal as a judgment condition to detect the high-voltage interlock state, which can avoid the interference of the instability of the voltage or current signal itself on the detection result to a certain extent, so that the interlock state of the high-voltage device 105 can be detected more accurately and reliably.

[0049] In some embodiments, the master control chip 101 can use a TC275 chip with a Tricore core to provide the first pulse signal for the input sub-circuit 102, collect the second pulse signal provided by the output sub-circuit 103, and compare and process the first pulse signal and the second pulse signal. The high-voltage interlock detection circuit can further include a download circuit, a crystal oscillator circuit, a reset circuit and a power supply circuit, etc. to form a minimum system board together with the master control chip.

[0050] In some embodiments, the first pin end P1 can be the P00.7 pin of the TC275 chip, and the second pin end P2 can be the P00.8 pin of the TC275 chip.

[0051] In some embodiments, the first pulse signal can have a specific duty cycle, and the duty cycle is neither 0 nor 100%. In addition, the frequency of the first pulse signal can also be specific. The master chip 101 can determine whether the state of the high-voltage device 105 is normal according to the duty cycle of both the first pulse signal and the second pulse signal, or according to the duty cycle and frequency of both the first pulse signal and the second pulse signal. When the state of the high-voltage device 105 is normal, the duty cycle between the first pulse signal and the second pulse signal should be consistent, and the frequency should also be consistent.

[0052] Exemplarily, the first pulse signal is a pulse width modulation (PWM) wave with a frequency of 1 KHz and a duty cycle of 50%.

[0053] It should be noted that the PWM wave is a signal that appears between high and low levels. The frequency of the PWM refers to the number of times the pulse signal goes from high to low and back to high (one pulse period) in 1s, which is the inverse of the pulse period; the duty cycle of the PWM refers to the proportion of the output time of the high level in the entire pulse period in one pulse period. Exemplarily, the PWM wave with a frequency of 1 KHz and a duty cycle of 50% has a pulse period of 0.1 ms, and the pulse signal goes from high to low and back to high 1000 times in 1s. The proportion of the output time of the high level in the entire pulse period in one pulse period is 50%.

[0054] In some embodiments, the master chip 101 can control the GTM (Generic Timer Module) ATOM (Advanced Routing Unit-connected Timer Output Module) to make the first pin end P1 provide the first pulse signal to the input sub-circuit 102.

[0055] When detecting the state of the high-voltage device, the input sub-circuit 102, the high-voltage device 105, and the output sub-circuit 103 need to be connected in series in turn, so that the high-voltage device 105 is connected to the first power supply VCC1, as part of the high-voltage interlock detection circuit. The first power supply VCC1 can provide operating voltage for the high-voltage interlock detection circuit. In addition, the first power supply VCC1 can also provide a conduction voltage for the input sub-circuit 102. In other words, the first power supply VCC1 can cooperate with the first pulse signal to realize the conduction or disconnection of the input sub-circuit 102, so as to control the electrical conduction or electrical resistance of the high-voltage device 105 and the first power supply VCC1. In some embodiments, the first power supply VCC1 can be a direct current voltage source of 3.3-5V.

[0056] As shown in FIG. 1, the input sub-circuit 102 can include a first field effect transistor Q1, a second field effect transistor Q2, and a first resistor R1. Figure 2

[0057] The gate of the first field effect transistor Q1 is connected to the first pin end P1, the first pole of the first field effect transistor Q1 is connected to the common end GND, and the second pole of the first field effect transistor Q1 is connected to one end of the first resistor R1.

[0058] In some embodiments, the first field effect transistor Q1 can be an N-channel enhancement mode field effect transistor. When the first field effect transistor Q1 is an N-channel enhancement mode field effect transistor, the first pole of the first field effect transistor Q1 is a source, and the second pole of the first field effect transistor Q1 is a drain.

[0059] It should be noted that when the first field effect transistor Q1 is an N-channel enhancement mode field effect transistor, the first field effect transistor Q1 is turned on when the gate voltage is greater than the source voltage, that is, a positive voltage is provided to the gate. Therefore, when the first pulse signal is high, the gate of the first field effect transistor Q1 inputs a high level, and the first pole (source) of the first field effect transistor Q1 is connected to the common end GND, so that the first field effect transistor Q1 is turned on.

[0060] As shown in FIG. 1, the other end of the first resistor R1 is connected to the first power supply VCC1. The gate of the second field effect transistor Q2 is connected to the second node N2, the second node N2 is located between the second pole of the first field effect transistor Q1 and one end of the first resistor R1, the first pole of the second field effect transistor Q2 is connected to the first power supply VCC1, and the second pole of the second field effect transistor Q2 is connected to one end of the high-voltage device 105. Figure 2 The second node N2 can serve as a connection point of the first field effect transistor Q1 and the second field effect transistor Q2.

[0061] In some embodiments, the second field effect transistor Q2 can be a P-channel enhancement mode field effect transistor. When the second field effect transistor Q2 is a P-channel enhancement mode field effect transistor, the first pole of the second field effect transistor Q2 is a source, and the second pole of the second field effect transistor Q2 is a drain.

[0062]

[0063] ​​It should be noted that in the case of the second field effect transistor Q2 being a P-channel enhancement mode field effect transistor, the second field effect transistor Q2 is turned on when the gate voltage is less than the source voltage, that is, a reverse voltage is provided to the gate. Therefore, when the first pulse signal is at a high level, the first field effect transistor Q1 is turned on, and since the first pole (source) of the second field effect transistor Q2 is connected to the first power supply VCC1 and the gate of the second field effect transistor Q2 is connected to the first power supply VCC1 through the first resistor R1, the first resistor R1 can pull down the voltage at the second node N2 as a pull-up resistor, so that the gate voltage of the second field effect transistor Q2 is less than the source voltage, thereby turning on the second field effect transistor Q2.

[0064] In some embodiments, the resistance of the first resistor R1 can be 4.7KΩ.

[0065] In order to protect the circuit, as shown in Figure 2 the input sub-circuit 102 can further include a second resistor R2 and a first diode D1. One end of the second resistor R2 is connected to the second pole of the second field effect transistor Q2, and the other end of the second resistor R2 is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to one end of the high voltage device 105.

[0066] The second resistor R2 can be used as a current limiting resistor to limit the current flowing through the first diode D1 and the high voltage device 105, so as to prevent the electronic components from being burned out due to excessive current, thereby protecting the high voltage interlock detection circuit. The first diode D1 is connected between the second resistor R2 and the high voltage device 105, and since the first diode D1 has a forward conduction characteristic, connecting the cathode of the first diode D1 to one end of the high voltage device 105 can prevent the voltage of the high voltage device 105 from being reversely injected into the input sub-circuit 102, thereby protecting the high voltage interlock detection circuit.

[0067] In some embodiments, the resistance of the second resistor R2 can be 220Ω.

[0068] In the embodiments of the present application, as shown in Figure 2 the output sub-circuit 103 can include a third resistor R3, one end of the third resistor R3 being connected to the other end of the high voltage device 105, and the other end of the third resistor R3 being connected to the common end GND. The second pin end P2 of the master control chip 101 can be connected to a third node N3 between the one end of the third resistor R3 and the other end of the high voltage device 105. Therefore, the output sub-circuit 103 can output a second pulse signal to the second pin end P2 of the master control chip 101 in response to the first pulse signal, so that the master control chip 101 determines the state of the high voltage device 105 according to the comparison result of the first pulse signal and the second pulse signal.

[0069] When the first pulse signal is at high level, the first field effect transistor Q1 and the second field effect transistor Q2 are both turned on, so that the high voltage device 105 can be electrically connected with the first power supply VCC1. In the case that the high voltage device 105 is normal, the second pulse signal detected by the second pin end P2 of the master control chip 101 is also at high level. When the first pulse signal is at low level, the turn-on condition of the first field effect transistor Q1 and the second field effect transistor Q2 cannot be met, and the first field effect transistor Q1 and the second field effect transistor Q2 are both in the off state. At this time, the second field effect transistor Q2 is in the second pole (drain) open circuit state. The second pole of the second field effect transistor Q2 is connected to the common end GND through the high voltage device 105 and the third resistor R3, so that the second pin end P2 of the master control chip 101 detects low level. As can be seen from the above, in the case that the high voltage device is normal, the duty ratio and / or frequency characteristics of the first pulse signal and the second pulse signal should be the same.

[0070] In some embodiments, the resistance value of the third resistor R3 can be 20KΩ.

[0071] In response to the first pulse signal, if the second pin end P2 of the master control chip 101 detects that the second pulse signal is continuously at high level, that is, the second pulse signal is at high level regardless of whether the first pulse signal is at high level or low level, that is, the duty ratio is 100%, it indicates that the high voltage device 105 is abnormal, and the specific fault type of the high voltage device is short-circuit to the first power supply VCC1.

[0072] In response to the first pulse signal, if the second pin end P2 of the master control chip 101 detects that the second pulse signal is continuously at low level, that is, the second pulse signal is at low level regardless of whether the first pulse signal is at high level or low level, that is, the duty ratio is 0%, it indicates that the high voltage device is abnormal, and the specific fault type of the high voltage device 105 can be open circuit or short-circuit to the common end GND.

[0073] In order to further accurately determine the specific fault type of the high voltage device, referring to Figure 2 The master control chip 101 of the high voltage interlock detection circuit can further include a third pin end P3, and the third pin end P3 can be an output port of a detection signal. In some embodiments, the third pin end P3 can be a P00.9 pin of a TC275 chip.

[0074] The high voltage interlock detection circuit can further include a detection sub-circuit 104 and a second power supply VCC2, and the detection sub-circuit 104 is connected to the third pin end P3, the second power supply VCC2 and a first node N1, respectively. The first node N1 is located between the other end of the high voltage device 105 and the output sub-circuit 103.

[0075] The third pin end P3 can be configured to provide a detection signal to the detection sub-circuit 104, and the detection sub-circuit 104 is configured to control the electrical conduction or electrical resistance between the second power supply VCC2 and the output sub-circuit 103 in response to the detection signal.

[0076] In some embodiments, the second power supply VCC2 can be provided by a power supply circuit of a minimum system board, and the second power supply VCC2 can be a direct current voltage source of 3.3V or 5V.

[0077] The master control chip 101 can also be configured to determine the fault type of the high-voltage device 105 according to the duty cycle change of the second pulse signal, and specifically determine whether the fault type of the high-voltage device 105 is open circuit or short circuit to the common end GND when the duty cycle of the second pulse signal remains 0%.

[0078] In some embodiments, the master control chip 101 can control the ATOM of the GTM to provide a detection signal to the detection sub-circuit 104 through the third pin end P3.

[0079] In the embodiments of the present application, referring to Figure 2 , the detection sub-circuit 104 can include a third field effect transistor Q3 and a fourth resistor R4. The gate of the third field effect transistor Q3 is connected to the third pin end P3, the first pole of the third field effect transistor Q3 is connected to the second power supply VCC2, and the second pole of the third field effect transistor Q3 is connected to the other end of the high-voltage device 105.

[0080] One end of the fourth resistor R4 is connected to the third pin end P3, and the other end is connected to the second power supply VCC2.

[0081] In some embodiments, the third field effect transistor Q3 can be a P-channel enhancement mode field effect transistor, and when the third field effect transistor Q3 is a P-channel enhancement mode field effect transistor, the first pole of the third field effect transistor Q3 is the source, and the second pole of the third field effect transistor Q3 is the drain.

[0082] It should be noted that when the third field effect transistor Q3 is a P-channel enhancement mode field effect transistor, the third field effect transistor Q3 is turned on when the gate voltage is less than the source voltage, that is, a reverse voltage is provided to the gate. Therefore, when the detection signal is at a low level, since the first pole (source) of the third field effect transistor Q3 is connected to the second power supply VCC2, the gate of the third field effect transistor Q3 is connected to the second power supply VCC2 through the fourth resistor R4, and the fourth resistor R4 can be used as a pull-up resistor to lower the gate voltage of the third field effect transistor Q3, so that the gate voltage of the third field effect transistor Q3 is less than the source voltage, thereby turning on the third field effect transistor Q3.

[0083] In some embodiments, the resistance value of the fourth resistor R4 can be 4.7KΩ.

[0084] In some embodiments, the detection signal can be a pulse signal including low signal level and high signal level. When the second pin end P2 of the master chip 101 detects the second pulse signal as low signal level, the detection signal can be switched to low signal level, and further determination of the fault type of the high voltage device 105 is needed; when the detection signal remains as high signal level, further determination of the fault type of the high voltage device 105 is not needed.

[0085] As described above, when the detection signal is low signal level, the third field effect transistor Q3 is turned on. When the detection signal remains as high signal level, the third field effect transistor Q3 can remain in the off state, thereby bypassing the detection sub-circuit 104, and the third pin end P3 is in the initial reset state. In other words, the initial reset state of the third pin end P3 is outputting high signal level, and the action state of the third pin end P3 is outputting low signal level.

[0086] When further determination of the fault type of the high voltage device 105 is needed, the detection signal can be switched to low signal level to turn on the third field effect transistor Q3. In this case, when the high voltage device 105 is open circuit, it is equivalent to that the high voltage device 105 is not connected to the high voltage interlock detection circuit, and the sub-circuit between the second power supply VCC2, the third resistor R3 and the common end GND is connected, and the second pulse signal output by the output sub-circuit 104 is high signal level. When the high voltage device 105 is short-circuited to the power supply ground, the potentials at all places of the output sub-circuit 104 are the same as the potential of the common end GND, and the second pulse signal output by the output sub-circuit 104 is low signal level. When the detection sub-circuit 104 is working, the first pin end P1 can output the first pulse signal with a specific frequency and a specific duty cycle.

[0087] Therefore, when the detection sub-circuit 104 is working, if the duty cycle of the second pulse signal output by the output sub-circuit 103 is 100%, i.e. the second pulse signal remains as high signal level, it indicates that the specific fault type of the high voltage interlock detection circuit is that the high voltage device 105 is open circuit; if the duty cycle of the second pulse signal output by the output sub-circuit 103 is 0%, i.e. the second pulse signal remains as high signal level, it indicates that the specific fault type of the high voltage interlock detection circuit is that the high voltage device 105 is short-circuited to the power supply ground.

[0088] In some embodiments, the output sub-circuit 103 can further include a fifth resistor R5, which can be connected between the first node N1 and the third node N3, configured to limit the current of the output sub-circuit 103 and divide the voltage between the second power supply VCC2 and the ground GND, so that the voltage at the third node N3 is lower than the voltage of the second power supply VCC2. In the case of the high-voltage device 105 being broken, in order to make the output sub-circuit 103 output a high level to indicate the broken state of the high-voltage device, the resistance of the fifth resistor R5 cannot be too large to avoid excessive voltage division. In some embodiments, the resistance of the fifth resistor R5 can be 1KΩ.

[0089] In order to protect the detection sub-circuit 104, in some embodiments, the detection sub-circuit 104 can further include a second diode D2. The anode of the second diode D2 can be connected to the second electrode of the third field effect transistor Q3, and the cathode of the second diode D2 is connected to the other end of the high-voltage device 105. Since the second diode D2 has a forward conduction characteristic, the second diode D2 can prevent the voltage of the high-voltage device 105 from being reversed into the detection sub-circuit 104, thereby protecting the high-voltage interlock detection circuit.

[0090] In some embodiments, in order to protect the master control chip 101, as shown in Figure 2 The input sub-circuit 102 can further include a sixth resistor R6, which can be connected between the first pin end P1 and the gate of the first field effect transistor Q1, to limit the current and prevent excessive current from burning out the master control chip 101. In some embodiments, the resistance of the sixth resistor R6 can be 1KΩ.

[0091] Further, as shown in Figure 2 In some embodiments, the output sub-circuit 103 can further include a third diode D3 and a fourth diode D4. The anode of the third diode D3 can be connected to the ground GND, and the cathode can be connected to the second pin end P2 of the master control chip 101. The anode of the fourth diode D4 can be connected to the second pin end P2 of the master control chip 101, and the cathode can be connected to the third power supply VCC3.

[0092] In this way, the master control chip 101 is protected by the forward conduction characteristic of the diodes. The third diode D3 can prevent excessively low voltage from entering the second pin end P2 of the master control chip 101, and the fourth diode D4 can prevent excessively high voltage from entering the second pin end P2 of the master control chip 101.

[0093] It should be noted that the above embodiment takes the first field effect transistor Q1 as an N-channel enhancement field effect transistor, the second field effect transistor Q2 as a P-channel enhancement field effect transistor, and the third field effect transistor Q3 as a P-channel enhancement field effect transistor as an example for description. In other embodiments, the first field effect transistor Q1, the second field effect transistor Q2, and the third field effect transistor Q3 can also be other types of field effect transistors. For example, the first field effect transistor Q1 can be a P-channel enhancement field effect transistor, the second field effect transistor Q2 can be an N-channel enhancement field effect transistor, and the third field effect transistor Q3 can be an N-channel enhancement field effect transistor, and the connection mode of the first power supply VCC1, the second power supply VCC2, and the common terminal GND can be adjusted correspondingly, as long as the functions of the input sub-circuit 102, the output sub-circuit 103, and the detection sub-circuit 104 can be realized.

[0094] In some embodiments, the software program is integrated into the battery management system (BMS, Battery Management System) of the automobile.

[0095] In some embodiments, after the master control chip 101 determines the high-voltage interlock state of the high-voltage device 105, the state signal can be output through the CAN message data to represent the normal state and / or abnormal state of the high-voltage device 105. In some embodiments, the fault type of the high-voltage device 105 can be represented by 2 bits of data in the CAN message data segment. For example, "00" can represent that the state of the high-voltage device 105 is normal, "01" can represent that the fault type of the high-voltage device 105 is short-circuiting to the first power supply VCC1, "10" can represent that the fault type of the high-voltage device 105 is open-circuiting, and "11" can represent that the fault type of the high-voltage device 105 is short-circuiting to the common terminal GND.

[0096] In some embodiments, the software program and the high-voltage interlock detection circuit can be integrated into the battery management system (BMS, Battery Management System).

[0097] The high-voltage interlock circuit provided by the embodiment of the present application can effectively avoid the interference of the voltage or the current as the output source or the detection variable on the detection result due to the instability of the voltage or the current, so that the detection result is more accurate.

[0098] The embodiment of the application provides a high-voltage interlock state detection method, which is applied to the high-voltage interlock detection circuit provided in the above embodiment, as shown in the figure, and the method comprises the following steps. Figure 3

[0099] In step 201, the master control chip 101 outputs a first pulse signal to the input sub-circuit 102 through the first pin end P1, and acquires a second pulse signal provided by the output sub-circuit 103 through the second pin end P2 of the master control chip 101.

[0100] The first pulse signal is provided to the input sub-circuit 102 through the first pin end P1 of the master control chip 101, so that the input sub-circuit is electrically conducted or electrically interrupted, and the second pulse signal is acquired through the second pin end P2, so that the master control chip 101 compares the second pulse signal with the first pulse signal.

[0101] In step 202, when the duty cycle of the first pulse signal is consistent with the duty cycle of the second pulse signal, the master control chip 101 determines that the state of the high-voltage device 105 is normal.

[0102] When the duty cycle of the first pulse signal is consistent with the duty cycle of the second pulse signal, it indicates that the state of the high-voltage device 105 is normal, and the high-voltage interlock detection circuit is complete and does not exist fault.

[0103] In step 203, when the duty cycle of the first pulse signal is inconsistent with the duty cycle of the second pulse signal, the master control chip 101 determines that the state of the high-voltage device 105 is abnormal.

[0104] When the duty cycle of the first pulse signal is inconsistent with the duty cycle of the second pulse signal, it indicates that the state of the high-voltage device 105 is abnormal, and the high-voltage interlock detection circuit exists fault, and the fault state is indicated by the inconsistency of the duty cycle.

[0105] In some embodiments, the master control chip 101 determining that the state of the high-voltage device 105 is abnormal can include the following cases:

[0106] When the duty cycle of the second pulse signal is 100%, the master control chip 101 determines that the fault type of the high-voltage device 105 is short-circuit to the first power supply VCC1.

[0107] When the duty cycle of the second pulse signal is 100%, that is, the second pulse signal is continuously high, it is determined that the high-voltage device 105 is short-circuited to the first power supply VCC1.

[0108] ​When the duty cycle of the second pulse signal is 0%, the specific fault type of the high-voltage device 105 can be open circuit or short circuit to the common terminal GND. In this case, the master control chip 101 can provide a low-level detection signal to the detection sub-circuit 104 through the third pin end P3. The low-level detection signal is configured to turn on the third field effect transistor Q3 to electrically connect the second power supply VCC2 and the output sub-circuit 103.

[0109] When the master control chip 101 provides a low-level detection signal to the detection sub-circuit 104 through the third pin end P1, the third field effect transistor Q3 is turned on to electrically connect the second power supply VCC2 and the output sub-circuit 103, so as to output the second pulse signal.

[0110] When the second power supply VCC2 is electrically connected to the output sub-circuit 103, and the duty cycle of the second pulse signal is 100%, the master control chip 101 determines that the fault type of the high-voltage device 105 is open circuit.

[0111] When the second power supply VCC2 is electrically connected to the output sub-circuit 103, and the duty cycle of the second pulse signal is 0%, the master control chip 101 determines that the fault type of the high-voltage device 105 is short circuit to the common terminal GND.

[0112] In some embodiments, the method can further include that when the master control chip 101 outputs the first pulse signal to the input sub-circuit 102 through the first pin end P1, the master control chip 101 provides a high-level detection signal to the detection sub-circuit 104 through the third pin end P3.

[0113] The high-voltage interlock state detection method provided by the embodiments of the present application can determine whether the state of the high-voltage device 105 is normal by comparing the duty cycles of the first pulse signal and the second pulse signal, and can further determine the fault type of the high-voltage device 105 according to the duty cycle of the second pulse signal by outputting the detection signal and collecting the second pulse signal.

[0114] The embodiments of the present application also provide a vehicle, which can include the high-voltage interlock detection circuit provided by the above embodiments, and / or can perform the high-voltage interlock state detection method as described above.

[0115] In the vehicle provided by the embodiment of the application, the first input sub-circuit 102 is provided with a first pulse signal through the first pin end P1 of the master control chip 101, and the input sub-circuit 102 controls the high-voltage device 105 to be electrically connected or electrically disconnected with the first power supply VCC1 in response to the first pulse signal; the input sub-circuit 102, the high-voltage device 105 and the output sub-circuit 103 are connected in sequence, and the output sub-circuit 103 provides a second pulse signal to the second pin end P2 of the master control chip 101 in response to the first pulse signal; the master control chip 101 compares the duty cycles of the first pulse signal and the second pulse signal, and then determines the state of the high-voltage device 105 of the vehicle, so as to detect whether the interlocking state of the high-voltage device in the vehicle is normal.

[0116] In the present application, the terms "first" and "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance. The term "a plurality of" means two or more than two, unless otherwise explicitly limited.

[0117] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples given are intended as illustrative only and not limiting of the present application. The scope of the application is to be limited only by the appended claims.

[0118] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is to be limited only by the appended claims.

Claims

1. A high-voltage interlock detection circuit, characterized in that, The high-voltage interlock detection circuit includes: a main control chip (101), an input sub-circuit (102), an output sub-circuit (103), a high-voltage device (105), a first power supply (VCC1), and a common terminal (GND). The main control chip (101) includes a first pin terminal (P1) and a second pin terminal (P2); The input sub-circuit (102) is connected to the first pin terminal (P1), the first power supply (VCC1), the common terminal (GND), and one end of the high-voltage device (105), respectively. The first pin terminal (P1) is configured to output a first pulse signal to the input sub-circuit (102), and the input sub-circuit (102) is configured to control the high-voltage device (105) to be electrically connected or electrically disconnected from the first power supply (VCC1) in response to the first pulse signal. The output sub-circuit (103) is connected to the other end of the high voltage device (105), the second pin (P2) and the common terminal (GND), respectively. The output sub-circuit (103) is configured to provide a second pulse signal to the second pin (P2) in response to the first pulse signal. The main control chip (101) is configured to compare the duty cycle of the first pulse signal and the duty cycle of the second pulse signal, and determine the state of the high voltage device (105) based on the comparison result. The main control chip (101) also includes a third pin (P3). The high-voltage interlock detection circuit further includes a detection sub-circuit (104) and a second power supply (VCC2). The detection sub-circuit (104) is connected to the third pin terminal (P3), the second power supply (VCC2), and the first node (N1), respectively. The first node (N1) is located between the other end of the high-voltage device (105) and the output sub-circuit (103). The third pin terminal (P3) is configured to provide a detection signal to the detection sub-circuit (104). The detection sub-circuit (104) is configured to control the second power supply (VCC2) and the output sub-circuit (103) to be electrically connected or resistively disconnected in response to the detection signal. The main control chip (101) is also configured to determine the fault type of the high-voltage device (105) based on the duty cycle change of the second pulse signal.

2. The high-voltage interlock detection circuit according to claim 1, characterized in that, The input sub-circuit (102) includes a first field-effect transistor (Q1), a second field-effect transistor (Q2), and a first resistor (R1). The gate of the first field-effect transistor (Q1) is connected to the first pin (P1), the first terminal of the first field-effect transistor (Q1) is connected to the common terminal (GND), and the second terminal of the first field-effect transistor (Q1) is connected to one end of the first resistor (R1). The other end of the first resistor (R1) is connected to the first power supply (VCC1). The gate of the second field-effect transistor (Q2) is connected to the second node (N2), which is located between the second terminal of the first field-effect transistor (Q1) and one end of the first resistor (R1). The first terminal of the second field-effect transistor (Q2) is connected to the first power supply (VCC1), and the second terminal of the second field-effect transistor (Q2) is connected to one end of the high-voltage device (105).

3. The high-voltage interlock detection circuit according to claim 2, characterized in that, The input sub-circuit (102) also includes a second resistor (R2) and a first diode (D1); One end of the second resistor (R2) is connected to the second terminal of the second field-effect transistor (Q2), and the other end of the second resistor (R2) is connected to the positive terminal of the first diode (D1). The negative terminal of the first diode (D1) is connected to one end of the high-voltage device (105).

4. The high-voltage interlock detection circuit according to claim 1, characterized in that, The output sub-circuit (103) includes a third resistor (R3), one end of which is connected to the other end of the high-voltage device (105), and the other end of which is connected to the common terminal (GND). The second pin (P2) is connected to the third node (N3) between one end of the third resistor (R3) and the other end of the high voltage device (105).

5. The high-voltage interlock detection circuit according to claim 1, characterized in that, The detection sub-circuit (104) includes a third field-effect transistor (Q3) and a fourth resistor (R4). The gate of the third field-effect transistor (Q3) is connected to the third pin (P3), the first terminal of the third field-effect transistor (Q3) is connected to the second power supply (VCC2), and the second terminal of the third field-effect transistor (Q3) is connected to the other end of the high-voltage device (105). One end of the fourth resistor (R4) is connected to the third pin (P3), and the other end is connected to the second power supply (VCC2).

6. The high-voltage interlock detection circuit according to claim 5, characterized in that, The detection sub-circuit (104) also includes a second diode (D2); The positive terminal of the second diode (D2) is connected to the second terminal of the third field-effect transistor (Q3), and the negative terminal of the second diode (D2) is connected to the other end of the high-voltage device (105).

7. A method for detecting high-voltage interlock status, characterized in that, Applied to the high-voltage interlock detection circuit as described in any one of claims 1-6, the method includes: The main control chip (101) outputs a first pulse signal to the input sub-circuit (102) through the first pin terminal (P1), and obtains the second pulse signal provided by the output sub-circuit (103) through the second pin terminal (P2) of the main control chip (101); When the duty cycle of the first pulse signal and the duty cycle of the second pulse signal are the same, the main control chip (101) determines that the high voltage device (105) is in normal condition; When the duty cycle of the first pulse signal and the duty cycle of the second pulse signal are inconsistent, the main control chip (101) determines that the state of the high voltage device (105) is abnormal.

8. The method for detecting high-voltage interlock status according to claim 7, characterized in that, The method further includes: When the duty cycle of the second pulse signal is 100%, the main control chip (101) determines that the fault type of the high voltage device (105) is a short circuit to the first power supply (VCC1). When the duty cycle of the second pulse signal is 0%, the main control chip (101) provides a low-level detection signal to the detection sub-circuit (104) through the third pin (P3). The low-level detection signal is configured to turn on the third field-effect transistor (Q3) to electrically connect the second power supply (VCC2) to the output sub-circuit (103). When the second power supply (VCC2) and the output sub-circuit (103) are electrically connected, when the duty cycle of the second pulse signal is 100%, the main control chip (101) determines that the fault type of the high voltage device (105) is an open circuit. When the second power supply (VCC2) and the output sub-circuit (103) are electrically connected, when the duty cycle of the second pulse signal is 0%, the main control chip (101) determines that the fault type of the high voltage device (105) is a short circuit to the common terminal (GND).

9. A vehicle, characterized in that, The vehicle includes a high-voltage interlock detection circuit as described in any one of claims 1-6.

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