An LDO circuit and an LDO chip

Abstract

The present invention provides an LDO circuit and an LDO chip. The circuit includes an LDO circuit module and a current limiting circuit module, and the LDO circuit module is connected in parallel with the current limiting circuit module. The current limiting circuit module includes a first current limiting unit, a power consumption reduction unit, a second current limiting unit, and a working current unit. One end of the first current limiting unit is connected to the LDO circuit module, and one end of the second current limiting unit is connected to the LDO circuit module. The first end of the power consumption reduction unit is connected to the other end of the first current limiting unit, the second end of the power consumption reduction unit is connected to the other end of the second current limiting unit, the third end of the power consumption reduction unit is grounded, and the working current unit is connected to the working current Iout. The first current limiting unit includes a first MOS transistor, the second current limiting unit includes a second MOS transistor, the working current unit includes a third MOS transistor, and the first MOS transistor is respectively connected to the second MOS transistor and the third MOS transistor. The LDO circuit of the present application has a current limiting protection function and reduced power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to an LDO circuit and an LDO chip. Background Art

[0002] An LDO (low dropout regulator), that is, a low dropout linear regulator, is a common power management chip. Because of its characteristics such as low static power consumption, low cost, and no output ripple, it has a wide range of applications in portable and communication devices. However, when the output of the LDO is short-circuited or the load current is too large, the LDO may be damaged. Especially in the case of a short circuit, there is too much current passing through the adjustment tube in the LDO, which will burn out the adjustment tube and cause the chip to stop working, affecting the normal use of the LDO. Therefore, a current limiting circuit is usually set for the LDO to ensure its normal use; moreover, when the traditional LDO circuit works, if the current on the load resistor Rout1 is large, the current flowing through the current limiting circuit is also very large, resulting in a large power consumption of the current limiting circuit and a high working cost of the LDO circuit. Summary of the Invention

[0003] To solve the above technical problems, the present invention provides an LDO circuit and an LDO chip, which protect the LDO circuit and have low power consumption by setting a power consumption reduction unit in the LDO current limiting circuit.

[0004] In a first aspect, an embodiment of the present application provides an LDO circuit, including:

[0005] an LDO circuit module and a current limiting circuit module, the LDO circuit module is connected in parallel with the current limiting circuit module, and the current limiting circuit module includes: a first current limiting unit, a power consumption reduction unit, a second current limiting unit, and a working current unit;

[0006] One end of the first current limiting unit is connected to the LDO circuit module, one end of the second current limiting unit is connected to the LDO circuit module, the first end of the power consumption reduction unit is connected to the other end of the first current limiting unit, the second end of the power consumption reduction unit is connected to the other end of the second current limiting unit, the third end of the power consumption reduction unit is grounded, the working current unit is connected to the working current, the first current limiting unit includes a first MOS transistor, the second current limiting unit includes a second MOS transistor, the working current unit includes a third MOS transistor, and the first MOS transistor is respectively connected to the second MOS transistor and the third MOS transistor;

[0007] The working current unit is configured to receive the working current and transmit the working current to the second MOS transistor and the first MOS transistor through the third MOS transistor to activate the second current limiting unit and the first current limiting unit;

[0008] The first current limiting unit and the second current limiting unit are used to receive the output current of the LDO circuit module;

[0009] The power consumption reduction unit is used to transmit the output current received by the first current limiting unit and the second current limiting unit.

[0010] In one implementation, the operating current unit further includes: a third PMOS transistor, the source of the third PMOS transistor is connected to the operating current, the drain of the third PMOS transistor is connected to the third MOS transistor, and the gate of the third PMOS transistor is connected to an operating level.

[0011] In one implementation, the second current limiting unit further includes: a second PMOS transistor and a seventh PMOS transistor, the source of the second PMOS transistor is connected to the operating voltage, the gate of the second PMOS transistor is connected to the LDO circuit module, the drain of the second PMOS transistor is connected to the seventh PMOS transistor, and the drain of the seventh PMOS transistor is connected to the second MOS transistor.

[0012] In one implementation, the power consumption reduction unit includes a sixth PMOS transistor and a fifth NMOS transistor, the source of the sixth PMOS transistor is connected to the second current limiting unit, the gate of the sixth PMOS transistor is connected to the first current limiting unit, the drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain and the gate of the fifth NMOS transistor are connected, and the source of the fifth NMOS transistor is grounded.

[0013] In one implementation, the first current limiting unit further includes a fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the LDO circuit module, the gate of the fifth PMOS transistor is connected to the second current limiting unit, and the drain of the fifth PMOS transistor is respectively connected to the first MOS transistor and the power consumption reduction unit.

[0014] In one implementation, the current limiting circuit module further includes an accuracy control module, and the accuracy control module includes: an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, and a sixth NMOS transistor;

[0015] The source electrodes of the eighth PMOS transistor and the ninth PMOS transistor are respectively connected to the power supply voltage. The gate electrode of the eighth PMOS transistor is connected to the gate electrode of the ninth PMOS transistor. The gate electrode of the ninth PMOS transistor is connected to its drain electrode. The drain electrode of the ninth PMOS transistor is connected to the drain electrode of the fourth NMOS transistor. The drain electrode of the eighth PMOS transistor is connected to the drain electrode of the sixth NMOS transistor. The gate electrode of the sixth NMOS transistor is connected to the gate electrode of the fifth NMOS transistor. The gate electrode of the fourth NMOS transistor is connected to the gate electrode of the first NMOS transistor. The source electrodes of the fourth NMOS transistor, the sixth NMOS transistor, and the third NMOS transistor are grounded.

[0016] In one implementation, the LDO circuit module includes an operational amplifier, a power transistor, and a feedback unit. The output terminal of the operational amplifier is connected to the power transistor and the second current limiting unit. The first input terminal of the operational amplifier is connected to the feedback unit. The output terminal of the power transistor is respectively connected to the feedback unit and the first current limiting unit.

[0017] In one implementation, the feedback unit includes a first feedback resistor and a second feedback resistor. The inverting input terminal of the operational amplifier inputs the power supply voltage. The output terminal of the operational amplifier is connected to the gate electrode of the power transistor and the second current limiting unit. The source electrode of the power transistor is connected to the power supply voltage. The drain electrode of the power transistor is connected to the non-inverting input terminal of the operational amplifier through the first feedback resistor. One end of the second feedback resistor is connected to the first feedback resistor and the non-inverting input terminal of the operational amplifier, and the other end of the second feedback resistor is grounded.

[0018] In one implementation, the current limiting circuit module further includes a fourth PMOS transistor. The source electrode of the fourth PMOS transistor is connected to the power supply voltage. The drain electrode of the fourth PMOS transistor is connected to the output terminal of the operational amplifier and the gate electrode of the power transistor.

[0019] In a second aspect, an LDO chip provided by an embodiment of the present application includes the LDO circuit provided in the first aspect.

[0020] The embodiments of the present invention have the following advantages:

[0021] The LDO circuit and LDO chip provided by this application. The LDO circuit includes an LDO circuit module and a current limiting circuit module. When the load current of the LDO circuit module is too large, current limiting protection for the LDO circuit module can be achieved through the current limiting circuit module. Additionally, the current limiting circuit module includes a first current limiting unit, a power consumption reduction unit, a second current limiting unit, and a working current unit. Among them, the output current of the LDO circuit module originally needed to flow through the first current limiting unit and the second current limiting unit. After setting the working current unit to provide a working circuit for the current limiting circuit module, the output current only needs to flow through the power consumption reduction unit, thereby reducing the power consumption of the current limiting circuit module and thus reducing the power consumption of the entire LDO circuit.

[0022] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and detailed descriptions are made in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a frame structure diagram of an LDO circuit provided by an embodiment of this application;

[0025] Figure 2 It is a structure diagram of an LDO circuit provided by an embodiment of this application.

[0026] MAIN ELEMENT SYMBOL DESCRIPTION:

[0027] 10 - LDO circuit module; 20 - current limiting circuit module; 21 - first current limiting unit; 22 - power consumption reduction unit; 23 - second current limiting unit; 24 - working current unit; 25 - precision control module; R1 - first feedback resistor; R2 - second feedback resistor; Rout - load resistor; MP1 - power transistor; MP2 - second PMOS transistor; MP3 - third PMOS transistor; MP4 - fourth PMOS transistor; MP5 - fifth PMOS transistor; MP6 - sixth PMOS transistor; MP7 - seventh PMOS transistor; MP8 - eighth PMOS transistor; MP9 - ninth PMOS transistor; MN1 - first NMOS transistor; MN2 - second NMOS transistor; MN3 - third NMOS transistor; MN4 - fourth NMOS transistor; MN5 - fifth NMOS transistor; MN6 - sixth NMOS transistor; Vref - power supply voltage; V1 - first voltage; V2 - second voltage; V3 - third voltage; Vout - output voltage; Iout1 - output current; Iout - working current. Detailed implementation manners

[0028] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0029] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. On the contrary, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0030] In the present invention, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected", "fixed" and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this template are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0033] Embodiment 1

[0034] This embodiment provides an LDO circuit. Specifically, refer to Figure 1 , the LDO circuit includes: an LDO circuit module 10 and a current limiting circuit module 20, and the LDO circuit module 10 is connected in parallel with the current limiting circuit module 20.

[0035] The current limiting circuit module 20 includes: a first current limiting unit 21, a power consumption reduction unit 22, a second current limiting unit 23, and a working current unit 24. One end of the first current limiting unit 21 is connected to the LDO circuit module 10, one end of the second current limiting unit 23 is connected to the LDO circuit module 10, the first end of the power consumption reduction unit 22 is connected to the other end of the first current limiting unit 21, the second end of the power consumption reduction unit 22 is connected to the other end of the second current limiting unit 23, the third end of the power consumption reduction unit 22 is grounded, the working current unit 24 is connected to the working current Iout, the first current limiting unit 21 includes a first MOS transistor MN1, the second current limiting unit 23 includes a second MOS transistor MN2, the working current unit 24 includes a third MOS transistor MN3, and the first MOS transistor MN1 is respectively connected to the second MOS transistor MN2 and the third MOS transistor MN3;

[0036] The working current unit 24 is configured to receive the working current Iout and transmit the working current Iout to the second MOS transistor MN2 and the first MOS transistor MN1 through the third MOS transistor MN3 to activate the second current limiting unit 23 and the first current limiting unit 21;

[0037] The first current limiting unit 21 and the second current limiting unit 23 are configured to receive the output current of the LDO circuit module 10;

[0038] The power consumption reduction unit 22 is configured to transmit the output current received by the first current limiting unit 21 and the second current limiting unit 23.

[0039] Specifically, the first MOS transistor MN1, the second MOS transistor MN2, and the third MOS transistor MN3 are all NMOS transistors, and the working current Iout can be set to a small current. Since the first current limiting unit 21, the second current limiting unit 23, and the working current unit 24 are all activated by the working current Iout, the currents on the first current limiting unit 21, the second current limiting unit 23, and the working current unit 24 will not be greater than the working current Iout. The output current Iout1 of the LDO circuit module 10 is generally relatively large. If it directly flows through the first current limiting unit 21 and the second current limiting unit 23, it will cause a relatively large power consumption of the current limiting circuit.

[0040] Therefore, the present application additionally provides a power consumption reduction unit 22 and a working current unit 24 to reduce the power consumption of the current limiting circuit. Since the first current limiting unit 21 and the second current limiting unit 23 are activated by the working current Iout of the working current unit 24, and the working current Iout is much smaller than the output current Iout1 of the LDO circuit module 10, and because the current in the same branch must be equal, after the first current limiting unit 21 and the second current limiting unit 23 receive the output current of the LDO circuit module 10, the output current will be transmitted through the power consumption reduction unit 22 connected to the first current limiting unit 21 and the second current limiting unit 23, so that the output current is concentrated on the path of the power consumption reduction unit 22 and will not be distributed to the first current limiting unit 21 and the second current limiting unit 23. The output current that originally passed through the two paths of the first current limiting unit 21 and the second current limiting unit 23 now only passes through the path of the power consumption reduction unit 22, thereby reducing the power consumption of the current limiting circuit module 20 and then reducing the power consumption of the entire LDO circuit.

[0041] In an embodiment, referring to Figure 2 , the LDO circuit module includes an operational amplifier EA, a power transistor MP1, and a feedback unit. The output terminal of the operational amplifier EA is connected to the power transistor MP1 and the second current limiting unit 23. The first input terminal of the operational amplifier EA is connected to the feedback unit. The output terminal of the power transistor MP1 is connected to the feedback unit and the first current limiting unit 21, and is connected to the load resistor Rout.

[0042] Specifically, the feedback unit includes a first feedback resistor R1 and a second feedback resistor R2. The inverting input terminal of the operational amplifier EA is connected to the power supply voltage Vref. The output terminal of the operational amplifier EA is respectively connected to the gate of the power transistor MP1 and the second current limiting unit 23. The source of the power transistor MP1 is connected to the power supply voltage. The drain of the power transistor MP1 is connected to the inverting input terminal of the operational amplifier EA through the first feedback resistor R1. The drain of the power transistor MP1 is also connected to one end of the load resistor Rout. The other end of the load resistor Rout is grounded. One end of the second feedback resistor R2 is connected to the first feedback resistor R1 and the inverting input terminal of the operational amplifier EA, and the other end of the second feedback resistor R2 is grounded.

[0043] The load resistor Rout is the load connected to the LDO circuit. When the current on the load resistor is too large, a current limiting circuit is required to limit the current.

[0044] In one embodiment, referring to Figure 2 , the first current limiting unit 21 further includes: a fifth PMOS transistor MP5, the power consumption reduction unit 22 includes: a sixth PMOS transistor MP6 and a fifth NMOS transistor MN5; the second current limiting unit 23 further includes: a second PMOS transistor MP2 and a seventh PMOS transistor MP7, and the working current unit 24 further includes: a third PMOS transistor MP3.

[0045] Specifically, the gate of the power transistor MP1 is connected to the gate of the second PMOS transistor MP2. The drain of the second PMOS transistor is respectively connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor. The drain of the power transistor MP1 is connected to the source of the fifth PMOS transistor MP5. The gate of the fifth PMOS transistor MP5 is connected to the gate of the seventh PMOS transistor MP7. The gate and the drain of the seventh PMOS transistor MP7 are connected. The drain of the fifth PMOS transistor MP5 is respectively connected to the gate of the sixth PMOS transistor MP6 and the drain of the first NMOS transistor MN1. The drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth NMOS transistor MN5. The drain and the gate of the fifth NMOS transistor are connected. The source of the fifth NMOS transistor MN5 is grounded.

[0046] The gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 is connected to the gate of the third NMOS transistor MN3. The source of the third PMOS transistor MP3 is connected to the working current Iout. The gate of the third PMOS transistor MP3 is connected to the working level EN. The drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3. The drain and the gate of the third NMOS transistor MN3 are connected. The sources of the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 are all grounded.

[0047] The first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 form a current mirror, and the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 form another current mirror. In a specific embodiment, the ratio of the width-to-length ratio of the first NMOS transistor MN1 to the width-to-length ratio of the second NMOS transistor MN2 can be set to 1:1, and the ratio of the width-to-length ratio of the fifth PMOS transistor MP5 to the width-to-length ratio of the seventh PMOS transistor MP7 is set to 1:1.

[0048] According to the principle of the current mirror, when the ratio of the width-to-length ratio of the first NMOS transistor MN1 to the width-to-length ratio of the second NMOS transistor MN2 is 1:1, and the ratio of the width-to-length ratio of the fifth PMOS transistor MP5 to the width-to-length ratio of the seventh PMOS transistor MP7 is 1:1, the currents flowing through the fifth PMOS transistor MP5, the first NMOS transistor MN1, the seventh PMOS transistor MP7, and the second NMOS transistor MN2 are the same. The magnitude of the current is determined by the magnitude of the working current Iout, the width-to-length ratios of the third NMOS transistor MN3, the second NMOS transistor MN2, and the first NMOS transistor MN1. Then, the value of the output voltage Vout is equal to the value of the second voltage V2. Then, the gate, source, and drain voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 are all equal, and the difference in their currents only changes with their different width-to-length ratios. When the ratio of the width-to-length ratio of the first PMOS transistor MP1 to the width-to-length ratio of the second PMOS transistor MP2 is m:1, the ratio of the output current Iout1 to the current flowing through the sixth PMOS transistor MP6 is m:1, that is, the current flowing through the sixth PMOS transistor MP6 is Iout1 / m.

[0049] Therefore, the current that originally flowed through the first current limiting unit and the second current limiting unit now only flows through the sixth PMOS transistor MP6, and the current decreases, resulting in lower power consumption.

[0050] In an embodiment, the current limiting circuit module further includes a fourth PMOS transistor MP4. The source of the fourth PMOS transistor MP4 is connected to the power supply voltage, and the drain of the fourth PMOS transistor MP4 is respectively connected to the output terminal of the operational amplifier EA and the gate of the power transistor MP1. When the first voltage V1 drops to the threshold, the fourth PMOS transistor MP4 conducts, causing the third voltage V3 to increase and the output voltage Vout to decrease, and the output current of the LDO decreases, that is, the LDO is current-limited.

[0051] In an embodiment, referring to Figure 2 , the current limiting circuit further includes an accuracy control module 25, and the accuracy control module 25 includes: an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a fourth NMOS transistor MN4, and a sixth NMOS transistor MN6;

[0052] The source electrodes of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are respectively connected to the power supply voltage. The gate electrode of the eighth PMOS transistor MP8 is connected to the gate electrode of the ninth PMOS transistor MP9. The gate electrode of the ninth PMOS transistor MP9 is connected to its drain electrode. The drain electrode of the ninth PMOS transistor MP9 is connected to the drain electrode of the fourth NMOS transistor MN4. The drain electrode of the eighth PMOS transistor MP8 is connected to the drain electrode of the sixth NMOS transistor MN6. The gate electrode of the sixth NMOS transistor MN6 is connected to the gate electrode of the fifth NMOS transistor MN5. The gate electrode of the fourth NMOS transistor MN4 is connected to the gate electrode of the first NMOS transistor MN1. The source electrodes of the fourth NMOS transistor MN4, the sixth NMOS transistor MN6, and the third NMOS transistor MN3 are all grounded.

[0053] Specifically, the width-to-length ratio of the fifth NMOS transistor MN5 and the width-to-length ratio of the sixth NMOS transistor MN6 can be set to 1:1, and the ratio of the width-to-length ratios of the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 is set to 1:1:1.

[0054] The output current Iout1 = Vout / Rout. When the ratio of the width-to-length ratio of the fifth NMOS transistor MN5 to the width-to-length ratio of the sixth NMOS transistor MN6 is k:1, and the ratio of the width-to-length ratio of the third NMOS transistor MN3 to the width-to-length ratios of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 is 1:1:1, the fourth NMOS transistor MN4, the third NMOS transistor MN3, the second NMOS transistor MN2, and the first NMOS transistor MN1 form a current mirror structure with the width-to-length ratios set to 1:1:1:1. Therefore, the current of the fourth NMOS transistor MN4 is the same as that of the third NMOS transistor, both being the working current Iout. Since the ninth PMOS transistor and the fourth NMOS transistor are in the same branch, the current on the ninth PMOS transistor MP9 is also Iout. Also, because the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 form a current mirror, and the ratio of the width-to-length ratio of the eighth PMOS transistor MP8 to the width-to-length ratio of the ninth PMOS transistor MP9 is 1:1, the current flowing through MP8 is also the working current Iout.

[0055] The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 also form a current mirror. Since the fifth NMOS transistor MN5 and the sixth PMOS transistor MP6 are in the same branch, the current of the fifth NMOS transistor MN5 is also Iout1 / m. Therefore, the current I6 flowing through the sixth NMOS transistor MN6 is Iout1 / m / k. Since the eighth PMOS transistor MP8 and the sixth NMOS transistor MN6 are in the same branch and the current values flowing through them are equal, when the current of the sixth NMOS transistor MN6 is greater than the current of the eighth PMOS transistor MP8, in order to ensure that the currents in the same branch are equal, the voltage of the first voltage V1 decreases. When the voltage of the first voltage V1 decreases to the threshold value, the fourth PMOS transistor MP4 conducts, causing the voltage of the third voltage V3 to increase and the output voltage Vout to decrease, so that the output current Iout1 of the LDO circuit module decreases, that is, the LDO is current-limited. The current-limiting value I = m * k * Iout can be obtained, where Iout is the value of the given working current Iout reference. Compared with the traditional current-limiting circuit, its current-limiting accuracy is higher.

[0056] In an embodiment, when the level EN is high, the third PMOS transistor MP3 is non-conductive, that is, the current-limiting circuit module is disconnected from the LDO circuit module. When the level EN is low, the third PMOS transistor automatically conducts and automatically disconnects when the level EN is high, which will not affect the normal operation of the LDO circuit and is more convenient to use.

[0057] Embodiment 2

[0058] The embodiment of the present application also provides an LDO chip, including the LDO circuit provided in any embodiment of the first aspect.

[0059] The LDO chip provided in this embodiment can achieve the same functions as the LDO circuit provided in Embodiment 1. To avoid repetition, the present application will not elaborate here.

[0060] In all the examples shown and described here, any specific value should be interpreted as merely exemplary, not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.

[0061] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0062] The above-described embodiments only represent several embodiments of the present invention. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention.

Claims

1. An LDO circuit, characterized in that, Including: An LDO circuit module and a current limiting circuit module. The LDO circuit module is connected in parallel with the current limiting circuit module. The current limiting circuit module includes: a first current limiting unit, a power consumption reduction unit, a second current limiting unit, and a working current unit; One end of the first current limiting unit is connected to the LDO circuit module, one end of the second current limiting unit is connected to the LDO circuit module, the first end of the power consumption reduction unit is connected to the other end of the first current limiting unit, the second end of the power consumption reduction unit is connected to the other end of the second current limiting unit, the third end of the power consumption reduction unit is grounded, the working current unit is connected to the working current, the first current limiting unit includes a first MOS transistor, the second current limiting unit includes a second MOS transistor, the working current unit includes a third MOS transistor, and the first MOS transistor is respectively connected to the second MOS transistor and the third MOS transistor; The working current unit is configured to receive the working current and transmit the working current to the second MOS transistor and the first MOS transistor through the third MOS transistor to activate the second current limiting unit and the first current limiting unit; The first current limiting unit and the second current limiting unit are configured to receive the output current of the LDO circuit module; The power consumption reduction unit is configured to transmit the output current received by the first current limiting unit and the second current limiting unit.

2. The LDO circuit according to claim 1, wherein The working current unit further includes: a third PMOS transistor. The source of the third PMOS transistor is connected to the working current, the drain of the third PMOS transistor is connected to the third MOS transistor, and the gate of the third PMOS transistor is connected to the working level.

3. The LDO circuit according to claim 1, wherein The second current limiting unit further includes: a second PMOS transistor and a seventh PMOS transistor. The source of the second PMOS transistor is connected to the working voltage, the gate of the second PMOS transistor is connected to the LDO circuit module, the drain of the second PMOS transistor is connected to the seventh PMOS transistor, and the drain of the seventh PMOS transistor is connected to the second MOS transistor.

4. The LDO circuit according to claim 1, wherein The power consumption reduction unit includes a sixth PMOS transistor and a fifth NMOS transistor. The source of the sixth PMOS transistor is connected to the second current limiting unit, the gate of the sixth PMOS transistor is connected to the first current limiting unit, the drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain and the gate of the fifth NMOS transistor are connected, and the source of the fifth NMOS transistor is grounded.

5. The LDO circuit according to claim 1, wherein The first current limiting unit further includes a fifth PMOS transistor. The source of the fifth PMOS transistor is connected to the LDO circuit module, the gate of the fifth PMOS transistor is connected to the second current limiting unit, and the drain of the fifth PMOS transistor is respectively connected to the first MOS transistor and the power consumption reduction unit.

6. The LDO circuit according to claim 4, wherein The current limiting circuit module further includes an accuracy control module. The accuracy control module includes: an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, and a sixth NMOS transistor; The source electrodes of the eighth PMOS transistor and the ninth PMOS transistor are respectively connected to the power supply voltage. The gate electrode of the eighth PMOS transistor is connected to the gate electrode of the ninth PMOS transistor. The gate electrode of the ninth PMOS transistor is connected to its drain electrode. The drain electrode of the ninth PMOS transistor is connected to the drain electrode of the fourth NMOS transistor. The drain electrode of the eighth PMOS transistor is connected to the drain electrode of the sixth NMOS transistor. The gate electrode of the sixth NMOS transistor is connected to the gate electrode of the fifth NMOS transistor. The gate electrode of the fourth NMOS transistor is connected to the gate electrode of the first NMOS transistor. The source electrodes of the fourth NMOS transistor, the sixth NMOS transistor and the third NMOS transistor are grounded.

7. The LDO circuit according to claim 1, characterized in that, The LDO circuit module includes an operational amplifier, a power transistor and a feedback unit. The output terminal of the operational amplifier is connected to the power transistor and the second current limiting unit. The first input terminal of the operational amplifier is connected to the feedback unit. The output terminal of the power transistor is respectively connected to the feedback unit and the first current limiting unit.

8. The LDO circuit according to claim 7, characterized in that, The feedback unit includes a first feedback resistor and a second feedback resistor. The inverting input terminal of the operational amplifier inputs the power supply voltage. The output terminal of the operational amplifier is connected to the gate electrode of the power transistor and the second current limiting unit. The source electrode of the power transistor is connected to the power supply voltage. The drain electrode of the power transistor is connected to the non-inverting input terminal of the operational amplifier through the first feedback resistor. One end of the second feedback resistor is connected to the first feedback resistor and the non-inverting input terminal of the operational amplifier, and the other end of the second feedback resistor is grounded.

9. The LDO circuit according to claim 8, wherein The current limiting circuit module further includes a fourth PMOS transistor. The source electrode of the fourth PMOS transistor is connected to the power supply voltage. The drain electrode of the fourth PMOS transistor is connected to the output terminal of the operational amplifier and the gate electrode of the power transistor.

10. An LDO chip, characterized in that, The LDO chip includes the LDO circuit according to any one of claims 1-9.

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