Fault Control Method, Device, Equipment and Storage Medium

Abstract

An embodiment of the present invention provides a fault control method, device, equipment and storage medium. The method includes: respectively obtaining the OSES heartbeat signal of the dual controllers and the PWM signal input by the CPLD. In the case that any one of the dual controllers fails, controlling the other controller to receive the fan control right and controlling the CPLD of the failed controller to output a constant high-level voltage. In the case that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal, controlling both CPLDs of the dual controllers to output a constant high-level voltage. In the case that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, controlling the master controller to output a PWM signal with a target duty cycle and controlling the CPLD of the slave controller to output a constant high-level voltage. The embodiment of the present invention avoids the problem that the system crashes due to overheating caused by abnormal fan speed or stop due to faults, and improves the stability of the system.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and in particular, to a fault control method, device, equipment, and storage medium. Background Art

[0002] In a dual - control storage system, an SAS expansion chip is usually used to run an Embedded Operating System (OSES) for chassis management, so that a BMC chip is not required. In addition, since the SAS expansion chip does not have an analog - to - digital converter (ADC) and a fan control interface, a hardware management chip NCT7904 is required for fan control. The SAS Expander communicates with the NCT7904 through an I2C interface to obtain and control the fan speed.

[0003] In an existing dual - control storage system, during normal operation, the OSES system of the main controller reads the temperatures of each detection point, and controls the NCT7904 chip to output PWM to control the fan speed according to a speed - regulation strategy through an I2C interface. The PWM output of the NCT7904 chip controlled by the slave OSES system through the I2C is always at a high level and does not participate in fan speed regulation.

[0004] However, when one OSES system in the dual - control fails to start, at this time, the NCT7904 corresponding to the faulty OSES system defaults to output a Pulse - Width Modulation (PWM) with a target duty cycle. The other OSES system operates normally and controls the NCT7904 to output PWM through the I2C. The PWMs of the two controllers are combined on the backplane line, resulting in the problem that the fan speed is unstable due to the mixing of the PWMs of the two controllers. Or when one controller's NCT7904 fails and always outputs a low level, the PWM signal combined on the backplane line is forced to be pulled low by the faulty controller, causing the fan to stop rotating and the system to crash due to high temperature. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a fault control method, device, equipment, and storage medium, which solve the problem that the fan control of the existing dual - control system will cause abnormal fan speed or stop rotation, resulting in the system crashing due to overheating when a fault occurs. The specific technical solutions are as follows:

[0006] In the first aspect of the present invention, first, a fault control method is provided, which is characterized in that the method includes:

[0007] Obtain the target signals in the dual controllers respectively. The target signals include the embedded operating system OS ES heartbeat signal and the pulse width modulation PWM signal input by the CPLD. The dual controllers include a main controller and a slave controller.

[0008] When it is detected that any one of the dual controllers fails, control the other controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage. Here, a failure means that any one of the target signals is abnormal.

[0009] When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of the dual controllers to both output a constant high voltage.

[0010] When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, control the main controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage.

[0011] Optionally, when it is detected that any one of the dual controllers fails, controlling the other controller to receive the fan control right and controlling the CPLD of the failed controller to output a constant high voltage includes:

[0012] When it is detected that only the slave controller fails, control the main controller to receive the fan control right, and control the CPLD of the slave controller to output a constant high voltage.

[0013] When it is detected that only the main controller fails, control the slave controller to receive the fan control right, and control the CPLD of the main controller to output a constant high voltage.

[0014] Optionally, when it is detected that both of the dual controllers fail and the OS ES heartbeat signal of the slave controller is normal, controlling the CPLDs of the dual controllers to both output a constant high voltage includes:

[0015] When it is detected that the PWM signals input by the CPLDs of the main controller and the slave controller are both abnormal and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of the dual controllers to both output a constant high voltage.

[0016] When it is detected that the OSES heartbeat signal of the main controller is abnormal, the PWM signal input by the CPLD is normal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal input by the CPLD is abnormal, control the CPLDs of the dual controllers to both output a constant high voltage.

[0017] Optionally, when it is detected that both of the dual controllers fail and the OS ES heartbeat signal of the slave controller is abnormal, controlling the master controller to output a PWM signal with a target duty cycle, and controlling the CPLD of the slave controller to output a constant high voltage includes:

[0018] When it is detected that there is an abnormal signal and a normal signal in the target signals of the master controller and the OS ES heartbeat signal of the slave controller is abnormal, controlling the master controller to output a PWM signal with a target duty cycle, and controlling the CPLD of the slave controller to output a constant high voltage.

[0019] Optionally, before respectively obtaining the target signals in the dual controllers, further includes:

[0020] Establishing a connection between the master controller and the slave controller, so that both the master controller and the slave controller obtain the OS ES heartbeat signals of the dual controllers.

[0021] Optionally, after controlling another controller to receive the fan control right, further includes:

[0022] Obtaining the frequency of the TACH signal sent by the fan;

[0023] Adjusting the PWM signal output by another controller according to the TACH signal frequency.

[0024] Optionally, after controlling the CPLD of the slave controller to output a constant high voltage, further includes:

[0025] When it is detected that the target signals of the dual controllers are all abnormal, sending an alarm message to a target display screen so that the staff can handle it in time.

[0026] In a second aspect of the implementation of the present invention, there is also provided a fault control device, which is characterized by including:

[0027] A first acquisition module, configured to respectively acquire target signals in dual controllers, where the target signals include an embedded operating system OS ES heartbeat signal and a pulse width modulation PWM signal input by a CPLD, and the dual controllers include a master controller and a slave controller;

[0028] A first control module, configured to, when it is detected that any one of the dual controllers fails, control another controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage, where a failure means that any one of the target signals is abnormal;

[0029] A second control module, configured to control the CPLDs of the dual controllers to output a constant high-level voltage when it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal;

[0030] A third control module, configured to control the master controller to output a PWM signal with a target duty cycle and control the CPLD of the slave controller to output a constant high-level voltage when it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal.

[0031] In a third aspect of the embodiments of the present invention, there is also provided a communication device, including: a transceiver, a memory, a processor, and a program stored on the memory and executable on the processor;

[0032] The processor is configured to read the program in the memory to implement the execution of the fault control method described in any one of the above.

[0033] In a fourth aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium, in which instructions are stored, and when the instructions are run on a computer, the computer is caused to execute the fault control method described in any one of the above.

[0034] The fault control method provided by the embodiments of the present invention obtains target signals in the dual controllers respectively, where the target signals include an embedded operating system OSES heartbeat signal and a pulse width modulation PWM signal input by the CPLD. The dual controllers include a master controller and a slave controller. When it is detected that any one of the dual controllers fails, the other controller is controlled to receive the fan control right, and the CPLD of the failed controller is controlled to output a constant high-level voltage. Herein, a failure means that any one of the target signals is abnormal. When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal, the CPLDs of the dual controllers are controlled to output a constant high-level voltage. When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, the master controller is controlled to output a PWM signal with a target duty cycle, and the CPLD of the slave controller is controlled to output a constant high-level voltage. The embodiments of the present invention set different adjustment methods for different failures of the dual controllers, ensuring the normal operation of the fan, avoiding the problem that the system crashes due to overheating caused by abnormal fan speed or stop due to failures, and improving the stability of the system. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art.

[0036] Figure 1It is a flowchart of the steps of the fault control method provided by the embodiment of the present invention;

[0037] Figure 2 It is a flowchart of step 102 of the fault control method provided by the embodiment of the present invention;

[0038] Figure 3 It is a flowchart of step 103 of the fault control method provided by the embodiment of the present invention;

[0039] Figure 4 It is a flowchart of step 104 of the fault control method provided by the embodiment of the present invention;

[0040] Figure 5 It is a schematic structural diagram of a fault control device provided by the embodiment of the present invention;

[0041] Figure 6 It is a schematic structural diagram of a communication device provided by the embodiment of the present invention. Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the following will elaborate on each implementation manner of the present invention in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each implementation manner of the present invention, many technical details are proposed for the convenience of readers to understand the present application. However, even without these technical details and various changes and modifications based on the following implementation manners, the technical solutions required to be protected by the present application can still be achieved. The division of the following embodiments is for convenient description and should not constitute any limitation to the specific implementation manner of the present invention. The various embodiments can be combined and cross-referenced with each other on the premise of not conflicting with each other.

[0043] Referring to Figure 1 , a flowchart of the steps of the fault control method provided by the embodiment of the present invention is shown, and the method may include:

[0044] Step 101, respectively obtain the target signals in the dual controllers.

[0045] In the embodiments of the present invention, the dual controller is divided into a master controller and a slave controller. Each controller includes a SAS expansion chip, an NCT7904 chip, and a CPLD. Among them, an embedded operating system OSES runs in the SAS expansion chip, communicates with the NCT7904 through I2C to obtain and control the fan speed. The SAS expansion chip outputs a heartbeat signal to the CPLD of this controller and the opposite controller. The NCT7904 is a Hardware Monitor chip, which can output a PWM signal to the CPLD according to the registers configured by the OSES system and detect the frequency of the input TACH signal. The CPLD is a programmable logic unit that receives the PWM signal input by the NCT7904, detects whether the PWM is at a constant low level, outputs the PWM signal to the fan, receives the frequency of the TACH signal input by the fan and outputs it to the NCT7904.

[0046] It should be noted that the target signals in the embodiments of the present invention include the embedded operating system OSES heartbeat signal and the pulse width modulation PWM signal input to the CPLD. Among them, pulse width modulation is a very effective technology for controlling analog circuits using the digital output of a microprocessor. By changing the duty cycle, voltage regulation can be achieved. The larger the duty cycle, the larger the average voltage obtained, the larger the amplitude, and the higher the fan speed; the smaller the duty cycle, the smaller the average voltage obtained, the smaller the amplitude, and the lower the fan speed.

[0047] In addition, the master controller and the slave controller are interconnected through the backplane. There are usually ID signals between the controller and the backplane. The OSES system and the CPLD determine the position of the controller inserted on the backplane according to the ID signal. The general principle is that the lower controller is the master and the upper controller is the slave. And because of the signal interconnection, the CPLD of each controller can obtain the OSES system heartbeat signals of this controller and the opposite controller. The specific implementation steps include:

[0048] Establish a connection between the master controller and the slave controller so that both the master controller and the slave controller can obtain the OSES heartbeat signal of the dual controller.

[0049] Step 102, in the case of detecting a failure of any one of the dual controllers, control the other controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage.

[0050] In the embodiments of the present invention, a fault occurs when any signal in the target signal is abnormal, that is, the OSES heartbeat signal of the controller is abnormal, or the pulse width modulation (PWM) signal input by the CPLD is abnormal, or both the OSES heartbeat signal and the PWM signal of the controller are abnormal. When a fault occurs in any one of the dual controllers and the other controller remains normal, the control right of the fan is switched to the other controller that remains normal, and at the same time, the CPLD of the faulty controller is controlled to output a constant high voltage. Among them, when the PWM is at a constant high level, the fan rotates at full speed, and when it is at a constant low level, the fan stops rotating.

[0051] It should be noted that after the normal other controller receives the control right of the fan, it can judge the current speed of the fan by the frequency of the received TACH signal. Among them, TACH refers to the fan speed output. The higher the fan speed, the higher the frequency of the TACH signal. Therefore, the fan speed is determined by detecting the frequency of the TACH signal and corresponding adjustments are made. That is, if the current fan speed is too fast, the duty cycle of the PWM needs to be reduced to lower the fan speed, and if the current fan speed is too slow, the duty cycle of the PWM needs to be increased to increase the fan speed. Specifically, after controlling the other controller to receive the control right of the fan, it further includes:

[0052] Obtain the frequency of the TACH signal sent by the fan;

[0053] Adjust the PWM signal output by the other controller according to the TACH signal frequency.

[0054] In addition, when initially determining the duty cycle of the output PWM signal, the temperature of the system at this time is obtained according to the temperature sensor, and the output PWM signal is set according to the temperature. Setting the PWM duty cycle according to the temperature is calculated based on historical data.

[0055] Step 103, when it is detected that both dual controllers have failed and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of both dual controllers to output a constant high voltage.

[0056] In the embodiments of the present invention, both dual controllers have failed and the OSES heartbeat signal of the slave controller is normal. Therefore, the pulse width modulation (PWM) signal of the slave controller is abnormal. At this time, the OSES heartbeat signal and / or the PWM signal of the master controller are abnormal. When these situations occur, the CPLDs of both dual controllers output a constant high voltage, and at this time, the fan speed will not be adjusted and remains running at full speed.

[0057] Step 104, when it is detected that both dual controllers have failed and the OSES heartbeat signal of the slave controller is abnormal, control the master controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage.

[0058] In the embodiments of the present invention, when both controllers fail and the OSES heartbeat signal of the slave controller is abnormal, it includes the following situations: Situation 1: The OSES heartbeat signal of the master controller is abnormal, the pulse width modulation (PWM) signal is normal, and the OSES heartbeat signal of the slave controller is abnormal, and the pulse width modulation (PWM) signal is normal; Situation 2: The OSES heartbeat signal of the master controller is normal, the pulse width modulation (PWM) signal is abnormal, and the OSES heartbeat signal of the slave controller is abnormal, and the pulse width modulation (PWM) signal is normal; Situation 3: The OSES heartbeat signal of the master controller is normal, the pulse width modulation (PWM) signal is abnormal, and the OSES heartbeat signal of the slave controller is abnormal, and the pulse width modulation (PWM) signal is abnormal; Situation 4: The OSES heartbeat signal of the master controller is abnormal, the pulse width modulation (PWM) signal is normal, and the OSES heartbeat signal of the slave controller is abnormal, and the pulse width modulation (PWM) signal is abnormal. In these situations, control the master controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage.

[0059] It should be noted that when both controllers fail and the OSES heartbeat signal of the slave controller is abnormal, the master controller outputs a PWM signal with a target duty cycle. Therefore, one of the target signals of the master controller needs to remain normal. When all the target signals of the master controller are abnormal and the slave controller also fails, in order to ensure the operation of the fan, an alarm message needs to be sent to the target display screen to remind the staff to deal with the controller failure in time. The specific implementation steps include:

[0060] When it is detected that all the target signals of the two controllers are abnormal, send an alarm message to the target display screen so that the staff can deal with it in time.

[0061] The fault control method provided by the embodiment of the present invention obtains target signals in the dual controllers respectively. The target signals include the heartbeat signal of the embedded operating system OSES and the pulse width modulation PWM signal input by the CPLD. The dual controllers include a main controller and a slave controller. When it is detected that any one of the dual controllers fails, the other controller is controlled to receive the fan control right, and the CPLD of the failed controller is controlled to output a constant high voltage. Wherein, a failure means that any one of the target signals is abnormal. When it is detected that both dual controllers fail and the OSES heartbeat signal of the slave controller is normal, the CPLDs of both dual controllers are controlled to output a constant high voltage. When it is detected that both dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, the main controller is controlled to output a PWM signal with a target duty cycle, and the CPLD of the slave controller is controlled to output a constant high voltage. The embodiment of the present invention sets different adjustment methods for different failures of the dual controllers, ensures the normal operation of the fan, avoids the problems of abnormal fan speed or fan stop caused by failures, resulting in system downtime due to overheating, and improves the stability of the system.

[0062] Referring to Figure 2 , a flowchart of step 102 of the fault control method provided by the embodiment of the present invention is shown, which specifically includes:

[0063] Step 201, when it is detected that only the slave controller fails, control the main controller to receive the fan control right, and control the CPLD of the slave controller to output a constant high voltage.

[0064] In the embodiment of the present invention, the situation where only the slave controller fails includes: the OSES heartbeat signal and the PWM signal of the main controller are both normal, and the OSES heartbeat signal and / or the PWM signal of the slave controller are abnormal. At this time, the fan control right is handed over to the main controller. Since the PWM signals of the main controller and the slave controller are combined on the backplane line, in order to avoid the PWM signal of the slave controller affecting the PWM signal of the main controller, the CPLD of the slave controller is controlled to output a constant high voltage.

[0065] Step 202, when it is detected that only the main controller fails, control the slave controller to receive the fan control right, and control the CPLD of the main controller to output a constant high voltage.

[0066] In the embodiments of the present invention, the situation where only the main controller fails includes: the OSES heartbeat signal and / or the PWM signal of the main controller are abnormal, and the OSES heartbeat signal and the PWM signal of the slave controller are both normal. At this time, the control right of the fan is switched to the slave controller. Since the PWM signals of the main controller and the slave controller are together on the backplane line, in order to avoid the PWM signal of the main controller affecting the PWM signal of the slave controller, the CPLD of the main controller is controlled to output a constant high voltage.

[0067] Referring to Figure 3 , a flowchart of step 103 of the fault control method provided by the embodiments of the present invention is shown, which specifically includes:

[0068] Step 301, when it is detected that the PWM signals input to the CPLDs of both the main controller and the slave controller are abnormal and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of both controllers to output a constant high voltage.

[0069] In the embodiments of the present invention, the situation where the PWM signals input to the CPLDs of both the main controller and the slave controller are abnormal and the OSES heartbeat signal of the slave controller is normal includes: the OSES heartbeat signal of the main controller is normal, the PWM signal is abnormal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal is abnormal; the OSES heartbeat signal of the main controller is abnormal, the PWM signal is abnormal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal is abnormal. At this time, control the CPLDs of both controllers to output a constant high voltage. When the fan receives that both controllers output a constant high voltage, it runs at full speed and the speed remains unchanged.

[0070] Step 302, when it is detected that the OSES heartbeat signal of the main controller is abnormal, the PWM signal input to the CPLD is normal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal input to the CPLD is abnormal, control the CPLDs of both controllers to output a constant high voltage.

[0071] Another situation in the embodiments of the present invention to control the fan to run at full speed, that is, to control the CPLDs of both controllers to output a constant high voltage, is: the OSES heartbeat signal of the main controller is abnormal, the PWM signal input to the CPLD is normal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal input to the CPLD is abnormal.

[0072] Referring to Figure 4 , a flowchart of step 104 of the fault control method provided by the embodiments of the present invention is shown, which specifically includes:

[0073] Step 401, when an abnormal signal and a normal signal appear in the target signal of the main controller and the OSES heartbeat signal of the slave controller is abnormal, control the main controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage.

[0074] In the embodiments of the present invention, the situation where an abnormal signal and a normal signal appear in the target signal of the main controller and the OSES heartbeat signal of the slave controller is abnormal includes: the OSES heartbeat signal of the main controller is normal, the PWM signal is abnormal, the OSES heartbeat signal of the slave controller is abnormal, and the PWM signal is normal; the OSES heartbeat signal of the main controller is normal, the PWM signal is abnormal, the OSES heartbeat signal of the slave controller is abnormal, and the PWM signal is abnormal; the OSES heartbeat signal of the main controller is abnormal, the PWM signal is normal, the OSES heartbeat signal of the slave controller is abnormal, and the PWM signal is normal; the OSES heartbeat signal of the main controller is abnormal, the PWM signal is normal, the OSES heartbeat signal of the slave controller is abnormal, and the PWM signal is abnormal; in these cases, the main controller outputs a PWM signal with a target duty cycle, and the CPLD of the slave controller outputs a constant high voltage. Among them, the target duty cycle is based on the results obtained through multiple implementations.

[0075] Refer to Figure 5 , which shows the structural schematic diagram of a fault control device provided by the embodiments of the present invention. As Figure 5 shown, the device may include:

[0076] The first acquisition module 501 is configured to respectively acquire the target signals in the dual controllers, where the target signals include the embedded operating system OSES heartbeat signal and the pulse width modulation PWM signal input to the CPLD, and the dual controllers include a main controller and a slave controller.

[0077] The first control module 502 is configured to, when it is detected that any one of the dual controllers fails, control the other controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage, where a failure means that any one of the signals in the target signal is abnormal.

[0078] The second control module 503 is configured to, when it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of the dual controllers to both output a constant high voltage.

[0079] The third control module 504 is configured to, when it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, control the main controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage.

[0080] Optionally, the first control module 502 further includes:

[0081] A first control sub-module, configured to control the master controller to receive the fan control right and control the CPLD of the slave controller to output a constant high voltage when it is detected that only the slave controller fails.

[0082] A second control sub-module, configured to control the slave controller to receive the fan control right and control the CPLD of the master controller to output a constant high voltage when it is detected that only the master controller fails.

[0083] Optionally, the second control module 503 further includes:

[0084] A third control sub-module, configured to control the CPLDs of the dual controllers to output constant high voltages when it is detected that the PWM signals input to the CPLDs of the master controller and the slave controller are both abnormal and the OSES heartbeat signal of the slave controller is normal.

[0085] A fourth control sub-module, configured to control the CPLDs of the dual controllers to output constant high voltages when it is detected that the OSES heartbeat signal of the master controller is abnormal, the PWM signal input to the CPLD is normal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal input to the CPLD is abnormal.

[0086] Optionally, the second control module 504 further includes:

[0087] A fifth control sub-module, configured to control the master controller to output a PWM signal with a target duty cycle and control the CPLD of the slave controller to output a constant high voltage when it is detected that one of the target signals of the master controller is an abnormal signal and the other is a normal signal and the OSES heartbeat signal of the slave controller is abnormal.

[0088] Optionally, the fault control device further includes:

[0089] A connection establishment module, configured to establish a connection between the master controller and the slave controller so that both the master controller and the slave controller can obtain the OSES heartbeat signals of the dual controllers.

[0090] A second acquisition module, configured to acquire the frequency of the TACH signal sent by the fan.

[0091] An adjustment module, configured to adjust the PWM signal output by the other controller according to the TACH signal frequency.

[0092] An alarm module, configured to send an alarm message to a target display screen when it is detected that the target signals of the dual controllers are both abnormal, so that the staff can handle it in time.

[0093] The fault control method provided by the embodiments of the present invention obtains the target signals in the dual controllers respectively. The target signals include the heartbeat signal of the embedded operating system OSES and the pulse width modulation PWM signal input by the CPLD. The dual controllers include a main controller and a slave controller. When it is detected that any one of the dual controllers fails, control the other controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage. Wherein, a failure means that any one of the target signals is abnormal. When it is detected that both dual controllers fail and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of both dual controllers to output a constant high voltage. When it is detected that both dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, control the main controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage. The embodiments of the present invention set different adjustment methods for different failures of the dual controllers, ensure the normal operation of the fan, avoid the problem that the system crashes due to overheating caused by abnormal fan speed or stoppage due to failures, and improve the stability of the system.

[0094] The embodiments of the present invention also provide a communication device, as Figure 6 shown, including a processor 601, a communication interface 602, a memory 603, and a communication bus 604. Among them, the processor 601, the communication interface 602, and the memory 603 complete the communication with each other through the communication bus 604.

[0095] The memory 603 is used to store a computer program;

[0096] The processor 601, when executing the program stored on the memory 603, implements the following steps:

[0097] Obtain the target signals in the dual controllers respectively. The target signals include the heartbeat signal of the embedded operating system OS ES and the pulse width modulation PWM signal input by the CPLD. The dual controllers include a main controller and a slave controller;

[0098] When it is detected that any one of the dual controllers fails, control the other controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage. Wherein, a failure means that any one of the target signals is abnormal;

[0099] When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of both of the dual controllers to output a constant high voltage level.

[0100] When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, control the master controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage level.

[0101] The communication bus mentioned in the above terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0102] The communication interface is used for communication between the above terminal and other devices.

[0103] The memory may include a Random Access Memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0104] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0105] The present invention also provides a readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, enabling the electronic device to execute the access control method of the foregoing embodiments.

[0106] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For related parts, please refer to the partial description of the method embodiments.

[0107] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Based on the above description, the structures required to construct such systems are obvious. In addition, the present invention is not directed to any particular programming language. It should be understood that the content of the present invention described herein can be implemented using various programming languages, and the descriptions of specific languages above are for disclosing the best implementation manners of the present invention.

[0108] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0109] Similarly, it should be understood that, in order to streamline the present invention and help understand one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0110] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0111] Each component embodiment of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or device program for executing part or all of the methods described herein. Such a program for implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0112] It should be noted that the above embodiments are illustrative of the present invention rather than restrictive, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

[0113] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0114] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0115] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present invention and should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0116] It should be noted that in the embodiments of the present application, all processes related to obtaining various data are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the owner of the corresponding device.

Claims

1. A fault control method, characterized in that, the method includes: respectively obtaining target signals in the dual controllers, where the target signals include an embedded operating system OS ES heartbeat signal and a pulse width modulation PWM signal input by a CPLD, and the dual controllers include a main controller and a slave controller; in the case where a fault occurs in any one of the dual controllers, controlling the other controller to receive the fan control right, and controlling the CPLD of the faulty controller to output a constant high voltage, where a fault means that any one of the target signals is abnormal; in the case where faults occur in both of the dual controllers and the OSES heartbeat signal of the slave controller is normal, controlling the CPLDs of the dual controllers to both output a constant high voltage, where both of the dual controllers having faults means that the PWM signals input to the CPLDs of the main controller and the slave controller are both abnormal or the OSES heartbeat signal of the main controller is abnormal, the PWM signal input to the CPLD is normal and the PWM signal input to the CPLD of the slave controller is abnormal; in the case where faults occur in both of the dual controllers and the OSES heartbeat signal of the slave controller is abnormal, controlling the main controller to output a PWM signal with a target duty cycle, and controlling the CPLD of the slave controller to output a constant high voltage.

2. The method according to claim 1, characterized in that, the controlling the other controller to receive the fan control right and controlling the CPLD of the faulty controller to output a constant high voltage in the case where a fault occurs in any one of the dual controllers includes: in the case where only the slave controller has a fault, controlling the main controller to receive the fan control right, and controlling the CPLD of the slave controller to output a constant high voltage; in the case where only the main controller has a fault, controlling the slave controller to receive the fan control right, and controlling the CPLD of the main controller to output a constant high voltage.

3. The method according to claim 1, characterized in that, the controlling the CPLDs of the dual controllers to both output a constant high voltage in the case where faults occur in both of the dual controllers and the OSES heartbeat signal of the slave controller is normal includes: in the case where the PWM signals input to the CPLDs of the main controller and the slave controller are both abnormal and the OSES heartbeat signal of the slave controller is normal, controlling the CPLDs of the dual controllers to both output a constant high voltage; in the case where the OSES heartbeat signal of the main controller is abnormal, the PWM signal input to the CPLD is normal, the OSES heartbeat signal of the slave controller is normal, and the PWM signal input to the CPLD of the slave controller is abnormal, controlling the CPLDs of the dual controllers to both output a constant high voltage.

4. The method according to claim 1, characterized in that, When it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, controlling the master controller to output a PWM signal with a target duty cycle, and controlling the CPLD of the slave controller to output a constant high voltage, includes: When it is detected that one abnormal signal and one normal signal appear in the target signals of the master controller and the OSES heartbeat signal of the slave controller is abnormal, controlling the master controller to output a PWM signal with a target duty cycle, and controlling the CPLD of the slave controller to output a constant high voltage.

5. The method according to claim 1, characterized in that, before separately obtaining the target signals in the dual controllers, further includes: Establishing a connection between the master controller and the slave controller, so that both the master controller and the slave controller obtain the OSES heartbeat signals of the dual controllers.

6. The method according to claim 1, characterized in that, after controlling the other controller to receive the fan control right, further includes: Obtaining the frequency of the TACH signal sent by the fan; Adjusting the PWM signal output by the other controller according to the TACH signal frequency.

7. The method according to claim 1, characterized in that, after controlling the CPLD of the slave controller to output a constant high voltage, further includes: When it is detected that the target signals of the dual controllers are both abnormal, sending an alarm message to a target display screen so that the staff can handle it in time.

8. A fault control device, characterized in that, includes: A first acquisition module, configured to separately acquire target signals in dual controllers, the target signals include an embedded operating system OSES heartbeat signal and a pulse width modulation PWM signal input by the CPLD, and the dual controllers include a master controller and a slave controller; A first control module, configured to, when it is detected that any one of the dual controllers fails, control the other controller to receive the fan control right, and control the CPLD of the failed controller to output a constant high voltage, where a failure means that any one of the target signals is abnormal; A second control module, configured to, when it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is normal, control the CPLDs of the dual controllers to both output constant high voltages, and both of the dual controllers fail means that the PWM signals input by the CPLDs of the master controller and the slave controller are both abnormal, or the OSES heartbeat signal of the master controller is abnormal, the PWM signal input by the CPLD is normal, and the PWM signal input by the CPLD of the slave controller is abnormal; A third control module, configured to, when it is detected that both of the dual controllers fail and the OSES heartbeat signal of the slave controller is abnormal, control the master controller to output a PWM signal with a target duty cycle, and control the CPLD of the slave controller to output a constant high voltage.

9. A communication device, characterized in that, includes: A transceiver, a memory, a processor, and a program stored on the memory and executable on the processor; The processor is configured to read the program in the memory to implement the steps in the fault control method according to any one of claims 1-7.

10. A readable storage medium for storing a program, characterized in that, when the program is executed by a processor, it implements the steps in the fault control method according to any one of claims 1-7.

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