FPGA simulation verification method, device, electronic device and storage medium

Abstract

The present application relates to the field of communication technology, and in particular to an FPGA simulation verification method, device, electronic device, and storage medium. The method comprises: inputting test data into a virtual uplink interface and receiving first output data output by the virtual uplink interface; inputting the first output data into an FPGA simulation module for data processing and receiving second output data output by the FPGA simulation module; inputting the second output data into a virtual downlink interface and receiving third output data output by the virtual downlink interface; and obtaining a simulation verification result of the FPGA to be verified based on the first output data, the second output data, and the third output data, in combination with their respective corresponding expected standard data. In this way, not only the target logic function of the FPGA to be verified is simulated, but also the hardware interface of the device to be installed on the FPGA to be verified is simulated, thereby improving the accuracy of the simulation verification.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an FPGA simulation verification method, device, electronic device, and storage medium. Background Art

[0002] With the advancement of communications technology, large-scale, high-speed, and highly complex data communication chip designs are becoming increasingly common. This is especially true for large-scale logic designs based on Field Programmable Gate Arrays (FPGAs), which perform numerous and complex logic functions. To ensure the reliability of FPGA designs in practical applications, simulation verification is often required before they are put into use.

[0003] In the prior art, when simulating and verifying an FPGA, a corresponding test stimulus module is usually developed to simulate and verify the logic function modules of the FPGA.

[0004] For example, see Figure 1 The figure shows a schematic diagram of a test stimulus module simulation. The logic function module A has an input terminal and an output terminal. During simulation, a test stimulus module A needs to be developed to simulate the logic function module A. The output of the test stimulus module A corresponds to the input of the logic function module A, and the input of the test stimulus module A corresponds to the output of the logic function module A. The test data generated by the test stimulus module A is processed by the logic function module A and the processing result is transmitted to the input terminal of the test stimulus module A through the output terminal of the logic function module A. The test stimulus module A determines whether the function of the logic function module A is normal by comparing whether the received processing result is consistent with the expected result.

[0005] However, since the test stimulus module only simulates and verifies the corresponding logical function module and does not simulate and verify the function of the FPGA on the actual physical device, problems related to the hardware interface of the actual physical device are difficult to expose during the simulation verification process. The simulation verification results are not consistent with the results of the test on the actual physical device, resulting in inaccurate simulation results.

[0006] In addition, since each development of a logic function module requires the development of a corresponding test stimulus module to simulate and verify the logic function module, the development workload of the test stimulus module is greater than that of the logic function module, resulting in low execution efficiency of FPGA simulation verification.

[0007] In view of this, the accuracy and execution efficiency of FPGA simulation verification under relevant technologies need to be further improved. Summary of the Invention

[0008] The embodiments of the present application provide an FPGA simulation verification method, device, electronic device, and storage medium to improve the accuracy and execution efficiency of FPGA simulation verification.

[0009] The specific technical solutions provided in the embodiments of this application are as follows:

[0010] In a first aspect, an FPGA simulation verification method is provided, comprising:

[0011] Inputting test data into a virtual uplink interface and receiving first output data output by the virtual uplink interface, wherein the virtual uplink interface is obtained by virtualizing an uplink hardware interface of a target physical device, and the target physical device is a device to be installed in the FPGA to be verified;

[0012] Inputting the first output data into an FPGA simulation module for data processing, and receiving second output data output by the FPGA simulation module, wherein the FPGA simulation module simulates the target logic function of the FPGA to be verified;

[0013] Inputting the second output data to the virtual downstream interface, and receiving the third output data output by the virtual downstream interface, wherein the virtual downstream interface is obtained by virtualizing the downstream hardware interface of the target physical device;

[0014] Based on the first output data, the second output data and the third output data, in combination with their corresponding expected standard data, a simulation verification result of the FPGA to be verified is obtained.

[0015] Optionally, before inputting the test data into the virtual uplink interface, the method further includes:

[0016] Abstracting the physical resources of the uplink hardware interface of the target physical device into corresponding first logical resources, and generating a virtual uplink interface corresponding to the uplink hardware interface based on the first logical resources;

[0017] The physical resources of the downstream hardware interface of the target physical device are abstracted into corresponding second logical resources, and a virtual downstream interface corresponding to the downstream hardware interface is generated based on the second logical resources.

[0018] Optionally, input test data to the virtual uplink interface, including:

[0019] Determine the physical interface for transmitting the test data based on the attribute information of the virtual uplink interface;

[0020] Forward test data through the physical interface to the virtual uplink interface.

[0021] Optionally, inputting the first output data into an FPGA simulation module for data processing, and receiving second output data output by the FPGA simulation module, includes:

[0022] Compile the logic development program of the FPGA to be verified to obtain the logic dynamic link library corresponding to the logic development program;

[0023] Call the FPGA simulation tool to load the logic dynamic link library;

[0024] The first output data is input into an FPGA simulation tool to obtain second output data output after being processed by the FPGA simulation tool using a logic dynamic link library.

[0025] Optionally, obtaining a simulation verification result of the FPGA to be verified based on the first output data, the second output data, and the third output data in combination with their respective corresponding expected standard data includes:

[0026] If the first output data, the second output data, and the third output data satisfy at least one of the following conditions, the simulation verification result of the FPGA to be verified is determined to be abnormal:

[0027] The first output data is inconsistent with the first standard data corresponding to it;

[0028] The second output data is inconsistent with the corresponding second standard data;

[0029] The third output data is inconsistent with its corresponding third standard data.

[0030] Optionally, after determining that the simulation verification result of the FPGA to be verified is abnormal, the method further includes:

[0031] If the simulation verification result indicates that the virtual uplink interface is abnormal, determining the abnormal problem related to the virtual uplink interface based on the saved first debugging information corresponding to the virtual uplink interface;

[0032] If the simulation verification results indicate that the target logic function is abnormal, the abnormal problem in the target logic function is determined based on the simulation waveform diagram saved by the FPGA simulation tool;

[0033] If the simulation verification result indicates that the virtual downstream interface is abnormal, the abnormal problem related to the virtual downstream interface is determined based on the saved second debugging information corresponding to the virtual upstream interface.

[0034] In a second aspect, an FPGA simulation verification device is provided, comprising:

[0035] A first processing module is configured to input test data into a virtual uplink interface and receive first output data output by the virtual uplink interface, wherein the virtual uplink interface is obtained by virtualizing an uplink hardware interface of a target physical device, and the target physical device is a device to be installed in the FPGA to be verified;

[0036] a second processing module, configured to input the first output data into an FPGA simulation module for data processing, and receive second output data output by the FPGA simulation module, wherein the FPGA simulation module simulates a target logic function of the FPGA to be verified;

[0037] a third processing module, configured to input the second output data to a virtual downstream interface and receive third output data output by the virtual downstream interface, wherein the virtual downstream interface is obtained by virtualizing a downstream hardware interface of a target physical device;

[0038] The generation module is used to obtain a simulation verification result of the FPGA to be verified based on the first output data, the second output data and the third output data in combination with their respective corresponding expected standard data.

[0039] Optionally, before inputting the test data into the virtual uplink interface, the apparatus further includes a preprocessing module, wherein the preprocessing module is configured to:

[0040] Abstracting the physical resources of the uplink hardware interface of the target physical device into corresponding first logical resources, and generating a virtual uplink interface corresponding to the uplink hardware interface based on the first logical resources;

[0041] The physical resources of the downstream hardware interface of the target physical device are abstracted into corresponding second logical resources, and a virtual downstream interface corresponding to the downstream hardware interface is generated based on the second logical resources.

[0042] Optionally, when inputting the test data into the virtual uplink interface, the first processing module is further configured to:

[0043] Determine the physical interface for transmitting the test data based on the attribute information of the virtual uplink interface;

[0044] Forward test data through the physical interface to the virtual uplink interface.

[0045] Optionally, when the first output data is input to the FPGA simulation module for data processing and the second output data output by the FPGA simulation module is received, the second processing module is further configured to:

[0046] Compile the logic development program of the FPGA to be verified to obtain the logic dynamic link library corresponding to the logic development program;

[0047] Call the FPGA simulation tool to load the logic dynamic link library;

[0048] The first output data is input into an FPGA simulation tool to obtain second output data output after being processed by the FPGA simulation tool using a logic dynamic link library.

[0049] Optionally, when obtaining a simulation verification result of the FPGA to be verified based on the first output data, the second output data, and the third output data in combination with their respective corresponding expected standard data, the generating module is further configured to:

[0050] If the first output data, the second output data, and the third output data satisfy at least one of the following conditions, the simulation verification result of the FPGA to be verified is determined to be abnormal:

[0051] The first output data is inconsistent with the first standard data corresponding to it;

[0052] The second output data is inconsistent with the corresponding second standard data;

[0053] The third output data is inconsistent with its corresponding third standard data.

[0054] Optionally, after determining that the simulation verification result of the FPGA to be verified is abnormal, the apparatus further includes a determination module, the determination module being configured to:

[0055] If the simulation verification result indicates that the virtual uplink interface is abnormal, determining the abnormal problem related to the virtual uplink interface based on the saved first debugging information corresponding to the virtual uplink interface;

[0056] If the simulation verification results indicate that the target logic function is abnormal, the abnormal problem in the target logic function is determined based on the simulation waveform diagram saved by the FPGA simulation tool;

[0057] If the simulation verification result indicates that the virtual downstream interface is abnormal, the abnormal problem related to the virtual downstream interface is determined based on the saved second debugging information corresponding to the virtual upstream interface.

[0058] In a third aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any one of the methods described in the first aspect are implemented.

[0059] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in any one of the first aspects are implemented.

[0060] In a fifth aspect, a computer program product is provided, which includes a computer program, and the computer program is stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the electronic device performs the steps of any one of the methods described in the first aspect above.

[0061] In an embodiment of the present application, the service device first inputs the test data constructed by the data device into the virtual upstream interface, and receives the first output data output by the virtual upstream interface, wherein the virtual upstream interface is obtained by virtualizing the upstream hardware interface of the target physical device, and the target physical device is the device to be installed of the FPGA to be verified. The first output data is then input into the FPGA simulation module for data processing, and the second output data output by the FPGA simulation module is received, wherein the FPGA simulation module is a simulation of the target logical function of the FPGA to be verified. Then, the second output data is input into the virtual downstream interface, and the third output data output by the virtual downstream interface is received, wherein the virtual downstream interface is obtained by virtualizing the downstream hardware interface of the target physical device. Finally, based on the first output data, the second output data and the third output data, combined with their respective corresponding expected standard data, the simulation verification result of the FPGA to be verified is obtained. In this way, when determining the simulation verification results of the FPGA to be verified, not only the target logic function of the FPGA to be verified is simulated, but also the upstream hardware interface and downstream hardware interface of the device to be installed on the FPGA to be verified are simulated, thereby improving the accuracy of the simulation verification. In addition, the test data constructed by the data device is called, and there is no need to develop a large number of stimulus test modules, which simplifies the test data input process and improves the execution efficiency of the FPGA simulation verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 This is a schematic diagram of a test stimulus module simulation in an embodiment of the present application;

[0063] Figure 2 This is a schematic diagram of an application scenario in an embodiment of the present application;

[0064] Figure 3 This is a schematic diagram of a pre-processing process in an embodiment of the present application;

[0065] Figure 4 A schematic diagram of a hardware interface of a target physical device in an embodiment of the present application;

[0066] Figure 5 This is a flowchart of an FPGA simulation verification method in an embodiment of the present application;

[0067] Figure 6This is a flow chart of transmitting test data to a virtual uplink interface in an embodiment of the present application;

[0068] Figure 7 This is a schematic diagram of transmitting test data to a virtual uplink interface in an embodiment of the present application;

[0069] Figure 8 This is a flow chart of data processing in the FPGA simulation module according to an embodiment of the present application;

[0070] Figure 9 This is a schematic diagram of the first output data being input into the FPGA simulation module for data processing in an embodiment of the present application;

[0071] Figure 10 This is a schematic diagram of inputting the second output data to the virtual downlink interface in an embodiment of the present application;

[0072] Figure 11 A schematic diagram of a process for determining the simulation verification result of the FPGA to be verified in an embodiment of the present application;

[0073] Figure 12 This is a first schematic diagram of determining the simulation verification result of the FPGA to be verified in an embodiment of the present application;

[0074] Figure 13 A second schematic diagram of determining the simulation verification result of the FPGA to be verified in an embodiment of the present application;

[0075] Figure 14 A schematic diagram of a process for determining abnormalities in an FPGA to be verified according to an embodiment of the present application;

[0076] Figure 15 This is an example diagram of FPGA simulation verification in the embodiment of this application;

[0077] Figure 16 This is a structural diagram of the FPGA simulation verification device in the embodiment of the present application;

[0078] Figure 17 This is a schematic diagram of the structure of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0080] The following explains some of the terms used in the embodiments of the present application to facilitate understanding by those skilled in the art.

[0081] (1) FPGA logic development program: refers to the program developed by developers using hardware description language to describe the internal logic structure of FPGA. Common hardware programming languages include hardware description language (Verilog) and very high-speed integrated circuit hardware description language (VHDL).

[0082] (2) Data equipment: test instruments or test programs used to construct test data, such as IXIA, TREX, and TC.

[0083] The preferred implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0084] like Figure 2 As shown, it is a schematic diagram of an application scenario of an embodiment of the present application. It is a schematic diagram of an application scenario of an embodiment of the present application. The application scenario diagram includes a service device 210 and a data device 220. The service device 210 calls the data device 220 to construct test data. The service device 210 inputs the test data to the virtual uplink interface and receives the first output data output by the virtual uplink interface. The service device 210 then inputs the first output data to the FPGA simulation module for data processing and receives the second output data output by the FPGA simulation module. Then, the second output data is input to the virtual downlink interface and the third output data output by the virtual downlink interface is received. Finally, based on the first output data, the second output data and the third output data, combined with their respective corresponding expected standard data, the simulation verification result of the FPGA to be verified is obtained.

[0085] The service device 210 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. This application does not impose any restrictions on this.

[0086] Based on the above embodiments, see Figure 3 The figure is a schematic diagram of a pre-processing process in an embodiment of the present application, which specifically includes:

[0087] Step 30: abstracting the physical resources of the uplink hardware interface of the target physical device into corresponding first logical resources, and generating a virtual uplink interface corresponding to the uplink hardware interface based on the first logical resources.

[0088] Among them, the target physical device can be an FPGA network card and other devices, the uplink hardware interface can be an Ethernet interface, a high-speed serial computer expansion (Peripheral Component Interconnect Express, PCIE) interface and a serial hard disk (Serial Advanced Technology Attachment, SATA) interface, etc., and the downlink hardware interface can be an Ethernet interface, PCIE interface and SATA interface, etc., which is not limited in the embodiments of the present application.

[0089] For example, see Figure 4 The figure shows a schematic diagram of the hardware interface of the target physical device in the embodiment of the present application. The target physical device is an FPGA network card. The FPGA network card includes a PCIE interface and an Ethernet interface. The data in the network enters the FPGA chip for processing through the Ethernet interface and is then transmitted to the host through the PCIE interface. Correspondingly, the data on the host side is transmitted to the FPGA chip through the PCIE interface and then sent to the network through the Ethernet interface. Based on the data transmission direction of the FPGA network card, the uplink hardware interface and the downlink hardware interface are determined. If the data transmission direction is from the Ethernet interface to the PCIE interface, the uplink hardware interface is the Ethernet interface and the downlink hardware interface is the PCIE interface. If the data transmission direction is from the PCIE interface to the Ethernet interface, the uplink hardware interface is the PCIE interface and the downlink hardware interface is the Ethernet interface.

[0090] In an embodiment of the present application, a virtualization tool is called to abstract the physical resources of the uplink hardware interface of the target physical device into corresponding first logical resources, and the uplink hardware interface is mapped into a virtual uplink interface based on the first logical resources.

[0091] Among them, the virtualization tool can be a virtual operating system emulator (Quick EMUlator, QEMU) and the like, which is not limited in the embodiments of the present application.

[0092] For example, assuming that the uplink hardware interface is an Ethernet interface, the physical resources of the Ethernet interface are abstracted into corresponding first logical resources, and the Ethernet interface is mapped into a virtual Ethernet interface according to the first logical resources.

[0093] Step 31: abstracting the physical resources of the downstream hardware interface of the target physical device into corresponding second logical resources, and generating a virtual downstream interface corresponding to the downstream hardware interface based on the second logical resources.

[0094] In an embodiment of the present application, a virtualization tool is called to abstract the physical resources of the downstream hardware interface of the target physical device into corresponding second logical resources, and the downstream hardware interface is mapped into a virtual downstream interface based on the second logical resources.

[0095] For example, assuming that the downlink hardware interface is a PCIE interface, the physical resources of the PCIE interface are abstracted into corresponding second logical resources, and the PCIE interface is mapped into a virtual PCIE interface according to the second logical resources.

[0096] In this way, the hardware uplink interface and the hardware downlink interface are virtualized, so that the uplink virtual interface and the downlink virtual interface can normally receive and send data.

[0097] Furthermore, in the embodiment of the present application, after pre-processing, the simulation verification result of the FPGA to be verified can be determined based on the virtual uplink interface and the virtual downlink interface, see Figure 5 As shown, it is a flow chart of an FPGA simulation verification method in the embodiment of the present application. Figure 5 , describe the specific operations in detail:

[0098] Step 32: Input the test data to the virtual uplink interface, and receive the first output data output by the virtual uplink interface.

[0099] The virtual uplink interface is obtained by virtualizing the uplink hardware interface of the target physical device, and the target physical device is a device to be installed in the FPGA to be verified.

[0100] In the embodiment of the present application, after the data device is called to construct the test data, the test data is input to the virtual uplink interface, and the first output data output by the virtual uplink interface is received.

[0101] Among them, the test data can be network messages such as Internet Protocol (IP) messages, User Datagram Protocol (UDP) messages, Transmission Control Protocol (TCP) messages, Address Resolution Protocol (ARP) messages, HTTP messages and ICMP messages, which are not limited in the embodiments of the present application.

[0102] For example, assuming that the test data is 100 UDP packets, the 100 UDP packets are input to the virtual uplink interface, and the first output data output by the virtual uplink interface is received.

[0103] In this way, users can flexibly call data devices to construct test data according to actual conditions. There is no need for professionals to develop a large number of test stimulus modules, which reduces the development workload and simplifies the test data input process, thereby improving the execution efficiency of FPGA simulation verification and enriching the diversity of test data input, providing convenience for users.

[0104] Specifically, when executing step 32, the service device performs the following operations. Figure 6 As shown in FIG, it is a flow chart of the test data transmission to the virtual uplink interface in the embodiment of the present application. Figure 6 , describe the specific operations in detail:

[0105] Step 320: Determine the physical interface for transmitting the test data based on the attribute information of the virtual uplink interface.

[0106] In the embodiment of the present application, after the uplink hardware interface of the target physical device is virtualized, the physical interface for transmitting the test data is determined based on the attribute information of the virtual uplink interface.

[0107] The physical interface is an interface that can transmit test data to the virtual uplink interface.

[0108] For example, assuming that the virtual uplink interface is a virtual Ethernet interface, the physical interface for transmitting test data can be a physical network port, which is not limited in the embodiments of the present application.

[0109] Step 321: Forward the test data to the virtual uplink interface through the physical interface.

[0110] In the embodiment of the present application, after obtaining the physical interface for transmitting the test data, the test data is forwarded to the virtual uplink interface through the physical interface.

[0111] For example, see Figure 7 As shown, this is a schematic diagram of transmitting test data to the virtual uplink interface in an embodiment of the present application. Assuming that the physical interface is a physical network port, the test data is forwarded to the virtual Ethernet interface through the physical network port.

[0112] In this way, a data channel for sending the test data to the virtual uplink interface is opened through the physical interface, so that the test data can be successfully sent to the virtual uplink interface.

[0113] Step 33: Input the first output data to the FPGA simulation module for data processing, and receive the second output data output by the FPGA simulation module.

[0114] Among them, the FPGA simulation module is used to simulate the target logic function of the FPGA to be verified.

[0115] In addition, it is worth noting that the FPGA simulation module and the virtual uplink interface can be connected according to the UDP protocol, and the FPGA simulation module and the virtual downlink interface can be connected according to the UDP protocol. The connection protocol is not restricted in the embodiments of the present application.

[0116] In an embodiment of the present application, after obtaining the first output data, the first output data is input into the FPGA simulation module for data processing, and the second output data output by the FPGA simulation module is received.

[0117] For example, assuming that the first output data obtained is 100 UDP packets, the 100 UDP packets are input into the FPGA simulation module for data processing, and the second output data output by the FPGA simulation module is received.

[0118] Specifically, when executing step 33, the service device performs the following operations. Figure 8 As shown in the figure, it is a flow chart of data processing of FPGA simulation module in the embodiment of the present application. Figure 8 , describe the specific operations in detail:

[0119] Step 330: Compile the logic development program of the FPGA to be verified to obtain a logic dynamic link library corresponding to the logic development program.

[0120] In an embodiment of the present application, a compilation tool provided by an FPGA manufacturer or other third party is called to compile the logic development program of the FPGA to be verified, and a logic dynamic link library corresponding to the logic development program is obtained.

[0121] The data input or output interface of the logic development program of the FPGA to be verified may be an Advanced Extensible Interface (AXI) and an Advanced Extensible Interface Stream (AXIS).

[0122] For example, the xelab tool is called to compile the logic development program of the FPGA to be verified into a logic dynamic link library in the so format under Linux and a logic dynamic link library in the dll format under Windows.

[0123] In this way, the compiled logic dynamic link library can use C or C++ programs to call FPGA logic, including calling the AXI interface or AXIS interface in the FPGA logic for data input and output.

[0124] Step 331: Call the FPGA simulation tool to load the logic dynamic link library.

[0125] In an embodiment of the present application, after obtaining the logic dynamic link library, the FPGA simulation tool is called and run to load the logic dynamic link library onto the FPGA simulation tool.

[0126] Among them, the FPGA simulation tool can be an extensible simulation platform (XSimStudio, XSIM) and HDL language simulation software, etc., which is not limited in the embodiments of the present application.

[0127] Step 332: Input the first output data into the FPGA simulation tool to obtain the second output data output after the FPGA simulation tool processes the data using the logic dynamic link library.

[0128] In an embodiment of the present application, the obtained first output data is input into an FPGA simulation tool, and the FPGA simulation tool uses a logic dynamic link library to process the first output data to obtain the processed second output data.

[0129] For example, see Figure 9 As shown, this is a schematic diagram of the first output data input into the FPGA simulation module for data processing in an embodiment of the present application. Assuming that the first output data is 100 UDP packets, the FPGA logic of the logic dynamic link library filters the data and only retains 10 UDP packets. The FPGA simulation tool filters the first output data to obtain the second output data after processing.

[0130] In this way, the FPGA logic development program is compiled into a logic dynamic link library that can be called by the software program, and simulated in combination with the FPGA simulation tool, which can realize the simulation verification of the FPGA logic function.

[0131] Step 34: Input the second output data to the virtual downstream interface, and receive the third output data output by the virtual downstream interface.

[0132] The virtual downstream interface is obtained by virtualizing the downstream hardware interface of the target physical device.

[0133] In the embodiment of the present application, after obtaining the second output data, the second output data is input to the virtual downstream interface, and the third output data output by the virtual downstream interface is received.

[0134] For example, see Figure 10 As shown, this is a schematic diagram of the second output data input to the virtual downstream interface in an embodiment of the present application. Assuming that the virtual downstream interface is a virtual PCIE interface and the second output data is 10 UDP packets, the 10 UDP packets are input to the virtual PCIE interface, and the third output data output by the virtual PCIE interface is received.

[0135] Optionally, in an embodiment of the present application, after obtaining the third output data, the third output data can be returned to the data device through the virtual downstream interface, FPGA simulation module, and virtual upstream interface in sequence to obtain the fourth output data.

[0136] Step 35: Based on the first output data, the second output data, and the third output data, in combination with their corresponding expected standard data, a simulation verification result of the FPGA to be verified is obtained.

[0137] In an embodiment of the present application, after obtaining the third output data, the first test result of the FPGA to be verified is determined based on the first output data and its corresponding expected standard data, the second test result of the FPGA to be verified is determined based on the second output data and its corresponding expected standard data, the third test result of the FPGA to be verified is determined based on the third output data and its corresponding expected standard data, and the simulation verification result of the FPGA to be verified is determined based on the first test result, the second test result and the third test result.

[0138] Specifically, when executing step 35, the service device performs the following operations. Figure 11 FIG. 1 is a flow chart showing the flow of determining the simulation verification result of the FPGA to be verified in the embodiment of the present application. Figure 11 , describe the specific operations in detail:

[0139] Step 350: Determine whether the first output data, the second output data, and the third output data meet at least one of the following conditions; if so, execute step 351; otherwise, execute step 352.

[0140] Condition 1: The first output data is inconsistent with its corresponding first standard data.

[0141] Condition 2: The second output data is inconsistent with its corresponding second standard data.

[0142] Condition 3: The third output data is inconsistent with its corresponding third standard data.

[0143] Step 351: Determine whether the simulation verification result of the FPGA to be verified is abnormal.

[0144] In an embodiment of the present application, it is determined whether the first output data, the second output data, and the third output data meet at least one of the above conditions. If at least one condition is met, it is determined that the simulation verification result of the FPGA to be verified is abnormal.

[0145] For example, see Figure 12As shown, this is the first schematic diagram for determining the simulation verification result of the FPGA to be verified in an embodiment of the present application. Assuming that the test data is 100 UDP packets, the logical function of the FPGA to be verified is to retain 10 UDP packets, the first output data is 100 UDP packets, the second output data is 10 UDP packets, and the third output data is 5 UDP packets. Then, the first standard data corresponding to the first output data is 100 UDP packets, the second standard data corresponding to the second output data is 10 UDP packets, and the third standard data corresponding to the third output data is 10 UDP packets. The first output data 100 UDP packets are consistent with the corresponding first standard data, the second output data 10 UDP packets are consistent with the corresponding second standard data, and the third output data 5 UDP packets are inconsistent with the corresponding third standard data. It is determined that the simulation verification result of the FPGA to be verified is abnormal.

[0146] Step 352: Determine whether the simulation verification result of the FPGA to be verified is normal.

[0147] In an embodiment of the present application, it is determined whether the first output data, the second output data, and the third output data meet at least one of the above conditions. If at least one condition is not met, it is determined that the simulation verification result of the FPGA to be verified is normal.

[0148] For example, see Figure 13 As shown, this is a second schematic diagram of determining the simulation verification result of the FPGA to be verified in an embodiment of the present application. Assuming that the test data is 100 UDP packets, the logical function of the FPGA to be verified is to retain 10 UDP packets, the first output data is 100 UDP packets, the second output data is 10 UDP packets, and the third output data is 10 UDP packets. Then, the first standard data corresponding to the first output data is 100 UDP packets, the second standard data corresponding to the second output data is 10 UDP packets, and the third standard data corresponding to the third output data is 10 UDP packets. The first output data 100 UDP packets are consistent with the corresponding first standard data, the second output data 10 UDP packets are consistent with the corresponding second standard data, and the third output data 10 UDP packets are consistent with the corresponding third standard data. It is determined that the simulation verification result of the FPGA to be verified is normal.

[0149] In this way, based on the first output data, the second output data and the third output data, combined with their respective corresponding expected standard data, the simulation verification results of the FPGA to be verified are obtained. Not only the FPGA logic development program is simulated, but also the upstream hardware interface and the downstream hardware interface are simulated, so that the simulation verification results are more consistent with the results tested on the actual physical device, thereby improving the accuracy of FPGA simulation verification.

[0150] Optionally, when determining the simulation verification result of the FPGA to be verified, the simulation verification result of the FPGA to be verified can also be obtained based on the fourth output data and its corresponding expected standard data. If the fourth output data is inconsistent with its corresponding fourth standard data, the simulation verification result of the FPGA to be verified is determined to be abnormal.

[0151] Further, in the embodiment of the present application, after determining that the simulation verification result of the FPGA to be verified is abnormal, the abnormal problem of the FPGA to be verified can be determined based on the saved debugging information or simulation waveform. Figure 14 As shown in FIG, it is a flow chart of determining abnormal problems of the FPGA to be verified in the embodiment of the present application. Figure 14 , describe the specific operations in detail:

[0152] Step 1400: If the simulation verification result indicates that the virtual uplink interface is abnormal, then based on the saved first debugging information corresponding to the virtual uplink interface, determine the abnormal problem related to the virtual uplink interface.

[0153] In the embodiment of the present application, when the simulation verification result indicates that the virtual uplink interface is abnormal, the first debugging information corresponding to the stored virtual uplink interface is analyzed to determine the abnormal problem related to the virtual uplink interface.

[0154] Among them, the first debugging information can be the attribute information of the data received and the attribute information of the data sent by the virtual uplink interface. The attribute information of the data at least includes: data volume, data type, data status, etc., which is not limited in the embodiments of the present application.

[0155] Step 1401: If the simulation verification result indicates that the target logic function is abnormal, the abnormal problem in the target logic function is determined based on the simulation waveform diagram saved by the FPGA simulation tool.

[0156] In an embodiment of the present application, when the simulation verification result indicates that the target logic function is abnormal, the simulation waveform diagram saved by the FPGA simulation tool is analyzed to determine the abnormal problem in the target logic function.

[0157] Among them, when the first output data is input into the FPGA simulation tool and the second output data output after the FPGA simulation tool uses the logic dynamic link library for processing is obtained, the FPGA simulation tool will generate a simulation waveform diagram and save the simulation waveform diagram.

[0158] Step 1402: If the simulation verification result indicates that the virtual downstream interface is abnormal, the abnormal problem related to the virtual downstream interface is determined based on the saved second debugging information corresponding to the virtual upstream interface.

[0159] In the embodiment of the present application, when the simulation verification result indicates that the virtual downstream interface is abnormal, the second debugging information corresponding to the stored virtual downstream interface is analyzed to determine the abnormal problem related to the virtual upstream interface.

[0160] Among them, the second debugging information can be the attribute information of the data received and the attribute information of the data sent by the virtual downstream interface. The attribute information of the data at least includes: data volume, data type, data status, etc., which is not limited in the embodiments of the present application.

[0161] In this way, after determining that the simulation verification result of the FPGA to be verified is abnormal, the debugging information in the development process is enriched based on the saved first debugging information, second debugging information and simulation waveform diagram, which is conducive to faster positioning and solving abnormal problems in the development process.

[0162] Based on the above embodiments, the FPGA simulation verification method in the embodiments of the present application is described in detail using specific examples. Figure 15 The following is an example diagram of FPGA simulation verification in the embodiment of the present application, specifically including:

[0163] Assume that the device to be installed of the FPGA to be verified is an FPGA network card, the uplink hardware interface of the FPGA network card is an Ethernet interface, and the downlink hardware interface is a PCIE interface. The IXIA instrument is used to construct test data, and the test data is 10 UDP packets and 20 ARP packets. The target logic function of the FPGA to be verified is to filter ARP packets. The first standard data corresponding to the first output data is 10 UDP packets and 20 ARP packets, the second standard data corresponding to the second output data is 10 UDP packets, and the third standard data corresponding to the third output data is 10 UDP packets.

[0164] First, call the IXIA instrument to construct test data, input the test data into the virtual Ethernet interface through the physical network port, receive the first output data output by the virtual Ethernet interface, and save the first debugging information corresponding to the virtual Ethernet interface. The first output data is 10 UDP packets and 20 ARP packets.

[0165] Secondly, compile the logic development program of the FPGA to be verified, obtain the logic dynamic link library corresponding to the logic development program, call the FPGA simulation tool to load the logic dynamic link library, input the first output data into the FPGA simulation tool, obtain the second output data output by the FPGA simulation tool after processing using the logic dynamic link library, and save the generated simulation waveform. The second output data is 10 UDP packets.

[0166] Then, the second output data is input to the virtual PCIE interface, and the third output data output by the virtual PCIE interface is received, and the second debugging information corresponding to the virtual PCIE interface is saved, where the third output data is 5 UDP packets.

[0167] Finally, the first output data is consistent with its corresponding first standard data, the second output data is consistent with its corresponding second standard data, and the third output data is inconsistent with its corresponding third standard data, and the simulation verification result of the FPGA to be verified is determined to be abnormal.

[0168] The simulation verification result indicates that the virtual PCIE interface is abnormal. Based on the second debugging information corresponding to the virtual PCIE interface, the abnormal problem related to the virtual PCIE interface is determined.

[0169] Based on the same inventive concept, an FPGA simulation verification device is also provided in the embodiment of the present application. Figure 16 FIG. 1 is a schematic diagram of the structure of the FPGA simulation verification device in an embodiment of the present application, which specifically includes:

[0170] A first processing module 1601 is configured to input test data into a virtual uplink interface and receive first output data output by the virtual uplink interface, wherein the virtual uplink interface is obtained by virtualizing an uplink hardware interface of a target physical device, and the target physical device is a device to be installed in the FPGA to be verified;

[0171] A second processing module 1602 is configured to input the first output data into an FPGA simulation module for data processing, and receive second output data output by the FPGA simulation module, wherein the FPGA simulation module simulates the target logic function of the FPGA to be verified;

[0172] A third processing module 1603 is configured to input the second output data to a virtual downstream interface and receive third output data output by the virtual downstream interface, wherein the virtual downstream interface is obtained by virtualizing a downstream hardware interface of a target physical device;

[0173] The generating module 1604 is configured to obtain a simulation verification result of the FPGA to be verified based on the first output data, the second output data, and the third output data in combination with their corresponding expected standard data.

[0174] Optionally, before inputting the test data into the virtual uplink interface, the apparatus further includes a pre-processing module 1605, which is configured to:

[0175] Abstracting the physical resources of the uplink hardware interface of the target physical device into corresponding first logical resources, and generating a virtual uplink interface corresponding to the uplink hardware interface based on the first logical resources;

[0176] The physical resources of the downstream hardware interface of the target physical device are abstracted into corresponding second logical resources, and a virtual downstream interface corresponding to the downstream hardware interface is generated based on the second logical resources.

[0177] Optionally, when inputting the test data into the virtual uplink interface, the first processing module 1601 is further configured to:

[0178] Determine the physical interface for transmitting the test data based on the attribute information of the virtual uplink interface;

[0179] Forward test data through the physical interface to the virtual uplink interface.

[0180] Optionally, when the first output data is input to the FPGA simulation module for data processing and the second output data output by the FPGA simulation module is received, the second processing module 1602 is further configured to:

[0181] Compile the logic development program of the FPGA to be verified to obtain the logic dynamic link library corresponding to the logic development program;

[0182] Call the FPGA simulation tool to load the logic dynamic link library;

[0183] The first output data is input into an FPGA simulation tool to obtain second output data output after being processed by the FPGA simulation tool using a logic dynamic link library.

[0184] Optionally, when obtaining a simulation verification result of the FPGA to be verified based on the first output data, the second output data, and the third output data in combination with their respective corresponding expected standard data, the generating module 1604 is further configured to:

[0185] If the first output data, the second output data, and the third output data satisfy at least one of the following conditions, the simulation verification result of the FPGA to be verified is determined to be abnormal:

[0186] The first output data is inconsistent with the first standard data corresponding to it;

[0187] The second output data is inconsistent with the corresponding second standard data;

[0188] The third output data is inconsistent with its corresponding third standard data.

[0189] Optionally, after determining that the simulation verification result of the FPGA to be verified is abnormal, the apparatus further includes a determination module, and the determination module 1606 is configured to:

[0190] If the simulation verification result indicates that the virtual uplink interface is abnormal, determining the abnormal problem related to the virtual uplink interface based on the saved first debugging information corresponding to the virtual uplink interface;

[0191] If the simulation verification results indicate that the target logic function is abnormal, the abnormal problem in the target logic function is determined based on the simulation waveform diagram saved by the FPGA simulation tool;

[0192] If the simulation verification result indicates that the virtual downstream interface is abnormal, the abnormal problem related to the virtual downstream interface is determined based on the saved second debugging information corresponding to the virtual upstream interface.

[0193] Based on the above embodiments, see Figure 17 Shown is a schematic structural diagram of an electronic device in an embodiment of the present application.

[0194] An embodiment of the present application provides an electronic device, which may include a processor 1710 (Center Processing Unit, CPU), a memory 1720, an input device 1730 and an output device 1740, etc. The input device 1730 may include a keyboard, a mouse, a touch screen, etc., and the output device 1740 may include a display device, such as a liquid crystal display (LCD), a cathode ray tube (CRT), etc.

[0195] The memory 1720 may include a read-only memory (ROM) and a random access memory (RAM), and provides program instructions and data stored in the memory 1720 to the processor 1710. In the embodiment of the present application, the memory 1720 may be used to store the program of any one of the FPGA simulation verification methods in the embodiment of the present application.

[0196] The processor 1710 calls the program instructions stored in the memory 1720, and the processor 1710 is used to execute any FPGA simulation verification method in the embodiments of the present application according to the obtained program instructions.

[0197] Based on the above embodiments, in an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the FPGA simulation verification method in any of the above method embodiments is implemented.

[0198] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0199] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0200] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0201] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0202] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A field programmable gate array (FPGA) simulation verification method, characterized in that: include: Inputting test data into a virtual uplink interface and receiving first output data output by the virtual uplink interface, wherein the virtual uplink interface is obtained by virtualizing an uplink hardware interface of a target physical device, the target physical device being a device to be installed in the FPGA to be verified; Inputting the first output data into an FPGA simulation module for data processing, and receiving second output data output by the FPGA simulation module, wherein the FPGA simulation module simulates a target logic function of the FPGA to be verified; inputting the second output data into a virtual downstream interface, and receiving third output data output by the virtual downstream interface, wherein the virtual downstream interface is obtained by virtualizing a downstream hardware interface of the target physical device; Based on the first output data, the second output data, and the third output data, in combination with their respective corresponding expected standard data, a simulation verification result of the FPGA to be verified is obtained.

2. The method according to claim 1, wherein Before inputting the test data into the virtual uplink interface, the method further includes: Abstracting the physical resources of the uplink hardware interface of the target physical device into corresponding first logical resources, and generating a virtual uplink interface corresponding to the uplink hardware interface based on the first logical resources; The physical resources of the downstream hardware interface of the target physical device are abstracted into corresponding second logical resources, and a virtual downstream interface corresponding to the downstream hardware interface is generated based on the second logical resources.

3. The method according to claim 1, wherein Inputting the test data into the virtual uplink interface includes: Determine the physical interface for transmitting the test data based on the attribute information of the virtual uplink interface; The test data is forwarded to the virtual uplink interface through the physical interface.

4. The method according to any one of claims 1 to 3, wherein Inputting the first output data into the FPGA simulation module for data processing, and receiving the second output data output by the FPGA simulation module, includes: Compiling the logic development program of the FPGA to be verified to obtain a logic dynamic link library corresponding to the logic development program; Calling an FPGA simulation tool to load the logic dynamic link library; The first output data is input into the FPGA simulation tool to obtain second output data output by the FPGA simulation tool after being processed by the logic dynamic link library.

5. The method according to claim 4, wherein The obtaining, based on the first output data, the second output data, and the third output data, in combination with their respective corresponding expected standard data, a simulation verification result of the FPGA to be verified, includes: If the first output data, the second output data, and the third output data satisfy at least one of the following conditions, it is determined that the simulation verification result of the FPGA to be verified is abnormal: The first output data is inconsistent with its corresponding first standard data; The second output data is inconsistent with its corresponding second standard data; The third output data is inconsistent with its corresponding third standard data.

6. The method according to claim 5, wherein After determining that the simulation verification result of the FPGA to be verified is abnormal, the method further includes: If the simulation verification result indicates that the virtual uplink interface is abnormal, determining the abnormal problem related to the virtual uplink interface based on the saved first debugging information corresponding to the virtual uplink interface; If the simulation verification result indicates that the target logic function is abnormal, determining the abnormal problem in the target logic function based on the simulation waveform diagram saved by the FPGA simulation tool; If the simulation verification result indicates that the virtual downstream interface is abnormal, the abnormal problem related to the virtual downstream interface is determined based on the saved second debugging information corresponding to the virtual upstream interface.

7. An FPGA simulation verification device, characterized in that: include: a first processing module, configured to input test data into a virtual uplink interface and receive first output data output by the virtual uplink interface, wherein the virtual uplink interface is obtained by virtualizing an uplink hardware interface of a target physical device, the target physical device being a device to be installed in the FPGA to be verified; a second processing module, configured to input the first output data into an FPGA simulation module for data processing, and receive second output data output by the FPGA simulation module, wherein the FPGA simulation module simulates a target logic function of the FPGA to be verified; a third processing module, configured to input the second output data into a virtual downstream interface and receive third output data output by the virtual downstream interface, wherein the virtual downstream interface is obtained by virtualizing a downstream hardware interface of the target physical device; A generation module is used to obtain a simulation verification result of the FPGA to be verified based on the first output data, the second output data and the third output data in combination with their respective corresponding expected standard data.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The method comprises a computer program stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the electronic device performs the steps of the method according to any one of claims 1 to 6.

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