A transaction-based digital logic simulation system

Abstract

The application discloses a transaction-based data logic simulation system, which comprises an upper computer and a digital logic simulation device; wherein the upper computer is coupled with the digital logic simulation device and is used to send a design under test (DUT) and a simulation instruction to the digital logic simulation device; the digital logic simulation device receives and loads the design under test and receives the simulation instruction, generates simulation excitation data based on the simulation instruction, applies the simulation excitation data to the design under test to obtain a simulation result, compares the simulation result with a preset simulation result to obtain a comparison result, and sends the comparison result to the upper computer. The application solves the technical problem of low digital logic simulation efficiency in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital logic simulation, and in particular to a transaction-based digital logic simulation system. BACKGROUND

[0002] FPGA simulation verification is a necessary step for FPGA design testing and is one of the effective means to ensure the quality of FPGA design. With the increasing complexity of system design, the scale and design complexity of programmable logic gate array (FPGA) devices grow rapidly. In particular, for large-scale FPGA logic design, the simulation running time is long and the efficiency is low, especially in the later stage of design, when the circuit scale is large and the simulation scenarios are numerous. Using traditional software simulation will consume several hours, days or even weeks of time, thereby greatly prolonging the test period and relatively increasing the research and development cost, and ultimately reducing the market competitiveness of the product. Therefore, simulation acceleration technology for FPGA design has emerged. At present, simulation acceleration mainly uses hardware acceleration, which has two implementation methods, namely, an FPGA-based acceleration method and a method based on a special acceleration computing structure. The method based on a special acceleration computing structure requires the design of a special computing structure, which has high research and development and experimental costs. There are corresponding products that have applied professional integrated circuits for verification, but the price is high and the scalability is not strong, and they are often applied to large-scale integrated circuit research and development with sufficient funds. Since FPGA design is flexible and can be reconfigured, the FPGA-based acceleration method mainly uses an FPGA software and hardware co-simulation system to simulate the FPGA, which has low research and development and experimental costs and strong scalability, and is suitable for small-scale professional integrated circuit research and development or FPGA design verification.

[0003] The existing FPGA software and hardware co-simulation system mainly includes a software system part set in the user's PC end and a hardware system part for simulating the integrated circuit chip. In the FPGA simulation test process, the software system part is used to generate test excitation signals and read back simulation results for result determination, and the hardware system part is used to test the measured FPGA design and obtain test data. The existing FPGA software and hardware co-simulation system based on signals has limited data transmission bandwidth between the software and hardware when simulating a type of design to be measured that has large data transmission requirements or a special interface. If the amount of excitation / result data to be transmitted is huge, or the excitation data that can be generated more conveniently in the FPGA is generated by the upper computer, the simulation speed will inevitably be slowed down, thereby resulting in poor simulation acceleration effect. SUMMARY

[0004] The technical problem solved by the present application is: in view of the low efficiency of digital logic simulation in the prior art, the present application provides a transaction-based digital logic simulation system. In the scheme provided by the present application, the digital logic simulation device simulates the simulation excitation data without generating simulation excitation data on the host computer. This shortens the simulation excitation data generation time, reduces the data transmission pressure between the host computer and the digital logic simulation device, and improves the simulation efficiency.

[0005] In a first aspect, the present application provides a transaction-based digital logic simulation system, which comprises: a host computer and a digital logic simulation device; wherein the host computer is coupled to the digital logic simulation device and is configured to send a design under test (DUT) and a simulation instruction to the digital logic simulation device; the digital logic simulation device is configured to receive and load the DUT and receive the simulation instruction, generate simulation excitation data based on the simulation instruction, apply the simulation excitation data to the DUT to obtain a simulation result, compare the simulation result with a preset simulation result to obtain a comparison result, and send the comparison result to the host computer.

[0006] Optionally, the digital logic simulation device comprises a master FPGA and a slave FPGA; wherein the master FPGA is coupled to the host computer and is configured to receive the DUT and the simulation instruction sent by the host computer, send the DUT to the slave FPGA, generate the simulation excitation data according to the simulation instruction, and send the simulation excitation data to the slave FPGA; the slave FPGA is configured to receive and load the DUT and receive the simulation excitation data, apply the simulation excitation data to the DUT to obtain a simulation result, and send the simulation result to the master FPGA; the master FPGA is further configured to receive the simulation result sent by the slave FPGA, compare the simulation result with a preset ideal simulation result to obtain a comparison result, and send the comparison result to the host computer.

[0007] Optionally, before the master FPGA generates the simulation excitation data according to the simulation instruction, the master FPGA further receives a DUT excitation file sent by the host computer; after the master FPGA receives the simulation instruction, the master FPGA extracts excitation information of the DUT from the excitation file, and generates the simulation excitation data according to the simulation instruction and the excitation information.

[0008] Optionally, the master FPGA comprises a simulation excitation generation module, a result comparison module, a first communication module and a slave FPGA configuration module, wherein the simulation excitation generation module is configured to generate the simulation excitation data according to the simulation instruction; the first communication module is configured to receive the design under test sent by the host computer, send the design under test to the slave FPGA, and send the simulation excitation data to the slave FPGA and receive the simulation result sent by the slave FPGA; the result comparison module is configured to compare the simulation result with a preset ideal simulation result to obtain a comparison result; and the slave FPGA configuration module is configured to send the cached design under test to the slave FPGA after the slave FPGA is initialized, so that the slave FPGA loads the design under test.

[0009] Optionally, the slave FPGA comprises a design under test module, a design under test control module, a cache module and a second communication module, wherein the design under test module is configured to receive and load the design under test after the slave FPGA is initialized; the design under test control module is configured to control the working state of the design under test simulation clock, the data read-write of the design under test interface and the data cache; the cache module is configured to cache the simulation excitation data and the simulation result; and the second communication module is coupled with the first communication module and configured to receive the simulation excitation data from the master FPGA and send the simulation result to the master FPGA.

[0010] Optionally, the first communication module and the second communication module are both GTX communication modules.

[0011] Optionally, the digital logic simulation device further comprises a third communication module, wherein the third communication module is coupled with the host computer and the master FPGA, and is configured to realize data interaction between the host computer and the master FPGA.

[0012] Optionally, the third communication module is a PCIe communication module or a USB communication module.

[0013] Compared with the prior art, the application has at least the following beneficial effects:

[0014] (1) In the scheme provided by the embodiment of the application, the simulation excitation data is simulated by the digital logic simulation device, without the need to generate simulation excitation data on the host computer, which shortens the simulation excitation data generation time and also relieves the data transmission pressure between the host computer and the digital logic simulation device.

[0015] (2) The scheme provided by the embodiment of the present application uses FPGA to compare simulation results, which is faster than using simulation software to observe waveforms.

[0016] (3) In the scheme provided by the embodiment of the present application, the excitation and results required by the function and port to be simulated are edited into a file in advance, and are sent to the master FPGA before simulation starts. The host computer only needs to select the function or port to be simulated and send a simulation instruction, and all work is completed by the FPGA. The simulation conclusion is clear at a glance, and the operation is simple and easy to use. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A structure diagram of a transaction-based digital logic simulation system provided by an embodiment of the present application is shown.

[0018] Figure 2 A structure diagram of a digital logic simulation device provided by an embodiment of the present application is shown.

[0019] Figure 3 A structure diagram of a master FPGA provided by an embodiment of the present application is shown.

[0020] Figure 4 A structure diagram of a slave FPGA provided by an embodiment of the present application is shown.

[0021] Figure 5 Another structure diagram of a transaction-based digital logic simulation system provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] The scheme provided by the embodiment of the present application is only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the scope of protection of the present application.

[0023] In order to better understand the above technical solutions, the technical solutions of the present application will be described in detail below through the drawings and specific embodiments. It should be understood that the specific features of the embodiments of the present application and the embodiments are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0024] Figure 1 A structure diagram of a transaction-based digital logic simulation system provided by an embodiment of the present application is shown.

[0025] As an example, in the case of Figure 1In the digital logic simulation system 100, the host computer 101 is coupled to the digital logic simulation device 102, and is configured to send a design under test (DUT) and a simulation instruction to the digital logic simulation device 102. The host computer 101 can be a computer, a terminal, a client, or any device capable of sending control instructions or commands. The DUT can be a port or a function of an FPGA, and in the scheme provided in the embodiments of the present application, the DUT can be set according to actual testing requirements, which is not limited herein. The simulation instruction can be information indicating a port or a function to be simulated, for example, the port or the function is a port or a function of an FPGA; the simulation instruction is used to instruct the digital logic simulation device 102 to simulate the port or the function to be simulated according to the indication of the simulation instruction to obtain a simulation result. For example, the host computer 101 receives actual transaction (e.g., actual things to be done or things done) information of a user, and generates a simulation instruction based on the requirement information.

[0026] Continuing to refer to Figure 1 Before receiving the simulation instruction, the digital logic simulation device 102 needs to load a file related to the DUT, which includes but is not limited to an excitation file of the DUT and a result file. As an example, a user compiles an excitation file of a DUT to be tested and a preset simulation result file in advance, and sends the excitation file and the preset simulation result file to the digital logic simulation device 102 through the host computer 101. The excitation file is used to control the generation of simulation excitation data; and the preset simulation result file is used to indicate a preset simulation result or to generate a preset simulation result. As another example, the host computer 101 also needs to send the DUT to the digital logic simulation device 102, for example, in the form of a bit stream file, and the digital logic simulation device 102 receives and loads the DUT.

[0027] Further, the digital logic simulation device 102 receives the simulation instruction, generates simulation excitation data based on the simulation instruction, applies the simulation excitation data to the DUT to obtain a simulation result, compares the simulation result with a preset simulation result to obtain a comparison result, and sends the comparison result to the host computer 101, so that the host computer 101 verifies the DUT based on the comparison result.

[0028] In the scheme provided in the embodiments of the present application, the simulation excitation data is generated by the digital logic simulation device, without the need to generate the simulation excitation data on the host computer, which shortens the simulation excitation data generation time, and also relieves the data transmission pressure between the host computer and the digital logic simulation device.

[0029] Figure 2A structural schematic diagram of a digital logic simulation device provided by an embodiment of the application is shown.

[0030] For example, in Figure 2 The digital logic simulation device 102 includes a master FPGA 1021 and a slave FPGA 1022. The master FPGA 1021 is coupled to the host computer 101, receives the design under test and the simulation instruction sent by the host computer 101, sends the design under test to the slave FPGA 1022, generates simulation stimulus data according to the simulation instruction, and sends the simulation stimulus data to the slave FPGA 1022. The slave FPGA 1022 receives and loads the design under test, receives the simulation stimulus data, and applies the simulation stimulus data to the design under test to obtain a simulation result, and sends the simulation result to the master FPGA 1021. The master FPGA 1021 also receives the simulation result sent by the slave FPGA 1022, compares the simulation result with a preset ideal simulation result to obtain a comparison result, and sends the comparison result to the host computer 101.

[0031] For another example, the digital logic simulation device 102 further includes a memory, which is located inside or outside the digital logic simulation device 102, and is used to store data required by the master FPGA 1021 or generated data, such as simulation stimulus data, simulation results, and comparison results. For example, the memory is a DDR3. For example, the master FPGA 1021 receives the simulation instruction, generates corresponding simulation stimulus data according to the simulation instruction, and pre-caches the simulation stimulus data in the memory or sends the simulation stimulus data to the slave FPGA 1022 in real time for simulation of the design under test. The master FPGA 1021 also receives the simulation data obtained after the simulation of the slave FPGA 1022 is completed, analyzes the simulation data by comparison with a preset simulation result to obtain a final simulation conclusion (comparison result), and sends the comparison result to the host computer 101.

[0032] In the scheme provided by the embodiment of the application, the FPGA is used to compare simulation results, and compared with the waveform observation mode using simulation software, the discrimination speed is faster, and the result discrimination is more objective, accurate, and clear.

[0033] In addition, the master FPGA 1021 completes the configuration loading of the slave FPGA 1022 before the simulation starts, and sends the design under test to the slave FPGA 1022, so that the slave FPGA 1022 can load the design under test. For example, the host computer 101 downloads the stimulus file and the preset simulation result file about the design under test edited by the user in advance to the master FPGA 1021, so as to control the generation of the simulation stimulus and the generation of the simulation result; the design under test is transmitted between the master FPGA 1021 and the slave FPGA 1022 in the form of a bit stream file (such as a binary bit data file). The host computer 101 also sends, for example, the stimulus file, the preset simulation result file and the design under test of the design under test to the master FPGA 1021 in response to receiving the simulation instruction or before receiving the simulation instruction (such as after initialization), and controls the master FPGA 1021 to complete the automatic loading of the slave FPGA 1022. After the simulation is completed, the master FPGA 1021 completes the comparison of the simulation result, and sends the simulation conclusion of the correct or incorrect simulation result to the host computer 101.

[0034] In the scheme provided by the embodiment of the application, the stimulus and the preset simulation result required by the design under test (such as the function or port of the FPGA) are edited into files in advance, and are sent to the master FPGA before the simulation starts. The host computer 101 only needs to select the function or port required for the simulation, and sends the simulation instruction, and all the work is completed by the FPGA, and the simulation conclusion is obvious at a glance, and the operation is simple and easy to use.

[0035] As an example, the host computer 101 generates the simulation instruction, and sends the stimulus file, the preset simulation result file and the design under test of the design under test to the master FPGA 1021, which is realized by software. That is, in the scheme provided by the embodiment of the application, the simulation and verification of the FPGA port or function are realized by combining the software (the host computer software) with the hardware (the digital logic simulation device 102). For example, the host computer 101 is programmed by using System Verilog, sends the simulation instruction, the stimulus file, the simulation result file and the design under test according to the corresponding bit sequence, and receives the comparison result. The interface module of the host computer 101 is programmed by using C language, and completes the encapsulation and function scheduling of the sub-functions such as the DMA reading or DMA writing, the register reading, the register writing and the like, and the program of the memory direct access (Direct Memory Access, DMA) through the PCIe XDMA channel or the USB GPIF II channel; in addition, the host computer 101 can control the design under test to be sent to the master FPGA 1021 before running the simulation, and loaded into the slave FPGA 1022 through the master FPGA 1021, so as to realize the automatic loading of the design under test. For example, when the initialization of the slave FPGA 1022 is completed, the design under test is obtained and loaded.

[0036] For the convenience of understanding, the structure and functions of the main FPGA are briefly introduced in the form of examples.

[0037] Figure 3 A structure diagram of a main FPGA provided by the embodiment of the application is shown.

[0038] For example, in the main FPGA 1021, the simulation excitation generation module 301, the result comparison module 302, the first communication module 303 and the slave FPGA configuration module 304 are included. Figure 3 The simulation excitation generation module 301 is used to generate simulation excitation data according to simulation instructions; the first communication module 303 is used to receive the design under test sent by the host computer 101, send the design under test to the slave FPGA 1022, and send the simulation excitation data to the slave FPGA 1022 and receive the simulation result sent by the slave FPGA 1022; and the result comparison module 302 is used to compare the simulation result with the preset ideal simulation result to obtain a comparison result.

[0039] For example, the functions of the modules in the main FPGA 1021 are as follows:

[0040] I. Simulation excitation generation module 301

[0041] When the main FPGA receives the simulation instructions transmitted by the host computer, the simulation excitation generation module 301 correctly extracts the simulation requirements of the user, finds the simulation excitation generation strategy in the excitation file and the preset simulation result file of the design under test edited by the user in advance according to the simulation requirements transmitted by the host computer, and the simulation excitation generation strategy includes the generation mode of the simulation excitation data and the use mode of the simulation excitation. For example, the simulation excitation data includes control signals, interface protocols, communication data, image data and video data, and the generation of the simulation excitation data includes the following cases:

[0042] 1. The control signals can be directly generated by the simulation excitation generation module 301.

[0043] 2. The interface protocol can be generated by using the existing protocol by giving relevant parameters.

[0044] 3. The communication data can be pre-stored in the memory and read by the simulation excitation generation module 301, and some can also use the IP core of the main FPGA to generate such data.

[0045] 4. The image and video data can be pre-stored in the memory and read by the simulation excitation generation module 301.

[0046] Further, after the simulation excitation data is generated, the use of the simulation excitation data is also involved. As an example, the use of the simulation excitation data includes the following modes:

[0047] 1) Real-time use: after the simulation excitation data is generated, the simulation excitation data is directly sent into the slave FPGA through the first communication module 303 between the master FPGA and the slave FPGA, and the simulation of the design under test is performed.

[0048] 2) Storage and use at a proper time: after the simulation excitation data is generated, the simulation excitation data is first sent into a specified address of a memory corresponding to the master FPGA, and when the simulation excitation data needs to be used, a read control signal is sent through the first communication module 303, the master FPGA reads the simulation excitation data in the corresponding address of the memory and sends the simulation excitation data into the slave FPGA, and the simulation of the design under test is performed.

[0049] II. Result comparison module 302

[0050] When the slave FPGA starts to return the simulation result data, the preset simulation result data is read at the same time, and the preset simulation result is compared with the simulation result returned by the slave FPGA. If the two results are consistent, the comparison result signal is configured as a high level, and if the two results are inconsistent, the comparison result signal is configured as a low level. Finally, the comparison result is uploaded to the host computer.

[0051] III. First communication module 303

[0052] As an example, the first communication module is a GTX communication module. The IP core of the Aurora protocol provided by Xilinx is mainly based on a GTX transmitter as a physical layer, forms a link layer function according to the protocol, and realizes user data interaction with the sending end and the receiving end through an AXI4_Stream protocol interface. The scheme provided in the embodiment of the application realizes high-speed optical fiber communication through the Aurora 64B / 66B IP provided by Xilinx, the channel rate reaches 10.3125 Gb / s, and the full-duplex mode is completed.

[0053] IV. Slave FPGA configuration module 304

[0054] As an example, the host computer completes the logic configuration of the slave FPGA through the PCIe or USB interface from the FPGA configuration module 304. The host computer stores the design file in the memory (such as DDR3) through the PCIe or USB, and then transmits the data. The slave FPGA configuration module 304 mainly includes configuration state detection and data buffering functions. Through the configuration interface connected with the slave FPGA, when the master FPGA receives the slave FPGA configuration instruction sent by the host computer, the slave FPGA configuration signal (such as the PROGRAM_B signal) is sent through the interface of the slave FPGA configuration signal, the slave FPGA initialization is waited to be completed, and the slave FPGA configuration bit stream file (such as the above to-be-tested design) of the memory is sent to the slave FPGA to complete the configuration of the slave FPGA. In addition, through the state interface connected with the slave FPGA, the control of the entire slave FPGA configuration process is responsible, the writing of the slave FPGA configuration program is completed, the design file stored in the memory (such as DDR3) is read out and buffered, because the data bit width of the memory reading and writing is 256 bits, and the data bit width of the slave FPGA configuration Slave Select MAP 16 mode is 16 bits, therefore, in order to match the data bit widths of the two, the 256-bit data needs to be converted into 16-bit data.

[0055] In addition, the master FPGA 1021 further includes an expected result generation logic module 305. The master FPGA receives the simulation instruction transmitted by the host computer, correctly extracts the simulation requirement of the user, according to the simulation requirement, searches and reads the preset simulation result from the excitation file and the preset simulation result of the to-be-tested design edited by the user in advance and transmitted by the host computer, and sends the preset simulation result into, for example, a first input first output (FIFO) for buffering, and waits for the simulation result data returned by the slave FPGA unit.

[0056] Figure 4 A structural schematic diagram of the slave FPGA provided by the embodiment of the application is shown.

[0057] The slave FPGA is not connected with the memory (such as the flash memory), therefore, before starting the simulation, the host computer writes the bit stream file of the to-be-tested design into the master FPGA 1021 through the PCIe or USB DMA writing mode, and then the master FPGA 1021 configures the slave FPGA 1022 through the slave select map mode to complete the automatic loading of the slave FPGA 1022 configuration stream.

[0058] As an example, in the slave FPGA configuration module 304, Figure 4From the FPGA 1022, the modules include a design-under-test module 401, a design-under-test control module 402, a cache module 403, and a second communication module 404. The design-under-test module 401 is configured to receive and load the design-under-test after initialization of the slave FPGA 1022 is completed. The design-under-test control module 402 is configured to control the working state of the design-under-test simulation clock, the data read / write of the design-under-test interface, and the data cache. The cache module 403 is configured to cache the simulation stimulus data and the simulation result. The second communication module 404 is coupled with the first communication module 303, and is configured to receive the simulation stimulus data from the master FPGA 1021 and send the simulation result to the master FPGA 1021.

[0059] As an example, the functions of the modules in the slave FPGA 1022 are as follows:

[0060] The design-under-test module 401 is configured to load the design-under-test (e.g., a design-under-test module or a design-under-test function), load the design-under-test engineering that needs to be simulated and accelerated into the slave FPGA 1022, and generate a bit file after synthesis and placement and routing. Before simulation starts, the host computer first sends the design-under-test into the master FPGA 1021, so that the master FPGA 1021 automatically configures the slave FPGA 1022, and then the hardware simulation test of the design-under-test can be performed.

[0061] The design-under-test control module 402 is configured to complete the working scheduling of the slave FPGA 1022, mainly control the working state of the design-under-test simulation clock and control the read / write of the design-under-test interface data, cache the simulation stimulus data, and output the simulation stimulus data to the design-under-test. The design-under-test control module 402 is also configured to cache the test data output by the design-under-test, and send the test data to the master FPGA 1021 through the second communication module 404.

[0062] The cache module 403 includes a simulation stimulus data cache and a result data cache. The simulation stimulus data cache is configured to cache the simulation stimulus data. The result data cache is configured to cache the simulation result.

[0063] The second communication module 404 is a GTX communication module, and has the same function as the GTX communication module in the master FPGA.

[0064] Figure 5 FIG. 6 shows a structure schematic diagram of another transaction-based digital logic simulation system provided by an embodiment of the present application.

[0065] Referring to Figure 5The digital logic simulation device 102 further comprises a third communication module 1023, wherein the third communication module 1023 is coupled with the host computer 101 and the main FPGA 1021, and is configured to perform data interaction between the host computer 101 and the main FPGA 1021. For example, the third communication module 1023 is configured to transmit and communicate simulation instructions, simulation conclusions, excitation files of the design under test, preset simulation result files, and the design under test. In order to increase the flexibility and ease of use of the system in the scheme provided by the embodiments of the present application, for example, the host computer 101 and the main FPGA 1021 have two communication modes, one is PCIe communication, and the other is USB3.0 communication. The function of the USB3.0 high-speed data communication is similar to the PCIe XDMA communication function, and the user can select to use the PCIe XDMA or USB3.0 GPIF II communication mode to communicate with the main FPGA 1021 according to the actual test requirements.

[0066] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer usable program codes.

[0067] The present application is described with reference to flowcharts and / or block diagrams according to the methods, devices (systems), and computer program products of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more flows and / or blocks.

[0068] These computer program instructions can also be stored in a computer readable storage medium that can guide the computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer readable storage medium produce a product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more flows and / or blocks.

[0069] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable data processing devices provide processes for implementing the functions specified in the flowchart Figure 1 one or more flows and / or blocks Figure 1 one or more flows and / or blocks

[0070] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A transaction-based digital logic simulation system, characterized by, The application relates to a digital logic simulation device and a host computer. The host computer is coupled with the digital logic simulation device and is used for sending a design under test (DUT) and simulation instructions to the digital logic simulation device. The digital logic simulation device receives and loads the design under test and receives the simulation instructions, generates simulation excitation data based on the simulation instructions, applies the simulation excitation data to the design under test to obtain simulation results, compares the simulation results with preset simulation results to obtain comparison results, and sends the comparison results to the host computer. The digital logic simulation device comprises a master FPGA and a slave FPGA. The master FPGA is coupled with the host computer, receives the design under test and the simulation instructions sent by the host computer, sends the design under test to the slave FPGA, generates the simulation excitation data according to the simulation instructions, and sends the simulation excitation data to the slave FPGA. The slave FPGA receives and loads the design under test, receives the simulation excitation data, applies the simulation excitation data to the design under test to obtain simulation results, and sends the simulation results to the master FPGA. The master FPGA also receives the simulation results sent by the slave FPGA, compares the simulation results with preset ideal simulation results to obtain comparison results, and sends the comparison results to the host computer. Before the master FPGA generates the simulation excitation data according to the simulation instructions, the master FPGA also receives an excitation file of the design under test sent by the host computer.

2. The system of claim 1, wherein, After the master FPGA receives the simulation instructions, the master FPGA extracts excitation information of the design under test from the excitation file, generates the simulation excitation data according to the simulation instructions and the excitation information. The master FPGA comprises a simulation excitation generation module, a result comparison module, a first communication module and a slave FPGA configuration module. The simulation excitation generation module is used for generating the simulation excitation data according to the simulation instructions.

3. The system of claim 2, wherein, The first communication module is used for receiving the design under test sent by the host computer, sending the design under test to the slave FPGA, sending the simulation excitation data to the slave FPGA, and receiving the simulation results sent by the slave FPGA. The result comparison module is used for comparing the simulation results with preset ideal simulation results to obtain comparison results. The slave FPGA configuration module is used for sending the buffered design under test to the slave FPGA after the slave FPGA is initialized, so that the slave FPGA loads the design under test. The slave FPGA comprises a design under test module, a design under test control module, a buffer module and a second communication module. The design under test module is used for receiving and loading the design under test after the slave FPGA is initialized.

4. The system of claim 3, wherein, The design under test control module is used for controlling the working state of a design under test simulation clock, the data read-write of a design under test interface and data buffering. ​ ​ The cache module is configured to cache the simulation excitation data and the simulation result. The second communication module is coupled with the first communication module, and is configured to receive the simulation excitation data from the main FPGA and send the simulation result to the main FPGA.

5. The system of claim 4, wherein, The first communication module and the second communication module are both GTX communication modules.

6. The system of any one of claims 1 to 5, wherein, The digital logic simulation device further comprises a third communication module, wherein the third communication module is coupled with the host computer and the main FPGA, and is configured to interact data between the host computer and the main FPGA.

7. The system of claim 6, wherein, The third communication module is a PCIe communication module or a USB communication module.

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