Pixel circuit, driving method thereof and display panel

Abstract

Embodiments of the present application provide a pixel circuit, a driving method thereof and a display panel, and relate to the technical field of display panels. The pixel circuit comprises a driving module configured to drive a light emitting element to emit light, a first end of the driving module being connected to a power supply signal; a storage module configured to store a target voltage signal; a first switch module, a first end of the first switch module being electrically connected to the storage module, and a second end of the first switch module being electrically connected to a second end of the driving module. In a bias stage or a target voltage signal writing stage before the bias stage, the storage module stores the target voltage signal. In the bias stage before a data writing stage, the first switch module is turned on, and the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module. According to the embodiments of the present application, the flickering phenomenon of the display panel during low-frequency display can be improved, and the picture display effect can be improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display panels, and particularly relates to a pixel circuit, a driving method thereof, and a display panel. BACKGROUND

[0002] At present, with the continuous development of AMOLED (Active-matrix organic light-emitting diode) display technology, the functions of AMOLED display panels are continuously updated, and different display modes are used in different working scenarios. Generally, in the locked state, the AMOLED display panel enters the Always On Display (AOD) mode, which can reduce the current consumption in the standby state to improve the battery life.

[0003] After the AMOLED display panel enters the AOD display mode, the power consumption of the display panel or the integrated circuit can be effectively reduced by using the adaptive refresh rate technology. However, during the process of reducing the refresh rate, the gate voltage of the driving thin film transistor (DTFT) in the internal pixel circuit is always in a constant voltage state, which causes the threshold voltage to be in a bias state for a long time, thereby affecting the driving current flowing into the organic light-emitting diode (OLED), and further affecting the display state of the display panel, so that the display panel appears a low-frequency flicker phenomenon. SUMMARY

[0004] The embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel, which can be beneficial to improve the flicker phenomenon of the display panel during low-frequency display and improve the picture display effect.

[0005] In a first aspect, the embodiments of the present application provide a pixel circuit, which comprises:

[0006] A driving module is configured to drive a light-emitting element to emit light, and a first end of the driving module is connected to a power supply signal.

[0007] A storage module is configured to store a target voltage signal.

[0008] A first switch module has a first end electrically connected to the storage module and a second end electrically connected to a second end of the driving module.

[0009] In a bias phase or a target voltage signal writing phase located before the bias phase, the storage module stores the target voltage signal.

[0010] In the biasing phase before the data writing phase, the first switch module is turned on, and the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

[0011] In a possible implementation of the first aspect, the pixel circuit further includes a second switch module; a control end of the second switch module is electrically connected with the first scan signal line; a first end of the second switch module is electrically connected with the storage module; and a second end of the second switch module is electrically connected with the first reference voltage signal end; in the biasing phase or in a target voltage signal writing phase before the biasing phase, the second switch module is turned on under the control of the first scan signal line, and the target voltage signal provided by the first reference voltage signal end is transmitted to the storage module.

[0012] In a possible implementation of the first aspect, a first end of the storage module is electrically connected with a control end of the driving module, and a second end of the storage module is electrically connected with the first power voltage signal end; a first end of the second switch module is electrically connected with the first end of the storage module and the control end of the driving module; in an initialization phase after the biasing phase, the second switch module is turned on under the control of the first scan signal line, and the first reference voltage signal provided by the first reference voltage signal end is transmitted to the control end of the driving module, so as to initialize the control end of the driving module.

[0013] In a possible implementation of the first aspect, the voltage value of the target voltage signal is different from the voltage value of the first reference voltage signal.

[0014] In a possible implementation of the first aspect, the voltage value of the target voltage signal is greater than the voltage value of the first reference voltage signal.

[0015] In a possible implementation of the first aspect, a control end of the driving module is electrically connected with a first end of the first switch module, and the pixel circuit further includes a data writing module; a control end of the data writing module is electrically connected with a second scan signal line; a first end of the data writing module is electrically connected with a data signal end; and a second end of the data writing module is electrically connected with a first end of the driving module; a control end of the first switch module is electrically connected with a third scan signal line; in a data writing phase after the biasing phase, the data writing module is turned on under the control of the second scan signal line, and the first switch module is turned on under the control of the third scan signal line, so as to transmit the data signal of the data signal end to the first end of the driving module.

[0016] In a possible implementation of the first aspect, a control end of the first switch module is electrically connected with a third scan signal line, and the waveforms of the scan signals output by the first scan signal line and the third scan signal line connected with the same pixel circuit are the same, and the phases are different by a preset interval.

[0017] In a possible implementation manner of the first aspect, the first scan signal line connected to the pixel circuit of the i-1th row and the third scan signal line connected to the pixel circuit of the i th row output the same waveform and the same phase of the scan signal.

[0018] In a possible implementation manner of the first aspect, the first scan signal line connected to the pixel circuit of the i-1th row and the third scan signal line connected to the pixel circuit of the i th row are electrically connected to the output terminal of the same shift register, and i is a positive integer.

[0019] In a possible implementation manner of the first aspect, one picture display period includes a refresh frame and a holding frame, the control end of the driving module is refreshed in the refresh frame, and the control end of the driving module is not refreshed in the holding frame; the refresh frame and the holding frame include a bias stage.

[0020] In a possible implementation manner of the first aspect, one picture display period includes one refresh frame and N holding frames, N is a positive integer, and the refresh frame and the N holding frames each include a bias stage.

[0021] In a possible implementation manner of the first aspect, the first switch module and the second switch module each include an oxide thin film transistor.

[0022] In a possible implementation manner of the first aspect, the first switch module and the second switch module each include an N-type transistor.

[0023] Based on the same inventive concept, in a second aspect, the embodiments of the present application provide a driving method of a pixel circuit, applied to the pixel circuit provided in any of the foregoing implementation manners of the first aspect of the present application, and the driving method of the pixel circuit includes: storing a target voltage signal in the storage module in a bias stage or a target signal writing stage located before the bias stage; and controlling the first switch module to be turned on in the bias stage before a data writing stage, so that the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

[0024] In a possible implementation manner of the second aspect, the pixel circuit further includes a second switch module, and the driving method of the pixel circuit further includes: controlling the first scan signal line to output the on level of the second switch module in the bias stage or a target voltage signal writing stage located before the bias stage, so that the second switch module is turned on, and the target voltage signal provided by the first reference voltage signal end is transmitted to the storage module.

[0025] Based on the same inventive concept, in a third aspect, the embodiments of the present application provide a display panel, which includes the pixel circuit provided in any of the foregoing implementation manners of the first aspect of the present application.

[0026] Based on the same inventive concept, in a fourth aspect, an embodiment of the present application provides a display device, which includes a display panel provided in the implementation of the third aspect of the present application.

[0027] An embodiment of the present application provides a pixel circuit, a driving method thereof, and a display panel. A driving module, a storage module, and a first switch module are provided in the pixel circuit. The first end of the first switch module is electrically connected to the storage module, and the second end is electrically connected to the second end of the driving module. In a bias stage or a target voltage signal writing stage before the bias stage, the target voltage signal is stored by the storage module. In a bias stage before data is written into the module, the target voltage signal stored in the storage module is transmitted to the second end of the driving module through the first switch module. Without adding an additional bias voltage writing transistor, the bias state of the driving module can be adjusted by the target voltage signal, thereby adjusting the threshold voltage of the driving module, improving the flickering phenomenon that occurs when the display panel displays at low frequencies, and improving the picture display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 A circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0030] Figure 2 Another circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0031] Figure 3 Another circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0032] Figure 4 Another circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0033] Figure 5 Another circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0034] Figure 6 Another circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0035] Figure 7 for Figure 6 A timing diagram of the pixel circuit shown;

[0036] Figure 8 Another circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0037] Figure 9 For Figure 8 Another timing diagram of the pixel circuit shown in FIG. 8A is shown in FIG. 8B.

[0038] Figure 10 For Figure 8 Another timing diagram of the pixel circuit shown in FIG. 8A is shown in FIG. 8B.

[0039] Figure 11 A flow diagram of a driving method of the pixel circuit provided by the embodiments of the present application is shown in FIG. 9.

[0040] Figure 12 A structural diagram of a display panel provided by the embodiments of the present application is shown in FIG. 10.

[0041] Figure 13 A structural diagram of a display device provided by the embodiments of the present application is shown in FIG. 11. DETAILED DESCRIPTION

[0042] The features and exemplary embodiments of various aspects of the present application will be described below in detail, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0043] It should be noted that, in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0044] It should be understood that the term "and / or" used herein is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects have an "or" relationship.

[0045] It should be noted that the transistor in the embodiments of the present application can be an N-type transistor or a P-type transistor. For the N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is high, the first electrode and the second electrode of the N-type transistor are on, and when the gate of the N-type transistor is low, the first electrode and the second electrode of the N-type transistor are off. For the P-type transistor, the on level is low and the off level is high. That is, when the control electrode of the P-type transistor is low, the first electrode and the second electrode of the P-type transistor are on, and when the control electrode of the P-type transistor is high, the first electrode and the second electrode of the P-type transistor are off. In the specific implementation, the gate of each transistor is used as the control electrode thereof, and according to the signal of the gate of each transistor and the type of the transistor, the first electrode can be used as the source electrode and the second electrode can be used as the drain electrode, or the first electrode can be used as the drain electrode and the second electrode can be used as the source electrode, which is not distinguished herein. In addition, the on level and the off level in the embodiments of the present application are generic, the on level refers to any level that can make the transistor on, and the off level refers to any level that can make the transistor off.

[0046] In the embodiments of the present application, the term "electrically connected" can refer to that two components are directly electrically connected, or that two components are electrically connected via one or more other components.

[0047] In the embodiments of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not an actual circuit unit.

[0048] Various modifications and changes can be made to the present application in light of the foregoing without departing from the spirit or scope of the present application, which is defined in the appended claims (the technical solutions claimed to be protected). Therefore, the present application is intended to cover the same within the spirit and scope of the appended claims and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction.

[0049] Before the technical solutions provided by the embodiments of the present application are described, the problems existing in the related art are first described in detail to facilitate the understanding of the embodiments of the present application:

[0050] The inventor has found that when the AMOLED display panel displays at a low frequency, the number of frames displayed per second of the display panel decreases, and accordingly, to prolong the light-emitting time of the organic light-emitting diode in each frame, the gate voltage of the driving transistor in the pixel circuit often needs to be in a constant voltage state for a long time, the leakage time of the gate of the driving transistor is prolonged, thereby causing the threshold voltage of the driving transistor to also be in a bias state for a long time.

[0051] Thus, the threshold voltage of the driving transistor is biased for a long time, causing the driving current of the driving transistor to drive the organic light emitting diode to emit light to be unstable, thereby affecting the display state of the display panel and causing the display panel to flicker during low-frequency display.

[0052] In view of the above research findings of the inventors, in order to solve the problems of the prior art, the embodiments of the present application provide a pixel circuit and a driving method thereof, and a display panel.

[0053] Figure 1 A circuit diagram of a pixel circuit provided in an embodiment of the present application. Figure 1 As shown, the pixel circuit 10 may specifically include a driving module 101, a storage module 102, and a first switch module 103. A first end of the first switch module 103 may be electrically connected to the storage module 102, and a second end of the first switch module 103 may be electrically connected to a second end of the driving module 101. The second end of the driving module 101 may be understood as an output end of the driving current of the driving module 101. For example, the driving module 101 may be a transistor, and the second end of the driving module 101 may specifically be a drain (or source) of the transistor.

[0054] In the present application, the above-mentioned driving module 101 can be used to drive the light-emitting element to emit light. In the bias stage or the target voltage signal writing stage before the bias stage, the target voltage signal is stored by the above-mentioned storage module 102. In the bias stage before the data writing stage of the pixel circuit 10, the first switch module 103 is turned on, and the target voltage signal in the storage module 102 is transmitted to the second end of the driving module 101 through the first switch module 103, so as to adjust the bias state of the driving module 101 by writing the target voltage signal. For example, by writing the target voltage signal to the second end of the driving module 101 through the turned-on first switch module, the voltage difference between the potential of the second end of the driving module 101 and the potential of the control end of the driving module 101 can be reduced, or even tend to be consistent, thereby improving the drift phenomenon of the threshold voltage Vth caused by the long-term constant voltage state of the control end of the driving module 101, and then improving the flickering phenomenon that occurs when the display panel displays at low frequency, thereby improving the picture display effect.

[0055] The pixel circuit provided by the embodiment of the present application comprises a driving module 101, a storage module 102 and a first switch module 103. The first end of the first switch module 103 is electrically connected with the storage module 102, and the second end is electrically connected with the second end of the driving module 101. In the bias stage or the target voltage signal writing stage before the bias stage, the target voltage signal is stored in the storage module 102. In the bias stage before the data writing, the target voltage signal stored in the storage module 102 is transmitted to the second end of the driving module 101 through the first switch module 103, without adding an additional bias voltage writing transistor, so that the bias state of the driving module 101 is adjusted through the target voltage signal, the threshold voltage of the driving module 101 is adjusted, the flicker phenomenon of the display panel in low-frequency display is improved, and the picture display effect is improved.

[0056] In some more specific embodiments, in order to more reasonably adjust the bias state of the driving module 101 to sufficiently improve the low-frequency flicker phenomenon of the display panel, the control end of the driving module 101 can be electrically connected with the first end of the first switch module 103. The voltage value of the target voltage signal is less than the sum of the voltage value of the power supply signal and the threshold voltage of the driving module 101, so as to ensure the effective conduction of the driving module 101. In this way, in the bias stage, the target voltage signal in the storage module 102 is transmitted to the second end of the driving module 101 through the conducting first switch module 103, the control end of the driving module 101 and the second end of the driving module 101 are connected through the conducting first switch module 103, the potential of the control end of the driving module 101 and the second end of the driving module 101 tends to be consistent, so as to effectively inhibit the threshold voltage drift phenomenon caused by the long-term constant voltage of the control end of the driving module 101, and further effectively improve the flicker phenomenon of the display panel in low-frequency display, and greatly improve the picture display effect.

[0057] Please refer to Figure 2 , Figure 2 Another circuit schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 3. As shown in FIG. 3, the pixel circuit comprises a driving module 101, a storage module 102 and a first switch module 103. The first end of the first switch module 103 is electrically connected with the storage module 102, and the second end is electrically connected with the second end of the driving module 101. In the bias stage or the target voltage signal writing stage before the bias stage, the target voltage signal is stored in the storage module 102. Figure 2As shown, in some embodiments, the bias signal voltage can be stored in the storage capacitor 102 in advance or at the same time as the target voltage signal is written, so as to achieve the writing of the target voltage signal to the second terminal of the driving module 101 during the bias phase. Optionally, the pixel circuit 10 may further include a second switch module 104, wherein the control terminal of the second switch module 104 is electrically connected to the first scan signal line S1, the first terminal of the second switch module 104 is electrically connected to the storage module 102, and the second terminal of the second switch module 104 is electrically connected to the first reference voltage signal terminal vref1. During the bias phase or during the target voltage signal writing phase preceding the bias phase, the second switch module 104 is turned on under the control of the first scan signal line S1, and transmits the target voltage signal provided by the first reference voltage signal terminal vref1 to the storage module 102.

[0058] In some embodiments, when the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the storage module 102 during a target voltage signal writing phase preceding the bias phase, the first switch module 103 may be turned off, and the second switch module 104 may be turned on in response to the on-level provided by the first scan signal line S1. The target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the storage module 102 via the turned-on second switch module 104. In this way, the storage module 102 stores the target voltage signal, and can therefore write the target voltage signal to the second terminal of the driver module 101 via the turned-on first switch module 103 during a subsequent bias phase.

[0059] In other embodiments, when the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the storage module 102 during the bias phase of the pixel circuit of the present application, the first switch module 103 is turned on by a corresponding control signal, and the second switch module 104 is turned on in response to the on-level provided by the first scan signal line S1. At this time, the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the storage module 102 via the turned-on second switch module 104 and stored as the target voltage signal in the storage module 102.

[0060] In this way, in the bias stage or in the target voltage signal writing stage before the bias stage, the target voltage signal provided by the first reference voltage signal terminal vref1 is stored in the storage module 102 through the conductive second switch module 104, so that the stored target voltage signal is written to the second end of the driving module 101 in the bias stage, thereby effectively achieving an improvement in the low-frequency flicker phenomenon of the display panel.

[0061] See below Figure 3 , Figure 3 This is another circuit diagram of a pixel circuit provided in an embodiment of the present application. Figure 3As shown, considering that there may be residual charges at the control terminal of the driving module 101, the data writing process in the data writing stage of the pixel circuit may be adversely affected.

[0062] Therefore, in order to fully guarantee the picture display effect of the display panel, in some embodiments, the first end of the storage module 102 can also be electrically connected to the control terminal of the driving module 101, and the second end of the storage module 102 can be connected to the first power voltage signal end ELVDD. The first end of the second switch module 104 can be electrically connected to the first end of the storage module 102 and the control terminal of the driving module 101, and the second end of the second switch module 104 can be electrically connected to the first reference voltage signal end vref1. It should be noted that the power signal connected to the first end of the driving module 101 can be provided by the first power voltage signal end ELVDD, but in other embodiments, it can also be provided by other power voltage signal ends, which are not limited in the present application.

[0063] In the initialization stage after the bias stage, the second switch module 104 is turned on in response to the on level provided by the first scan signal line S1, and the first reference voltage signal provided by the first reference voltage signal end vref1 can be transmitted to the control terminal of the driving module 101 through the turned-on second switch module 104, to realize the initialization of the control terminal of the driving module 101. When the driving module 101 is a driving transistor, the control terminal of the driving module 101 can be the gate of the driving transistor.

[0064] In some embodiments, considering the actual flashing screen condition of the display panel and the timing requirements of different stages in each frame, the voltage value of the target voltage signal can be different from that of the first reference voltage signal. Further, in some embodiments, the present inventors have found that the target voltage signal is actually used to adjust the bias state of the driving module 101 in the bias stage, and the first reference voltage signal is actually used to initialize the control terminal of the driving module 101 in the initialization stage after the bias stage, to solve the discharge of residual charges at the control terminal of the driving module 101 and guarantee the full conduction of the driving module 101. Based on this, in order to realize the reasonable use of the voltage signal, the voltage value of the target voltage signal can be greater than that of the first reference voltage signal.

[0065] Please refer to Figure 4 , Figure 4Another circuit schematic of the pixel circuit provided by the embodiment of the present application is provided. In some embodiments, on the basis of the above scheme, the control terminal of the driving module 101 is electrically connected with the first terminal of the first switch module 103, and the pixel circuit 10 can further include a data writing module 105, the control terminal of the data writing module 105 is electrically connected with the second scan signal line S2, the first terminal of the data writing module 105 is electrically connected with the data signal terminal data, and the second terminal of the data writing module 105 is electrically connected with the first terminal of the driving module 101.

[0066] In the data writing stage after the bias stage, the data writing module 105 is turned on in response to the turn-on level provided by the second scan signal line S2. In this way, the data signal of the data signal terminal can be transmitted to the first terminal of the driving module 101 through the turned-on data writing module 105.

[0067] Please refer to Figure 5 , Figure 5 Another circuit schematic of the pixel circuit provided by the embodiment of the present application is provided. In some more specific embodiments, on the basis of the above scheme, optionally, the control terminal of the first switch module 103 can be electrically connected with the third scan signal line S3.

[0068] Specifically, in the above data writing stage after the bias stage, the data writing module 105 is turned on under the control of the second scan signal line, the first switch module 103 is turned on in response to the turn-on level provided by the third scan signal line S3, and the control terminal of the driving module 101 is in communication with the second terminal of the driving module 101. Meanwhile, the data signal of the data signal terminal data is written into the first terminal of the driving module 101, and the first terminal and the control terminal of the driving module 101 exist a potential difference at this time and are thus turned on. In this way, the data signal of the data signal terminal data is written into the control terminal of the driving module 101 through the turned-on data writing module 105, the turned-on driving module 101 and the turned-on first switch module 103, and at the same time, the threshold voltage compensation of the driving module 101 is realized.

[0069] In some embodiments, in order to realize the reasonable setting of each scan signal line connected with the pixel circuit, the control terminal of the first switch module 103 is electrically connected with the third scan signal line S3. The waveforms of the scan signals output by the first scan signal line S1 and the third scan signal line S3 connected with the same pixel circuit 10 can be the same, and the phases are different by a preset interval. Exemplarily, the waveforms of the scan signals output by the first scan signal line S1 and the third scan signal line S3 can be different by a phase corresponding to half a period.

[0070] In some more specific embodiments, in order to facilitate reasonable multiplexing of the scanning signals, the first scanning signal line S1 connected to the (i-1)th row of pixel circuits and the third scanning signal line S3 connected to the ith row of pixel circuits output scanning signals with the same waveform and the same phase.

[0071] In some more specific embodiments, considering that the lighting mode of the pixel circuits in the display panel is row-by-row lighting, based on this, in combination with the specific working timing of the pixel circuits, in order to further improve the reasonable utilization of the scanning signal lines of the pixel circuits in the display panel, the first scanning signal line S1 connected to the (i-1)th row of pixel circuits and the third scanning signal line S3 connected to the ith row of pixel circuits can be electrically connected to the output end of the same shift register, i being a positive integer.

[0072] That is, in the present application, the scanning signals output by the first scanning signal line of the ith row and the third scanning signal line of the (i-1)th row in the display panel can be provided by the same shift register. In this way, the reasonable multiplexing of each shift register in the display panel is achieved, effectively simplifying the wiring complexity of the pixel circuits in the display panel.

[0073] In some embodiments, considering the actual application scenario of the display panel, one frame display period can include a refresh frame and a holding frame. The control end of the driving module 101 is refreshed during the refresh frame, and the control end of the driving module 101 is not refreshed during the holding frame. In order to fully guarantee the picture display effect, the above-mentioned refresh frame and holding frame can each include a bias stage.

[0074] In some more specific embodiments, one frame display period of the display panel can specifically include 1 refresh frame and N holding frames, N being a positive integer. In this frame display period, the refresh frame and the N holding frames can each include the above-mentioned bias stage, which can effectively improve the display effect of the display panel in each frame and avoid flickering of the display panel.

[0075] In some embodiments, on the basis of the above-mentioned scheme, considering that the off-state leakage current of the oxide transistor is small, in order to achieve full blocking of the first switch module 103 and the second switch module 104, the first switch module 103 and the second switch module 104 can each include an oxide thin film transistor.

[0076] When the first switch module 103 and the second switch module 104 are both oxide transistors, they can be fully turned off under the control of the scanning signal line cutoff level, which can reduce the leakage path of the control end of the driving module 101 and effectively reduce the potential change amplitude of the corresponding node of the control end of the driving module 101, so that the driving current generated by the subsequent driving module 101 is more accurate.

[0077] Further, in some more specific embodiments, the first switch module 103 and the second switch module 104 can each include an N-type transistor. When the first switch module 103 and the second switch module 104 are each an N-type transistor, the on level of the first scan signal line S1 is high, and the off level is low. The on level of the second scan signal line S2 is high, and the off level is low.

[0078] In order to facilitate understanding of the pixel circuit provided in the present application, the following will be described in combination with some specific application embodiments.

[0079] Please refer to Figure 6 , Figure 6 Another circuit schematic diagram of the pixel circuit provided in the embodiments of the present application is shown. As shown in Figure 6 , according to some embodiments of the present application, optionally, in the pixel circuit 10 provided in the embodiments, the driving module 101 can be a P-type driving transistor T1, the storage module 102 can be a storage capacitor Cst, the first switch module 103 can be an N-type transistor T3, the second switch module 104 can be an N-type transistor T4, and the data writing module 105 can be a P-type transistor T2. The first end of the transistor T3 can be electrically connected with the storage module Cst, and the second end of the transistor T3 can be electrically connected with the second end of the driving transistor T1. The control end of the transistor T4 is electrically connected with the first scan signal line S1, the first end of the transistor T4 is electrically connected with the first end of the storage module Cst, the first end of the transistor T4 is also electrically connected with the control end of the driving transistor T1, and the second end of the transistor T4 is electrically connected with the first reference voltage signal end vref1. The first end of the storage module Cst can also be electrically connected with the control end of the driving transistor T1, and the second end of the storage module Cst can be connected with the first power voltage signal end ELVDD. The control end of the transistor T2 is electrically connected with the second scan signal line S2, the first end of the transistor T2 is electrically connected with the data signal end data, and the second end of the transistor T2 is electrically connected with the first end of the driving transistor T1. The control end of the transistor T3 can be electrically connected with the third scan signal line S3. The power signal inputted into the first end of the driving transistor T1 can be provided by the first power voltage signal end ELVDD or by another power voltage signal end, which is not limited in the present application.

[0080] Figure 7 For Figure 6 , a timing diagram of the pixel circuit is shown. The following will introduce the pixel circuit shown in Figure 7 in combination with the timing shown in Figure 6 , Figure 6The working process of the pixel circuit in the target voltage signal writing stage t0, the bias stage t1, the initialization stage t2 and the data writing stage t3.

[0081] In the target voltage signal writing stage t0, the first scan signal line S1 provides a conduction level, the second scan signal line S2 provides a cutoff level, and the third scan signal line S3 provides a cutoff level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is cut off under the control of the second scan signal line S2, and the transistor T3 is cut off under the control of the third scan signal line S3. The target voltage signal provided by the first reference voltage signal end vref1 is transmitted to the storage capacitor Cst through the turned-on transistor T4, and the storage capacitor Cst thus stores the target voltage signal.

[0082] In the bias stage t1, the first scan signal line S1 provides a cutoff level, the second scan signal line S2 provides a cutoff level, and the third scan signal line S3 provides a conduction level. The transistor T4 is cut off under the control of the first scan signal line S1, the transistor T2 is cut off under the control of the second scan signal line S2, and the transistor T3 is turned on under the control of the third scan signal line S3. The target voltage signal stored in the storage capacitor Cst is transmitted to the second end of the driving transistor T1 through the turned-on transistor T3, so as to adjust the bias state of the driving transistor T1. The second end of the driving transistor T1 can be understood as the output end of the driving current of the driving transistor T1.

[0083] In the initialization stage t2, the first scan signal line S1 provides a conduction level, the second scan signal line S2 provides a cutoff level, and the third scan signal line S3 provides a cutoff level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is cut off under the control of the second scan signal line S2, and the transistor T3 is cut off under the control of the third scan signal line S3. The first reference voltage signal provided by the first reference voltage signal end vref1 is transmitted to the control end of the driving transistor T1 through the turned-on transistor T4, so as to initialize the control end of the driving transistor T1. The control end of the driving transistor T1 can be specifically the gate of the driving transistor. The voltage value of the above-mentioned target voltage signal is less than the sum of the voltage value of the power signal and the threshold voltage of the driving transistor T1.

[0084] In the data writing stage t3, the first scan signal line S1 provides a cut-off level, the second scan signal line S2 provides a turn-on level, and the third scan signal line S3 provides a turn-on level. The transistor T4 is cut off under the control of the first scan signal line S1, the transistor T2 is turned on under the control of the second scan signal line S2, and the transistor T3 is turned on under the control of the third scan signal line S3. The data signal of the data signal terminal data is written into the first end of the driving transistor T1 through the transistor T2, and the control end of the driving transistor T1 is in communication with the second end of the driving transistor T1 through the turned-on transistor T3. The first end and the control end of the driving transistor T1 are turned on due to the existence of a potential difference. In this way, the data signal of the data signal terminal data is finally written into the control end of the driving transistor T1 through the turned-on transistor T2, the turned-on driving transistor T1, and the turned-on transistor T3.

[0085] The pixel circuit provided by the embodiment of the present application adds the bias voltage writing stage and the bias stage by changing the timing of the pixel circuit, stores the target voltage signal through the storage module, and transmits the target voltage signal stored by the storage module to the second end of the driving module through the first switch module in the bias stage, so that the bias state of the driving module can be adjusted through the target voltage signal without adding an additional bias voltage writing transistor. The pixel circuit can effectively improve the flicker phenomenon of the display panel in low-frequency display and improve the display effect of the picture without increasing the cost of elements.

[0086] It should be noted that, in addition to the above-mentioned transistors, the pixel circuit 10 can also include other transistors, which together constitute various types of pixel circuits. That is, the embodiment of the present application can be applied to various types of pixel circuits such as 7T1C, 7T2C, or 9T1C.

[0087] For ease of understanding, the following will be described by taking a 7T1C pixel circuit as an example.

[0088] Figure 8 Another circuit schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, in the pixel circuit 10 provided by the embodiment of the present application, in addition to the above-mentioned transistors, the pixel circuit 10 can also include other transistors, which together constitute various types of pixel circuits. Figure 8 The pixel circuit provided by the embodiment of the present application adds the bias voltage writing stage and the bias stage by changing the timing of the pixel circuit, stores the target voltage signal through the storage module, and transmits the target voltage signal stored by the storage module to the second end of the driving module through the first switch module in the bias stage, so that the bias state of the driving module can be adjusted through the target voltage signal without adding an additional bias voltage writing transistor. The pixel circuit can effectively improve the flicker phenomenon of the display panel in low-frequency display and improve the display effect of the picture without increasing the cost of elements. Figure 6In addition to the structure shown in , the pixel circuit 10 further includes a transistor T5 (P-type), a transistor T6 (P-type), a transistor T7 (P-type), and an organic light emitting diode OLED. A first terminal of the transistor T5 is electrically connected to the first power supply voltage signal terminal ELVDD, a control terminal of the transistor T5 is electrically connected to the emission control signal terminal EM, a second terminal of the transistor T5 is electrically connected to the first terminal of the driving transistor T1, a first terminal of the transistor T6 is electrically connected to the second terminal of the driving transistor T1, a control terminal of the transistor T6 is electrically connected to the emission control signal terminal EM, a second terminal of the transistor T6 is electrically connected to the anode of the OLED, and the cathode of the OLED is electrically connected to the ground voltage signal terminal ELVSS. A first terminal of the transistor T7 is electrically connected to the anode of the OLED, a control terminal of the transistor T7 is electrically connected to the fourth scan signal line S4, and a second terminal of the transistor T7 is electrically connected to the second reference voltage signal terminal vref2. The power signal connected to the first terminal of the driving transistor T1 can be provided by the first power supply voltage signal terminal ELVDD.

[0089] Figure 9 for Figure 8 A timing diagram of the pixel circuit shown in FIG. Figure 9 The timing shown is Figure 8 The 7T1C pixel circuit shown is introduced. Figure 8 The operation of the pixel circuit can be divided into a light-emitting phase and a non-light-emitting phase. In the non-light-emitting phase, the light-emitting control signal terminal EM outputs an off-level, transistors T5 and T6 are turned off under the control of the light-emitting control signal terminal EM, and the OLED does not emit light. In the light-emitting phase, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 all provide an off-level, the light-emitting control signal terminal EM outputs an on-level, and transistors T5 and T6 are turned on under the control of the light-emitting control signal terminal EM, driving the OLED to emit light.

[0090] The non-light-emitting phase may specifically include: a target voltage signal writing phase t0, a bias phase t1, an initialization phase t2, and a data writing phase t3.

[0091] In the target voltage signal writing stage t0, the first scan signal line S1 provides a conduction level, the second scan signal line S2 provides a cutoff level, the third scan signal line S3 provides a cutoff level, and the fourth scan signal line S4 provides a cutoff level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is cut off under the control of the second scan signal line S2, the transistor T3 is cut off under the control of the third scan signal line S3, and the transistor T7 is cut off under the control of the fourth scan signal line S4. The target voltage signal provided by the first reference voltage signal end vref1 is transmitted to the storage capacitor Cst through the turned-on transistor T4, and the storage capacitor Cst thus stores the target voltage signal.

[0092] In the biasing stage t1, the first scan signal line S1 provides a cutoff level, the second scan signal line S2 provides a cutoff level, the third scan signal line S3 provides a conduction level, and the fourth scan signal line S4 provides a cutoff level. The transistor T4 is cut off under the control of the first scan signal line S1, the transistor T2 is cut off under the control of the second scan signal line S2, the transistor T3 is turned on under the control of the third scan signal line S3, and the transistor T7 is cut off under the control of the fourth scan signal line S4. The target voltage signal stored in the storage capacitor Cst is transmitted to the second end of the driving transistor T1 through the turned-on transistor T3, so as to adjust the biasing state of the driving transistor T1. The second end of the driving transistor T1 can be understood as the output end of the driving current of the driving transistor T1, and the voltage value of the target voltage signal is less than the sum of the voltage of the power supply signal and the threshold voltage of the driving transistor.

[0093] In the initialization stage t2, the first scan signal line S1 provides a conduction level, the second scan signal line S2 provides a cutoff level, the third scan signal line S3 provides a cutoff level, and the fourth scan signal line S4 provides a cutoff level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is cut off under the control of the second scan signal line S2, the transistor T3 is cut off under the control of the third scan signal line S3, and the transistor T7 is cut off under the control of the fourth scan signal line S4. The first reference voltage signal provided by the first reference voltage signal end vref1 is transmitted to the control end of the driving transistor T1 through the turned-on transistor T4, so as to initialize the control end of the driving transistor T1. The control end of the driving transistor T1 can be specifically the gate of the driving transistor.

[0094] During data writing phase t3, the first scan signal line S1 provides a cutoff voltage level, the second scan signal line S2 provides a conduction voltage level, the third scan signal line S3 provides a conduction voltage level, and the fourth scan signal line S4 provides a conduction voltage level. Transistor T4 is cutoff under the control of the first scan signal line S1, transistor T2 is turned on under the control of the second scan signal line S2, transistor T3 is turned on under the control of the third scan signal line S3, and transistor T7 is turned on under the control of the fourth scan signal line S4. The data signal at the data signal terminal data is written to the first terminal of the driving transistor T1 via transistor T2. The control terminal of the driving transistor T1 is connected to the second terminal of the driving transistor T1 via the turned-on transistor T3. The first terminal and the control terminal of the driving transistor T1 are conductive due to the potential difference. Thus, the data signal at the data signal terminal data is ultimately written to the control terminal of the driving transistor T1 via the turned-on transistors T2, T1, and T3. The second reference voltage signal provided by the second reference voltage signal terminal vref2 is written to the OLED anode via the turned-on transistor T2, initializing the OLED anode.

[0095] For more specific examples, see Figure 10 , Figure 10 for Figure 8 Another timing diagram of the pixel circuit shown. Figure 10 , the operation timings of the pixel circuits in the i-1th row and the i-th row are shown in FIG.

[0096] from Figure 10 It can be seen that the waveforms and phases of the scanning signals output by the first scanning signal line S1 connected to the pixel circuit in the i-1th row and the third scanning signal line S3 connected to the pixel circuit in the i-th row are the same. Based on this, in this embodiment, Figure 10 Specifically, the first scanning signal line S1 connected to the pixel circuits in the (i-1)th row and the third scanning signal line S3 connected to the pixel circuits in the (i)th row may both be electrically connected to the output end of the same shift register.

[0097] In summary, the pixel circuit provided in the embodiments of the present application adds the aforementioned bias voltage write phase and bias phase by changing the pixel circuit timing. Based on the different signal outputs of the added phases, a target voltage signal is stored in a storage module. During the bias phase, the target voltage signal stored in the storage module is transmitted to the second end of the driver module via a first switch module. This eliminates the need for additional bias voltage write transistors, thereby enabling the bias state of the driver module to be adjusted via the target voltage signal. This pixel circuit can effectively improve the flickering phenomenon that occurs during low-frequency display on a display panel without increasing component costs, thereby enhancing the display quality.

[0098] Based on the same inventive concept, the present application also provides a driving method for a pixel circuit, which is applied to the pixel circuit 11 provided in any of the above embodiments of the present application. Figure 11 , Figure 11 A schematic flow chart of a driving method for a pixel circuit provided in an embodiment of the present application.

[0099] like Figure 11 As shown, the driving method of the pixel circuit includes:

[0100] S1110, storing the target voltage signal by a storage module in a biasing phase or in a target voltage signal writing phase before the biasing phase;

[0101] S1120 , in a bias phase before a data writing phase, controlling the first switch module to be turned on, so that the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

[0102] Exemplarily, during a biasing phase or a target voltage signal writing phase preceding the biasing phase, the target voltage signal is stored in the storage module. During the biasing phase preceding the data writing phase, the conduction of the first switch module can be controlled by controlling the output of a shift register corresponding to a scan signal terminal connected to the control terminal of the first switch module. Thus, when the first switch module is conducting, the target voltage signal in the storage module is transmitted to the second terminal of the driver module via the conducting first switch module, thereby resetting the second terminal of the driver module.

[0103] An embodiment of the present application provides a method for driving a pixel circuit. During a biasing phase, a first switch module is controlled to conduct, allowing a target voltage signal stored in a storage module within the pixel circuit to be transmitted to the second terminal of a driver module via the conducting first switch module. This method adjusts the bias state of the driver module using the target voltage signal, thereby adjusting the driver module's threshold voltage. This effectively mitigates flickering during low-frequency display on the display panel, enhancing the display quality.

[0104] In some possible implementations, in order to reasonably implement driving of the pixel circuit in the aforementioned embodiment, optionally, the pixel circuit may further include a second switch module; and the driving method of the pixel circuit may further include:

[0105] In the bias stage or in the target voltage signal writing stage before the bias stage, the first scanning signal line is controlled to output the conduction level of the second switch module so that the second switch module is turned on and the target voltage signal provided by the first reference voltage signal terminal is transmitted to the storage module.

[0106] Specifically, in the bias stage or in the target voltage signal writing stage located before the bias stage, the first scan signal line can be enabled to output the on level of the second switch module by controlling the output of the shift register connected with the first scan signal line. In this way, the second switch module is turned on in response to the on level of the first scan signal line, and the target voltage signal provided by the first reference voltage signal end is transmitted into the storage module through the turned-on second switch module, so as to transmit the target voltage signal stored in the storage module to the second end of the driving module in the bias stage.

[0107] Based on the pixel circuit provided in any of the above embodiments, the present application also provides a display panel including the pixel circuit 10 provided in the present application. Please refer to Figure 12 , Figure 12 FIG. 1 shows a structural schematic diagram of a display panel provided in an embodiment of the present application. As shown in FIG. 1, the display panel 100 provided in the embodiment of the present application can include the pixel circuit 10 provided in any of the above embodiments. Figure 12 The display panel shown in FIG. 1 can be an organic light-emitting diode (OLED) display panel. Figure 12

[0108] Those skilled in the art should understand that in other implementations of the present application, the display panel can also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0109] The display panel provided in the embodiment of the present application has the beneficial effects of the pixel circuit 10 provided in the embodiment of the present application. For specific details, please refer to the specific description of the pixel circuit 10 in the above embodiments, which will not be repeated here.

[0110] Based on the display panel provided in the above embodiments, the present application also provides a display device including the display panel provided in the present application. Please refer to Figure 13 , Figure 13 FIG. 10 shows a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 13 The display device 1000 provided in the embodiment includes the display panel 100 provided in any of the above embodiments of the present application. Figure 13 The display device 1000 is described by taking a mobile phone as an example in the embodiment. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, which are not specifically limited in the present application. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application. For specific details, please refer to the specific description of the display panel 100 in the above embodiments, which will not be repeated here. ​

[0111] It should be understood that the specific structure of the circuit and the structure of the display panel provided by the drawings of the embodiments of the present application are merely some examples and are not intended to limit the present application. In addition, the above-mentioned embodiments of the present application can be combined with each other without contradiction.

[0112] It should be noted that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts of each of the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In accordance with the above-described embodiments of the present application, these embodiments do not describe all the details and do not limit the application to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited by the claims and their entire scope and equivalents.

[0113] Those skilled in the art should understand that the above-mentioned embodiments are exemplary and not limiting. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art should understand and implement other changed embodiments of the disclosed embodiments based on the drawings, the specification and the claims. In the claims, the term "comprising" does not exclude other structures; the number of "one" does not exclude multiple; the terms "first", "second" are used to mark the name and not to represent any specific order. Any reference signs in the claims should not be understood as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A pixel circuit, characterized in that: include: A driving module, used to drive the light-emitting element to emit light, wherein a first end of the driving module is connected to a power signal; a storage module, wherein the storage module is used to store the target voltage signal; a first switch module, wherein a first end of the first switch module is electrically connected to the storage module, and a second end of the first switch module is electrically connected to the second end of the driving module; In a biasing phase or in a target voltage signal writing phase located before the biasing phase, the storage module stores the target voltage signal; In the bias phase before the data writing phase, the first switch module is turned on, and the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module; the pixel circuit further includes a second switch module; The control end of the second switch module is electrically connected to the first scan signal line, the first end of the second switch module is electrically connected to the storage module, and the second end of the second switch module is electrically connected to the first reference voltage signal end; In the biasing stage or in the target voltage signal writing stage before the biasing stage, the second switch module is turned on under the control of the first scanning signal line to transmit the target voltage signal provided by the first reference voltage signal terminal to the storage module; The first end of the storage module is electrically connected to the control end of the driving module, and the second end of the storage module is connected to the first power supply voltage signal end; The first end of the second switch module is electrically connected to the first end of the storage module and the control end of the driving module; In an initialization phase following the bias phase, the second switch module is turned on under the control of the first scan signal line, and transmits the first reference voltage signal provided by the first reference voltage signal terminal to the control terminal of the driving module, so as to initialize the control terminal of the driving module; A voltage value of the target voltage signal is greater than a voltage value of the first reference voltage signal.

2. The pixel circuit according to claim 1, wherein: The control end of the driving module is electrically connected to the first end of the first switch module, and the pixel circuit further includes a data writing module; The control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal end, and the second end of the data writing module is electrically connected to the first end of the driving module; The control end of the first switch module is electrically connected to the third scan signal line; In the data writing phase after the bias phase, the data writing module is turned on under the control of the second scanning signal line, and the first switching module is turned on under the control of the third scanning signal line to write the data signal of the data signal end to the control end of the driving module.

3. The pixel circuit according to claim 1, wherein: The control end of the first switch module is electrically connected to the third scanning signal line. The scanning signals output by the first scanning signal line and the third scanning signal line connected to the same pixel circuit have the same waveform and a phase difference of a preset interval.

4. The pixel circuit according to claim 3, wherein: The scanning signals output by the first scanning signal line connected to the pixel circuits in the (i-1)th row and the third scanning signal line connected to the pixel circuits in the i-th row have the same waveform and the same phase.

5. The pixel circuit according to claim 3, wherein: The first scanning signal line connected to the pixel circuits in the (i-1)th row and the third scanning signal line connected to the pixel circuits in the (i)th row are both electrically connected to the output end of the same shift register, where i is a positive integer.

6. The pixel circuit according to claim 1, wherein: One picture display cycle includes a refresh frame and a hold frame. During the refresh frame, the control end of the driving module is refreshed, and during the hold frame, the control end of the driving module is not refreshed. The refresh frame and the hold frame include the bias phase.

7. The pixel circuit according to claim 3, wherein: One picture display cycle includes one refresh frame and N hold frames, where N is a positive integer. Both the refresh frame and the N hold frames include the bias phase.

8. The pixel circuit according to claim 1, wherein: The first switch module and the second switch module both include oxide thin film transistors.

9. The pixel circuit according to claim 8, wherein: The first switch module and the second switch module both include N-type transistors.

10. A method for driving a pixel circuit, characterized in that: Applicable to the pixel circuit according to any one of claims 1 to 9; The driving method includes: In a biasing phase or in a target voltage signal writing phase located before the biasing phase, storing the target voltage signal by a storage module; In the bias phase before the data writing phase, the first switch module is controlled to be turned on so that the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module; the pixel circuit further includes a second switch module; The driving method further includes: In the biasing stage or in the target voltage signal writing stage before the biasing stage, the first scanning signal line is controlled to output the conduction level of the second switch module, so that the second switch module is turned on, and the target voltage signal provided by the first reference voltage signal terminal is transmitted to the storage module; the first terminal of the storage module is electrically connected to the control terminal of the driving module, and the second terminal of the storage module is connected to the first power supply voltage signal terminal; The first end of the second switch module is electrically connected to the first end of the storage module and the control end of the driving module; In an initialization phase following the bias phase, the second switch module is turned on under the control of the first scan signal line, and transmits the first reference voltage signal provided by the first reference voltage signal terminal to the control terminal of the driving module, so as to initialize the control terminal of the driving module; A voltage value of the target voltage signal is greater than a voltage value of the first reference voltage signal.

11. A display panel, characterized in that: The display panel comprises the pixel circuit according to any one of claims 1 to 9.

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