Method, apparatus, device and medium for automatically expanding a storage array

Abstract

Embodiments of the present disclosure relate to a method, apparatus, device, and medium for automatically expanding a storage array. The method includes: obtaining the total number of word lines of a target expanded storage array and the total number of bit lines of the target expanded storage array; calculating the translation amount of a translation array in the translation direction according to the total number of word lines, the total number of bit lines, the total number of word lines of the translation array, the total number of bit lines of the translation array, and a preset translation rule; calculating the number of replication times of a replication array in the replication direction according to the translation amount, the total number of word lines of the replication array, the total number of bit lines of the replication array, and a preset replication rule; controlling at least part of the translation array and at least part of the replication array to translate the translation amount along the translation direction, and controlling the replication array to replicate the number of replication times along the replication direction to obtain a target expanded storage array. The present disclosure avoids errors such as unclear boundaries or coordinate offsets during the process of manually expanding a storage array, and effectively improves the production efficiency and shipment quality of semiconductor storage products.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor manufacturing technologies, and in particular, to a method, device, equipment and medium for automatically expanding a storage array. Background Art

[0002] With the rapid development of integrated circuit manufacturing processes, the market has higher and higher requirements for the storage capacity of semiconductor storage products, and higher requirements for the production efficiency and shipping quality of semiconductor storage products.

[0003] Traditional storage arrays need to plan the shape and size of the storage array according to the requirements of the storage capacity and the basic storage unit structure, and then build the planned storage array according to the word line size and the bit line size. How to efficiently build the planned storage array has become one of the technical problems to be solved urgently in the process of further improving the production efficiency of semiconductor storage products. Summary of the Invention

[0004] The embodiments of the present disclosure provide a method, device, equipment and medium for automatically expanding a storage array, which can automatically and efficiently generate a target expanded storage array according to the required storage capacity, avoid errors such as unclear boundaries or coordinate offsets during the process of manually expanding the storage array, and effectively improve the production efficiency and shipping quality of semiconductor storage products.

[0005] According to some embodiments, one aspect of the present disclosure provides a method for automatically expanding a storage array, including: obtaining the total number of word lines of the target expanded storage array and the total number of bit lines of the target expanded storage array; calculating the translation amount of the translation array in the translation direction according to the total number of word lines, the total number of bit lines, the total number of word lines of the translation array, the total number of bit lines of the translation array, and a preset translation rule; calculating the number of replication times of the replication array in the replication direction according to the translation amount, the total number of word lines of the replication array, the total number of bit lines of the replication array, and a preset replication rule; controlling at least part of the translation array and at least part of the replication array to translate the translation amount along the translation direction, and controlling the replication array to replicate the number of replication times along the replication direction to obtain the target expanded storage array.

[0006] In the method for automatically expanding a storage array in the above embodiments, since in this embodiment, the target expanded storage array can be automatically generated according to the total number of word lines of the target expanded storage array, the total number of bit lines of the target expanded storage array, the total number of word lines of the translation array, and the total number of bit lines of the translation array, the target expanded storage array is automatically and efficiently generated according to the required storage capacity, avoiding errors such as unclear boundaries or coordinate offsets during the process of manually expanding the storage array, and effectively improving the production efficiency and shipping quality of semiconductor storage products.

[0007] In some embodiments, the translation array includes a first translation array defined to translate in a first direction, a second translation array defined to translate in a second direction, and a third translation array defined to translate in the first direction and the second direction; calculating the translation amount of the translation array in the translation direction includes: calculating a first-direction translation amount of the first translation array in the first direction according to the difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array; calculating a second-direction translation amount of the second translation array in the second direction according to the difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array; taking the vector sum of the first-direction translation amount and the second-direction translation amount as the third-direction translation amount of the third translation array, so as to control the first translation array and a partial repeating array to translate the first-direction translation amount in the first direction, control the second translation array and a partial repeating array to translate the second-direction translation amount in the second direction, and control the third translation array to translate the third-direction translation amount in the direction of the vector sum of the first direction and the second direction, so as to realize obtaining a target extended storage array including a blank area by translating at least a partial translation array and a partial repeating array, and thus be able to fill the blank area by copying the repeating array to obtain the target extended storage array.

[0008] In some embodiments, calculating the translation amount of the translation array in the translation direction further includes: determining the word line pitch and the bit line pitch of the storage array; wherein, the word line pitch is the average distance between two adjacent word lines, and the bit line pitch is the average distance between two adjacent bit lines; calculating the first-direction translation amount stretch_x and the second-direction translation amount stretch_y according to the following formula:

[0009] stretch_x = (Nbitline - Ncornerb) * bitline_pitch;

[0010] stretch_y = (Nwordline - Ncornerw) * wordline_pitch;

[0011] In the above formula, Nwordline is the total number of word lines of the target extended storage array, Ncornerw is the total number of word lines of the translation array, Nbitline is the total number of bit lines of the target extended storage array, Ncornerb is the total number of bit lines of the translation array, wordline_pitch is the word line pitch, and bitline_pitch is the bit line pitch.

[0012] In some embodiments, after controlling at least part of the translation array and at least part of the replication array to translate the translation amount along the translation direction, the replication array is controlled to replicate the replication times along the replication direction, so that after obtaining a target extended storage array including blank areas by translating at least part of the translation array and at least part of the replication array, the blank areas are filled by replicating the replication array to obtain the target extended storage array, avoiding errors such as boundary overlap or coordinate offset in the target extended storage array.

[0013] In some embodiments, the replication array includes a first replication array for replicating in the first direction, a second replication array for replicating in the second direction, and a third replication array for replicating in the direction of the vector sum of the first direction and the second direction; calculating the replication times of the replication array in the replication direction further includes: calculating a first replication times of the first replication array and the third replication array in the first direction according to the difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array; calculating a second replication times of the second replication array and the third replication array in the second direction according to the difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array. After obtaining a target extended storage array including blank areas by translating at least part of the translation array and at least part of the replication array, the replication times of the replication array are calculated according to the size of the blank areas and the size of the replication array, so as to achieve intelligent and accurate filling of the blank areas, avoiding errors such as boundary overlap or coordinate offset in the target extended storage array.

[0014] In some embodiments, calculating the first replication times and the second replication times further includes: determining the number of bit lines Nb in the first replication array and the number of word lines Nw in the second replication array; calculating the first replication times repetition_x and the second replication times repetition_y according to the following formula:

[0015] repetition_x = ((Nrbitline - Ncornerb) / Nb) - 1;

[0016] repetition_y = ((Nrwordline - Ncornerw) / Nw) - 1;

[0017] In the above formula, Nrwordline is the total number of word lines of the target extended storage array, Nrbitline is the total number of bit lines of the target extended storage array, Ncornerw is the total number of word lines of the translation array, and Ncornerb is the total number of bit lines of the translation array.

[0018] In some embodiments, the translation array includes the corner array of the target extended storage array. By pre-translating the corner array, the optical proximity correction of the corner array is avoided from being different, improving the yield and quality of semiconductor memory products.

[0019] In some embodiments, the translation array is the corner array of the initial array, and the translation array and the repeating array together constitute the initial array; the repeating array is located between adjacent translation arrays. By dividing the initial array into a corner array and a repeating array, taking three corner arrays as the translation array, pre-translating the three corner arrays to obtain a target extended storage array including a blank area, and filling the blank area by copying the repeating array, a target extended storage array is obtained, avoiding the optical proximity correction of the corner array from being different, so as to improve the yield and quality of semiconductor memory products.

[0020] In some embodiments, the translation array is the corner array of the initial array, and the initial array is composed of the translation array and the intermediate array; the length of the repeating array in the replication direction is less than the length of the intermediate array in the replication direction, and the width of the repeating array in the replication direction is equal to the width of the intermediate array in the replication direction. By dividing the initial array into a corner array and an intermediate array, taking three corner arrays as the translation array, pre-translating the three corner arrays to obtain a target extended storage array including a blank area, determining the repeating array according to the intermediate array, setting the length of the repeating array in the replication direction to be less than the length of the intermediate array in the replication direction, and setting the width of the repeating array in the replication direction to be equal to the width of the intermediate array in the replication direction, and filling the blank area by copying the repeating array, a target extended storage array is obtained, avoiding the optical proximity correction of the corner array from being different, so as to improve the yield and quality of semiconductor memory products.

[0021] In some embodiments, the first direction is consistent with the extending direction of the word line; the second direction is consistent with the extending direction of the bit line, so as to automatically expand according to the extending directions of the word line and the bit line to form a target extended storage array, meeting the capacity requirement of the storage array.

[0022] Another aspect of the present disclosure provides a storage array automatic expansion device, including a target array word line / bit line total number acquisition module, a calculation module, and an expansion module. The target array word line / bit line total number acquisition module is configured to acquire the total number of word lines of the target expanded storage array and the total number of bit lines of the target expanded storage array; the calculation module is configured to calculate the translation amount of the translation array in the translation direction according to the total number of word lines, the total number of bit lines, the total number of word lines of the translation array, the total number of bit lines of the translation array, and a preset translation rule; and calculate the replication times of the replication array in the replication direction according to the translation amount, the total number of word lines of the replication array, the total number of bit lines of the replication array, and a preset replication rule; the expansion module is configured to control at least part of the translation array and at least part of the replication array to translate the translation amount along the translation direction, and the replication array to replicate the replication times along the replication direction to obtain a target expanded storage array.

[0023] In some embodiments, the translation array includes a first translation array defined to translate along a first direction, a second translation array defined to translate along a second direction, and a third translation array defined to translate along the first direction and the second direction; the calculation module includes a first translation amount calculation unit, a second translation amount calculation unit, and a third translation amount calculation unit. The first translation amount calculation unit is configured to calculate the first direction translation amount of the first translation array in the first direction according to the difference between the total number of bit lines of the target expanded storage array and the total number of bit lines of the translation array; the second translation amount calculation unit is configured to calculate the second direction translation amount of the second translation array in the second direction according to the difference between the total number of word lines of the target expanded storage array and the total number of word lines of the translation array; the third translation amount calculation unit is configured to use the vector sum of the first direction translation amount and the second direction translation amount as the third direction translation amount of the third translation array.

[0024] In some embodiments, the replication array includes a first replication array for replicating in the first direction, a second replication array for replicating in the second direction, and a third replication array for replicating in the first direction and the second direction; the calculation module further includes a first replication times calculation unit and a second replication times calculation unit. The first replication times calculation unit is configured to calculate the first replication times of the first replication array and the third replication array in the first direction according to the difference between the total number of bit lines of the target expanded storage array and the total number of bit lines of the translation array; the second replication times calculation unit is configured to calculate the second replication times of the second replication array and the third replication array in the second direction according to the difference between the total number of word lines of the target expanded storage array and the total number of word lines of the translation array.

[0025] In some embodiments, the expansion module includes a translation unit and a replication unit. The translation unit is configured to control the first translation array and a partial replication array to translate by a first-direction translation amount along the first direction, control the second translation array and the partial replication array to translate by a second-direction translation amount along the second direction, and control the third translation array to translate by a third-direction translation amount along the vector sum direction of the first direction and the second direction; the replication unit is configured to control the first replication array to replicate by a first replication number along the first direction, control the second replication array to replicate by a second replication number along the second direction, and control the third replication array to replicate by the first replication number along the first direction and replicate by the second replication number along the second direction.

[0026] In some embodiments, the translation array includes a corner array of the target expansion storage array; the first direction is consistent with the extension direction of the word line; the second direction is consistent with the extension direction of the bit line.

[0027] Another aspect of the present disclosure provides a computer device, including a memory and a processor. A computer program is stored on the memory and can run on the processor. When the processor executes the program, the steps of the method in any one of the embodiments of the present disclosure are implemented.

[0028] Another aspect of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in any one of the embodiments of the present disclosure are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0030] Figure 1 It is a schematic flowchart of a method for automatically expanding a storage array provided in an embodiment of the present disclosure;

[0031] Figure 2 It is a schematic flowchart of a method for automatically expanding a storage array provided in another embodiment of the present disclosure;

[0032] Figure 3a It is a schematic top view of an initial array provided in an embodiment of the present disclosure;

[0033] Figure 3b It is a schematic top view of the outline of a target expansion storage array provided in an embodiment of the present disclosure;

[0034] Figure 3c A top view schematic diagram of an initial array provided in another embodiment of the present disclosure;

[0035] Figure 3d A top view schematic diagram of the outline of a target extended storage array provided in another embodiment of the present disclosure;

[0036] Figure 4a A top view schematic diagram of a target extended storage array provided in an embodiment of the present disclosure;

[0037] Figure 4b A top view schematic diagram of a target extended storage array provided in another embodiment of the present disclosure;

[0038] Figure 5 A structural schematic diagram of a storage array automatic expansion device provided in an embodiment of the present disclosure;

[0039] Figure 6 A structural schematic diagram of a storage array automatic expansion device provided in another embodiment of the present disclosure;

[0040] Figure 7 A structural schematic diagram of a storage array automatic expansion device provided in yet another embodiment of the present disclosure;

[0041] Figure 8 A structural schematic diagram of a storage array automatic expansion device provided in still another embodiment of the present disclosure;

[0042] Reference numerals and descriptions:

[0043] 10. First translation array; 20. Second translation array; 30. Third translation array; 40. Fourth translation array; 81. First repetition array; 82. Second repetition array; 83. Third repetition array; 811. First upper repetition array; 812. First lower repetition array; 821. Second left repetition array; 822. Second right repetition array; 91. First blank area; 92. Second blank area; 93. Third blank area; 94. Fourth blank area; 95. Fifth blank area; 101. First intermediate array; 102. Second intermediate array; 103. Third intermediate array; 104. Fourth intermediate array; 105. Fifth intermediate array; 50. Storage array automatic expansion device; 51. Target array word line / bit line total number acquisition module; 52. Calculation module; 53. Expansion module; 521. First translation amount calculation unit; 522. Second translation amount calculation unit; 523. Third translation amount calculation unit; 524. First copy number calculation unit; 525. Second copy number calculation unit; 531. Translation unit; 532. Copy unit; 100. Initial array; 300. Target expanded storage array. Detailed implementation manners

[0044] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of the present disclosure more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] When using "including", "having", and "comprising" described herein, unless a clear limiting term is used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be understood as having a quantity of one.

[0047] It should be understood that although terms such as "first" and "second" can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element can be called the second element, and similarly, the second element can be called the first element.

[0048] In the description of the present disclosure, unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0049] It should be noted that in the present disclosure: the "distance" between two adjacent word lines refers to the distance between the center points of two adjacent word lines, and the "average distance" between two adjacent word lines refers to the average value of the distances between the center points of two adjacent word lines.

[0050] Since the basic memory cell structure includes multiple semiconductor layers with a complex layout and the lattice area presented in the memory array is very small, when it is necessary to copy the basic memory cells during the process of manually expanding the memory array, errors such as unclear boundaries or coordinate offsets are likely to occur; moreover, the manual expansion efficiency is low, seriously affecting the production efficiency and shipping quality of semiconductor memory products.

[0051] Please refer to Figure 1 , in an embodiment of the present disclosure, a method for automatically expanding a memory array is provided, including the following steps:

[0052] Step S110, obtaining the total number of word lines of the target expanded memory array and the total number of bit lines of the target expanded memory array;

[0053] Step S120, calculating the translation amount of the translation array in the translation direction according to the total number of word lines of the target expanded memory array, the total number of bit lines of the target expanded memory array, the total number of word lines of the translation array, the total number of bit lines of the translation array, and a preset translation rule; calculating the number of replication times of the replication array in the replication direction according to the translation amount, the total number of word lines of the replication array, the total number of bit lines of the replication array, and a preset replication rule;

[0054] Step S130, controlling at least part of the translation array and at least part of the replication array to translate the corresponding translation amount along the translation direction, and controlling the replication array to replicate the corresponding number of times along the replication direction to obtain the target expanded memory array.

[0055] Specifically, please continue to refer to Figure 1, after obtaining the total number of word lines of the target extended storage array and the total number of bit lines of the target extended storage array, the target extended storage array is automatically generated according to the total number of word lines of the target extended storage array, the total number of bit lines of the target extended storage array, the total number of word lines of the translation array, and the total number of bit lines of the translation array, realizing the automatic and efficient generation of the target extended storage array according to the required storage capacity, avoiding errors such as unclear boundaries or coordinate offsets during the process of manually expanding the storage array, and effectively improving the production efficiency and shipping quality of semiconductor storage products.

[0056] As an example, please refer to Figure 2 , the translation array includes a first translation array defined to translate along a first direction, a second translation array defined to translate along a second direction, and a third translation array defined to translate along the first direction and the second direction; calculating the translation amount of the translation array in the translation direction includes the following steps:

[0057] Step S1211, calculating the first-direction translation amount of the first translation array in the first direction according to the difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array;

[0058] Step S1212, calculating the second-direction translation amount of the second translation array in the second direction according to the difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array;

[0059] Step S1213, taking the vector sum of the first-direction translation amount and the second-direction translation amount as the third-direction translation amount of the third translation array.

[0060] Specifically, the first direction can be set to be consistent with the extension direction of the word lines, and the second direction can be set to be consistent with the extension direction of the bit lines. By controlling the first translation array and part of the repeating array to translate the first-direction translation amount along the first direction, controlling the second translation array and part of the repeating array to translate the second-direction translation amount along the second direction, and controlling the third translation array to translate the third-direction translation amount along the vector sum direction of the first direction and the second direction, a target extended storage array including a blank area is obtained by translating at least part of the translation array and at least part of the repeating array, so that the blank area can be accurately filled by copying the repeating array to obtain the target extended storage array.

[0061] More specifically, the expansion requirements of the storage array can be extended according to the actual required target, such as special structures or inherent defects in the storage array, etc., to determine the shape and size of the translation array and the shape and size of the repeated array. Then, according to the total number of word lines of the target-expanded storage array, the total number of bit lines of the target-expanded storage array, the total number of word lines of the translation array, the total number of bit lines of the translation array, and the preset translation rule, calculate the translation amount of the translation array in the translation direction; and according to the translation amount, the total number of word lines of the repeated array, the total number of bit lines of the repeated array, and the preset replication rule, calculate the replication times of the repeated array in the replication direction; after controlling at least part of the translation array and at least part of the repeated array to translate the corresponding translation amount along the translation direction, control the repeated array to replicate the replication times along the replication direction to obtain the target-expanded storage array.

[0062] As an example, please continue to refer to Figure 2 , calculating the translation amount of the translation array in the translation direction further includes: determining the word line pitch and bit line pitch of the storage array; wherein, the word line pitch is the average distance between two adjacent word lines, and the bit line pitch is the average distance between two adjacent bit lines; calculate the first direction translation amount stretch_x and the second direction translation amount stretch_y according to the following formula:

[0063] stretch_x = (Nbitline - Ncornerb) * bitline_pitch;

[0064] stretch_y = (Nwordline - Ncornerw) * wordline_pitch;

[0065] In the above formula, Nwordline is the total number of word lines of the target-expanded storage array, Ncornerw is the total number of word lines of the translation array, Nbitline is the total number of bit lines of the target-expanded storage array, Ncornerb is the total number of bit lines of the translation array, wordline_pitch is the word line pitch, and bitline_pitch is the bit line pitch.

[0066] As an example, after controlling at least part of the translation array and at least part of the repeated array to translate the corresponding translation amount along the translation direction, control the repeated array to replicate the corresponding replication times along the replication direction, so as to obtain the target-expanded storage array including blank areas after translating at least part of the translation array and at least part of the repeated array, and then fill the blank areas by replicating the repeated array to obtain the target-expanded storage array, avoiding errors such as boundary overlap or coordinate offset in the target-expanded storage array.

[0067] As an example, please continue to refer to Figure 2, the repeating array includes a first repeating array for replication in a first direction, a second repeating array for replication in a second direction, and a third repeating array for replication in the direction of the vector sum of the first direction and the second direction; calculating the number of replications of the repeating array in the replication direction further includes the following steps:

[0068] Step S1221, calculating a first replication number of the first repeating array and the third repeating array in the first direction according to the difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array;

[0069] Step S1222, calculating a second replication number of the second repeating array and the third repeating array in the second direction according to the difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array.

[0070] Specifically, after obtaining the target extended storage array including blank areas by translating at least part of the translation array and at least part of the repeating array, calculate the replication number of the repeating array according to the size of the blank area and the size of the repeating array, so as to achieve intelligent and accurate filling of the blank area and avoid errors such as boundary overlap or coordinate offset in the target extended storage array.

[0071] As an example, calculating the first replication number and the second replication number further includes: determining the number of bit lines Nb in the first repeating array and the number of word lines Nw in the second repeating array; calculating the first replication number repetition_x and the second replication number repetition_y according to the following formula:

[0072] repetition_x = ((Nrbitline - Ncornerb) / Nb) - 1;

[0073] repetition_y = ((Nrwordline - Ncornerw) / Nw) - 1;

[0074] In the above formula, Nrwordline is the total number of word lines of the target extended storage array, Nrbitline is the total number of bit lines of the target extended storage array, Ncornerw is the total number of word lines of the translation array, and Ncornerb is the total number of bit lines of the translation array.

[0075] As an example, please refer to Figure 3a - Figure 3b, the translation array is the corner array of the initial array 100. The translation array includes a first translation array 10, a second translation array 20, a third translation array 30, and a fourth translation array 40. The repeating array includes a first repeating array 81, a second repeating array 82, and a third repeating array 83. Among them, the first translation array 10, the second translation array 20, the third translation array 30, the fourth translation array 40, the first repeating array 81, the second repeating array 82, and the third repeating array 83 constitute the initial array 100. That is, the translation array and the repeating array together constitute the initial array 100. The first translation array 10 is defined to translate along the first direction ox, the second translation array 20 is defined to translate along the second direction oy, the third translation array 30 is defined to translate along the third direction oz. The first repeating array 81 is used to replicate in the first direction ox, the second repeating array 82 is used to replicate in the second direction oy, and the third repeating array 83 is used to replicate in the third direction oz. Among them, the third direction oz is the vector sum of the first direction ox and the second direction oy, and the vector sum direction can include multiple directions between the first direction ox and the second direction oy; the first repeating array 81 includes a first upper repeating array 811 and a first lower repeating array 812 located on opposite sides of the third repeating array 83. The second repeating array 82 includes a second left repeating array 821 and a second right repeating array 822 located on opposite sides of the third repeating array 83. The first upper repeating array 811 is located between the first translation array 10 and the fourth translation array 40, and the first lower repeating array 812 is located between the second translation array 20 and the third translation array 30; the second left repeating array 821 is located between the first translation array 10 and the third translation array 30, and the second right repeating array 822 is located between the second translation array 20 and the fourth translation array 40.

[0076] Figure 3a Among them, the first translation array 10, the second translation array 20, the third translation array 30, and the fourth translation array 40 are all corner arrays of the target extended storage array. After calculating the first direction translation amount, the second direction translation amount, and the third direction translation amount according to the translation amount calculation formula given above, the first translation array 10 and the second left repeating array 821 can be controlled to translate the first direction translation amount along the first direction ox first, the second translation array 20 and the first lower repeating array 812 are controlled to translate the second direction translation amount along the second direction oy, and the third translation array 30 is controlled to translate the third direction translation amount along the third direction oz, resulting in Figure 3b The target extended storage array including blank areas shown. The third direction translation amount is the vector sum of the first direction translation amount and the second direction translation amount. The first direction ox can be set to be consistent with the extension direction (WL) of the word line, and the second direction oy can be set to be consistent with the extension direction (BL) of the bit line.

[0077] Furthermore, please refer toFigure 3b and Figure 4a , after calculating the first replication times and the second replication times according to the replication times calculation formula given above, control the first upper repeated array 811 to replicate the first replication times in the first direction ox to fill the first blank area 91 located between the first translation array 10 and the first upper repeated array 811, control the first lower repeated array 812 to replicate the first replication times in the first direction ox to fill the second blank area 92 located between the third translation array 30 and the first lower repeated array 812, control the second left repeated array 821 to replicate the second replication times in the second direction oy to fill the third blank area 93 located between the second left repeated array 821 and the third translation array 30, control the second right repeated array 822 to replicate the second replication times in the second direction oy to fill the fourth blank area 94 located between the second right repeated array 822 and the second translation array 20, control the third repeated array 83 to replicate the first replication times in the first direction ox and replicate the replicated pattern in the second direction oy to fill the fifth blank area 95, to obtain Figure 4a the target extended storage array 300 shown. By dividing the initial array 100 into corner arrays and repeated arrays, taking the three corner arrays as translation arrays, pre-translating the three corner arrays to obtain a target extended storage array including blank areas, and filling the contour by replicating the repeated arrays, the target extended storage array 300 is obtained, avoiding different optical proximity corrections of the corner arrays, so as to improve the yield and quality of semiconductor memory products.

[0078] In other embodiments, the third repeated array can also be replicated a target number of times alone to fill the fifth blank area, and the target number of times = (the first replication times + 1) × (the second replication times + 1) - 1.

[0079] As an example, please refer to Figure 3c and Figure 3d, the translation array is the corner array of the initial array 100, and the initial array 100 is composed of the translation array and the intermediate array; the translation array includes a first translation array 10, a second translation array 20, a third translation array 30, and a fourth translation array 40, and the intermediate array includes a first intermediate array 101, a second intermediate array 102, a third intermediate array 103, a fourth intermediate array 104, and a fifth intermediate array 105. The first intermediate array 101 is located between the first translation array 10 and the fourth translation array 40, the second intermediate array 102 is located between the second translation array 20 and the third translation array 30, the third intermediate array 103 is located between the first translation array 10 and the third translation array 30, the fourth intermediate array 104 is located between the second translation array 20 and the fourth translation array 40, and the first intermediate array 101, the second intermediate array 102, the third intermediate array 103, and the fourth intermediate array 104 are arranged around the fifth intermediate array 105; the repeating array includes a first repeating array, a second repeating array, and a third repeating array 83. The first repeating array includes a first upper repeating array 811 and a first lower repeating array 812. The second repeating array includes a second left repeating array 821, a second right repeating array 822, and a third repeating array 83. The first upper repeating array 811 is located on the side of the first intermediate array 101 close to the first translation array 10. The length of the first upper repeating array 811 in the first direction ox is less than the length of the first intermediate array 101 in the first direction ox, and the width of the first upper repeating array 811 in the first direction ox is equal to the width of the first intermediate array 101 in the first direction ox; the first lower repeating array 812 is located on the side of the second intermediate array 102 close to the third translation array 30. The length of the first lower repeating array 812 in the first direction ox is less than the length of the second intermediate array 102 in the first direction ox, and the width of the first lower repeating array 812 in the first direction ox is equal to the width of the second intermediate array 102 in the first direction ox; the second left repeating array 821 is located on the side of the third intermediate array 103 close to the third translation array 30. The length of the second left repeating array 821 in the second direction oy is less than the length of the third intermediate array 103 in the second direction oy, and the width of the second left repeating array 821 in the second direction oy is equal to the width of the third intermediate array 103 in the second direction oy; the second right repeating array 822 is located on the side of the fourth intermediate array 104 close to the second translation array 20. The length of the second right repeating array 822 in the second direction oy is less than the length of the fourth intermediate array 104 in the second direction oy, and the width of the second right repeating array 822 in the second direction oy is equal to the width of the fourth intermediate array 104 in the second direction oy;The third repeated array 83 is located in the fifth intermediate array 105 in the area near the third intermediate array 103 and the second intermediate array 102. The length of the third repeated array 83 in the first direction ox is less than the length of the fifth intermediate array 105 in the first direction ox, and the length of the third repeated array 83 in the second direction oy is less than the length of the fifth intermediate array 105 in the second direction oy. The translation amount of the translation array in the translation direction can be calculated according to the following formula:;

[0080] stretch_x = (Nbitline - Ncornerb - Nmiddleb) * bitline_pitch;

[0081] stretch_y = (Nwordline - Ncornerw - Nmiddlew) * wordline_pitch;

[0082] In the above formula, stretch_x is the first direction translation amount of the first translation array 10 in the first direction ox, stretch_y is the second direction translation amount of the second translation array 20 in the second direction oy, Nwordline is the total number of word lines of the target extended storage array, Ncornerw is the total number of word lines of the translation array, Nbitline is the total number of bit lines of the target extended storage array, Ncornerb is the total number of bit lines of the translation array, Nmiddleb is the total number of bit lines of the intermediate array, Nmiddlew is the total number of word lines of the intermediate array, wordline_pitch is the word line pitch, and bitline_pitch is the bit line pitch.

[0083] Furthermore, the replication times of the repeated array in the corresponding replication direction can be calculated according to the following formula:

[0084] repetition_x = (Nrbitline - Ncornerb - Nmiddleb) / Nb;

[0085] repetition_y = (Nrwordline - Ncornerw - Nmiddlew) / Nw;

[0086] In the above formula, repetition_x is the first replication count of the first repeating array in the first direction ox, repetition_y is the second replication count of the second repeating array in the second direction oy, Nb is the number of bit lines in the first repeating array, Nw is the number of word lines in the second repeating array, Nrwordline is the total number of word lines of the target extended memory array, Nrbitline is the total number of bit lines of the target extended memory array, Nmiddleb is the total number of bit lines of the middle array, Nmiddlew is the total number of word lines of the middle array, Ncornerw is the total number of word lines of the translation array, and Ncornerb is the total number of bit lines of the translation array.

[0087] Further, please continue to refer to Figure 3c and Figure 3d , after controlling the first translation array 10 and the third middle array 103 to translate in the first direction ox by the first direction translation amount stretch_x, and controlling the second translation array 20 and the second middle array 102 to translate in the second direction oy by the second direction translation amount stretch_y, control the third translation array 30 to translate in the third direction oz by the third direction translation amount to obtain the target extended memory array including blank areas as shown in Figure 3d . The third direction translation amount is the vector sum of the first direction translation amount and the second direction translation amount. The first direction ox can be set to be consistent with the extension direction of the word lines (WL), and the second direction oy can be set to be consistent with the extension direction of the bit lines (BL).

[0088] Further, please refer to Figure 3d and Figure 4b , control the first upper repeating array 811 to replicate the first replication count repetition_x in the first direction ox to fill the first blank area 91 located between the first translation array 10 and the first middle array 101, control the first lower repeating array 812 to replicate the first replication count repetition_x in the first direction ox to fill the second blank area 92 located between the third translation array 30 and the second middle array 102, control the second left repeating array 821 to replicate the second replication count repetition_y in the second direction oy to fill the third blank area 93 located between the second left repeating array 821 and the third translation array 30, and control the second right repeating array 822 to replicate the second replication count repetition_y in the second direction oy to fill the fourth blank area 94 located between the second right repeating array 822 and the second translation array 20.

[0089] Since the fifth blank area 95 is irregular in shape, multiple replication strategies can be used to replicate the third repeated array 83 to fill the fifth blank area 95. Here, taking the individual replication of the third repeated array 83 as an example, the required replication times of the third repeated array 83 in different directions are described. Since the maximum length of the third repeated array 83 in the first direction ox is (Nrbitline - Ncornerb) * bitline_pitch, and the maximum length in the second direction oy is (Nwordline - Ncornerw) * wordline_pitch. Assuming that the length of the third repeated array 83 in the first direction ox is equal to the length of the first upper repeated array 811 in the first direction ox, and the length in the second direction oy is equal to the length of the second right repeated array 822 in the second direction oy, then the maximum replication times of the third repeated array 83 in the first direction ox is equal to repetition_xmax = (Nrbitline - Ncornerb) / Nb, the maximum replication times in the second direction oy is equal to repetition_ymax = (Nrwordline - Ncornerw) / Nw, and the total replication times within the fifth blank area 95 is equal to repetition_xmax * repetition_ymax - (Nmiddleb * Nmiddlew) / Nb * Nw.

[0090] In other embodiments, it is also possible to control the third repeated array 83 to first fill the blank between the fifth intermediate array 105 and the third intermediate array 103, and then set the part with a length of (Nrbitline - Ncornerb) * bitline_pitch in the first direction ox and a length of Nw * wordline_pitch in the second direction oy as the fourth repeated array, and perform replication in the second direction oy to fill the fifth blank area 95. It can be understood that the length of the fourth repeated array in the second direction oy is the same as the length of the third repeated array in the second direction oy; similarly, it is also possible to first control the third repeated array 83 to fill the blank between the fifth intermediate array 105 and the second intermediate array 102, and then use the newly defined fourth repeated array with a longer length in the second direction oy to perform replication in the first direction ox to fill the fifth blank area 95.

[0091] The reasons for using part of the intermediate array as the repeated array include, but are not limited to: the translation amount of the translation array in the first direction ox or the second direction oy is not an integer multiple of the length of the corresponding intermediate array in that direction, and directly using the intermediate array for replication will cause overlap.

[0092] Please refer to Figure 5, in an embodiment of the present disclosure, the storage array automatic expansion device 50, the storage array automatic expansion device 50 includes a target array word line / bit line total number acquisition module 51, a calculation module 52 and an expansion module 53. The target array word line / bit line total number acquisition module 51 is used to acquire the total number of word lines of the target expanded storage array and the total number of bit lines of the target expanded storage array. The calculation module 52 is used to calculate the translation amount of the translation array in the translation direction according to the total number of word lines, the total number of bit lines, the total number of word lines of the translation array, the total number of bit lines of the translation array and a preset translation rule, and calculate the replication times of the replication array in the replication direction according to the translation amount, the total number of word lines of the replication array, the total number of bit lines of the replication array and a preset replication rule. The expansion module 53 is used to control at least part of the translation array and at least part of the replication array to translate the corresponding translation amount along the translation direction, and the replication array to replicate the replication times along the replication direction to obtain the target expanded storage array. Since in this embodiment, the target expanded storage array can be automatically generated according to the total number of word lines of the target expanded storage array and the total number of bit lines of the target expanded storage array, the target expanded storage array is automatically and efficiently generated according to the required storage capacity, avoiding errors such as unclear boundaries or coordinate offsets during the manual expansion of the storage array, and effectively improving the production efficiency and shipping quality of semiconductor storage products.

[0093] As an example, please refer to Figure 6 , the translation array includes a first translation array defined to translate along a first direction, a second translation array defined to translate along a second direction, and a third translation array defined to translate along the first direction and the second direction. The calculation module 52 includes a first translation amount calculation unit 521, a second translation amount calculation unit 522 and a third translation amount calculation unit 523. The first translation amount calculation unit 521 is used to calculate the first direction translation amount of the first translation array in the first direction according to the difference between the total number of bit lines of the target expanded storage array and the total number of bit lines of the translation array. The second translation amount calculation unit 522 is used to calculate the second direction translation amount of the second translation array in the second direction according to the difference between the total number of word lines of the target expanded storage array and the total number of word lines of the translation array. The third translation amount calculation unit 523 is used to use the vector sum of the first direction translation amount and the second direction translation amount as the third direction translation amount of the third translation array. By controlling the first translation array and part of the replication array to translate the first direction translation amount along the first direction, controlling the second translation array and part of the replication array to translate the second direction translation amount along the second direction, and controlling the third translation array to translate the third direction translation amount along the vector sum direction of the first direction and the second direction, a target expanded storage array including a blank area is obtained by translating at least part of the translation array and at least part of the replication array, so that the blank area can be filled by replicating the replication array to obtain the target expanded storage array.

[0094] As an example, please refer to Figure 7, the repeating array includes a first repeating array for replication in the first direction, a second repeating array for replication in the second direction, and a third repeating array for replication in both the first and second directions; the calculation module 52 further includes a first replication count calculation unit 524 and a second replication count calculation unit 525. The first replication count calculation unit 524 is used to calculate the first replication count of the first repeating array and the third repeating array in the first direction according to the difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array; the second replication count calculation unit 525 is used to calculate the second replication count of the second repeating array and the third repeating array in the second direction according to the difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array. After obtaining the target extended storage array including the blank area by translating at least part of the translation array and at least part of the repeating array, calculate the replication count of the repeating array according to the size of the blank area and the size of the repeating array, so as to achieve intelligent and accurate filling of the blank area and avoid errors such as boundary overlap or coordinate offset in the target extended storage array.

[0095] As an example, please refer to Figure 8 , the expansion module 53 includes a translation unit 531 and a replication unit 532. The translation unit 531 is used to control the first translation array and part of the repeating array to translate in the first direction by the first direction translation amount, control the second translation array and part of the repeating array to translate in the second direction by the second direction translation amount, and control the third translation array to translate in the direction of the vector sum of the first and second directions by the third direction translation amount; the replication unit 532 is used to control the first repeating array to replicate the first replication count in the first direction, control the second repeating array to replicate the second replication count in the second direction, and control the third repeating array to replicate the first replication count in the first direction and the second replication count in the second direction. After obtaining the target extended storage array including the blank area by translating at least part of the translation array and at least part of the repeating array, calculate the replication count of the repeating array according to the size of the blank area and the size of the repeating array, so as to achieve intelligent and accurate filling of the blank area and avoid errors such as boundary overlap or coordinate offset in the target extended storage array.

[0096] As an example, the translation array includes the corner array of the target extended storage array; the first direction is consistent with the extending direction of the word lines; the second direction is consistent with the extending direction of the bit lines, so as to automatically expand according to the extending directions of the word lines and the bit lines to form the target extended storage array and meet the capacity requirements of the storage array.

[0097] In an embodiment of the present disclosure, a computer device is provided, including a memory and a processor. A computer program that can run on the processor is stored on the memory. When the processor executes the program, the steps of the method described in any one of the embodiments of the present disclosure are implemented.

[0098] In one embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the embodiments of the present disclosure are implemented.

[0099] Although Figure 1 - Figure 2 each step in the flowchart of Figure 1 - Figure 2 is shown in sequence according to the indication of the arrow, these steps are not necessarily executed in the sequence indicated by the arrow. Unless there is a clear description in this article, the execution of these steps is not strictly restricted in sequence, and these steps can be executed in other sequences. Moreover, although

[0100] those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database or other medium used in the various embodiments provided by the present disclosure can include non-volatile and / or volatile memories.

[0101] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present invention.

[0102] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0103] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0104] The above-described embodiments only represent several implementation manners of the present disclosure. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the disclosed patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent should be subject to the appended claims.

Claims

1. An automatic expansion method for a storage array, characterized in that Including: Obtaining the total number of word lines of the target extended storage array and the total number of bit lines of the target extended storage array; Calculating the translation amount of the translation array in the translation direction according to the total number of word lines, the total number of bit lines, the total number of word lines of the translation array, the total number of bit lines of the translation array, and a preset translation rule; calculating the replication times of the replication array in the replication direction according to the translation amount, the total number of word lines of the replication array, the total number of bit lines of the replication array, and a preset replication rule; Controlling at least part of the translation array and at least part of the replication array to translate the translation amount along the translation direction, and controlling the replication array to replicate the replication times along the replication direction to obtain the target extended storage array.

2. The method according to claim 1, wherein The translation array includes a first translation array defined to translate along a first direction, a second translation array defined to translate along a second direction, and a third translation array defined to translate along the first direction and the second direction; Calculating the translation amount of the translation array in the translation direction includes: Calculating a first-direction translation amount of the first translation array in the first direction according to the difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array; Calculating a second-direction translation amount of the second translation array in the second direction according to the difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array; Taking the vector sum of the first-direction translation amount and the second-direction translation amount as the third-direction translation amount of the third translation array.

3. The method according to claim 2, wherein Calculating the translation amount of the translation array in the translation direction further includes: Determining the word line pitch and the bit line pitch of the storage array; wherein, the word line pitch is the average distance between two adjacent word lines, and the bit line pitch is the average distance between two adjacent bit lines; Calculating the first-direction translation amount stretch_x and the second-direction translation amount stretch_y according to the following formula: stretch_x = (Nbitline - Ncornerb) * bitline_pitch; stretch_y = (Nwordline - Ncornerw) * wordline_pitch; In the above formula, Nwordline is the total number of word lines of the target extended storage array, Ncornerw is the total number of word lines of the translation array, Nbitline is the total number of bit lines of the target extended storage array, Ncornerb is the total number of bit lines of the translation array, wordline_pitch is the word line pitch, and bitline_pitch is the bit line pitch.

4. The method according to claim 2 or 3, characterized in that, After controlling at least part of the translation array and at least part of the replication array to translate the translation amount along the translation direction, controlling the replication array to replicate the replication times along the replication direction.

5. The method according to claim 2 or 3, characterized in that, The replication array includes a first replication array for replicating in the first direction, a second replication array for replicating in the second direction, and a third replication array for replicating in the direction of the vector sum of the first direction and the second direction; Calculating the replication times of the replication array in the replication direction includes: Calculate a first replication number of the first repeated array and the third repeated array in the first direction according to a difference between a total number of bit lines of the target extended storage array and a total number of bit lines of the translation array; Calculate a second replication number of the second repeated array and the third repeated array in the second direction according to a difference between a total number of word lines of the target extended storage array and a total number of word lines of the translation array.

6. The method according to claim 5, wherein Calculating the first replication number and the second replication number further includes: Determine a number of bit lines Nb in the first repeated array and a number of word lines Nw in the second repeated array; Calculate the first replication number repetition_x and the second replication number repetition_y according to the following formula: repetition_x = ((Nrbitline - Ncornerb) / Nb) - 1; repetition_y = ((Nrwordline - Ncornerw) / Nw) - 1; In the above formula, Nrwordline is the total number of word lines of the target extended storage array, Nrbitline is the total number of bit lines of the target extended storage array, Ncornerw is the total number of word lines of the translation array, and Ncornerb is the total number of bit lines of the translation array.

7. The method according to any one of claims 1 to 3, characterized in that, The translation array includes a corner array of the target extended storage array.

8. The method according to claim 7, wherein The translation array is a corner array of the initial array, and the translation array and the repeated array together form the initial array; The repeated array is located between adjacent translation arrays.

9. The method according to claim 7, characterized in that The translation array is a corner array of the initial array, and the initial array is composed of the translation array and an intermediate array; A length of the repeated array in the replication direction is less than a length of the intermediate array in the replication direction, and a width of the repeated array in the replication direction is equal to a width of the intermediate array in the replication direction.

10. The method according to claim 2 or 3, wherein: The first direction is consistent with an extending direction of word lines; The second direction is consistent with an extending direction of bit lines.

11. An automatic expansion device for a storage array, characterized in that, Includes: A target array word line / bit line total number acquisition module, configured to acquire a total number of word lines of a target extended storage array and a total number of bit lines of the target extended storage array; A calculation module, configured to calculate a translation amount of the translation array in a translation direction according to the total number of word lines, the total number of bit lines, the total number of word lines of the translation array, the total number of bit lines of the translation array, and a preset translation rule; And calculate a replication number of the repeated array in a replication direction according to the translation amount, the total number of word lines of the repeated array, the total number of bit lines of the repeated array, and a preset replication rule; An extension module, configured to control at least part of the translation array and at least part of the repeated array to translate the translation amount along the translation direction, and the repeated array to replicate the replication number along the replication direction, so as to obtain a target extended storage array.

12. The device according to claim 11, wherein, The translation array includes a first translation array defined to translate in a first direction, a second translation array defined to translate in a second direction, and a third translation array defined to translate in the first direction and the second direction; The calculation module includes: A first translation amount calculation unit, configured to calculate a first-direction translation amount of the first translation array in the first direction according to a difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array; A second translation amount calculation unit, configured to calculate a second-direction translation amount of the second translation array in the second direction according to a difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array; A third translation amount calculation unit, configured to use a vector sum of the first-direction translation amount and the second-direction translation amount as a third-direction translation amount of the third translation array.

13. The device according to claim 12, characterized in that, The repeating array includes a first repeating array for repeating in the first direction, a second repeating array for repeating in the second direction, and a third repeating array for repeating in the first direction and the second direction; The calculation module further includes: A first replication times calculation unit, configured to calculate a first replication times of the first repeating array and the third repeating array in the first direction according to a difference between the total number of bit lines of the target extended storage array and the total number of bit lines of the translation array; A second replication times calculation unit, configured to calculate a second replication times of the second repeating array and the third repeating array in the second direction according to a difference between the total number of word lines of the target extended storage array and the total number of word lines of the translation array.

14. The device according to claim 13, characterized in that, The extension module includes: A translation unit, configured to control the first translation array and part of the repeating arrays to translate the first-direction translation amount in the first direction, control the second translation array and part of the repeating arrays to translate the second-direction translation amount in the second direction, and control the third translation array to translate the third-direction translation amount in a direction of a vector sum of the first direction and the second direction; A replication unit, configured to control the first repeating array to repeat the first replication times in the first direction, control the second repeating array to repeat the second replication times in the second direction, and control the third repeating array to repeat the first replication times in the first direction and repeat the second replication times in the second direction.

15. The device according to any one of claims 12 - 14, characterized in that, The translation array includes a corner array of the target extended storage array; The first direction is consistent with the extending direction of the word lines; The second direction is consistent with the extending direction of the bit lines.

16. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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