A memory chip early storage failure screening method and test system

Abstract

The application relates to a memory chip early storage failure screening method and a test system. The screening method comprises the following steps: acquiring first voltage data of all chips on a wafer; establishing a first voltage data distribution curve; screening out failure chips and high-risk chips with a first dispersion degree; establishing a distribution hotspot map of the first voltage data on the wafer; determining a high-risk area in the failure chips and the high-risk chips; performing reliability test on the high-risk chips and the chips in the high-risk area, and acquiring second voltage data of the chips after the test; determining unqualified chips according to the second voltage data; and determining a target card control value according to the first voltage data of the unqualified chips, which is used for early failure screening of wafer chips in the same batch. The test system is based on the above screening method and comprises a voltage data acquisition module, a reliability test module, an analysis and calculation module and a screening module. The application can realize more efficient and comprehensive early storage failure screening.

Description

Technical Field

[0001] This application relates to the field of memory chip testing technology, and in particular to a method and testing system for screening early memory failures in memory chips. Background Technology

[0002] The failure rate of electronic components such as memory chips, and the electronic devices containing these components, typically exhibits a so-called bathtub curve shape. For example, early failure of memory chips refers to the period in which many chip products have a relatively high failure rate in the early stages of use, and this failure rate decreases rapidly. The characteristics are that failures occur in the early stages of product use, the failure rate is high, and it decreases rapidly with prolonged operation. Early failure has a significant impact on user experience, manufacturer profits, and reputation; therefore, testing and screening for early-failure chips is crucial for product quality. Especially for non-volatile memory chips with limited write cycles and critical data retention functions, further early memory failure screening is necessary for chips that pass initial screening.

[0003] Currently, the industry typically screens chips for early failures by controlling the initial threshold voltage of the worst-performing memory bit within the chip and the residual threshold voltage of the memory bit after temperature-accelerated aging. This screening method does not consider the risk differences between different areas of the wafer caused by variations in process conditions and material batches during manufacturing, resulting in poor screening efficiency. A reasonable and effective screening scheme can not only save testing time and costs but also determine subsequent yield and product lifespan. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the existing technology, the purpose of this application is to provide a method for screening early memory failures of memory chips that combines the test data distribution curve of the chip and the test data distribution heat map within the wafer, so as to more comprehensively and effectively screen out potential problematic chips, and a test system based on the screening method.

[0005] To achieve the above objectives, this application provides the following technical solutions.

[0006] A method for screening early memory failures in memory chips, comprising the following steps:

[0007] Obtain the first voltage data of all chips on the wafer;

[0008] Establish the first voltage data distribution curve on the wafer;

[0009] Based on the first voltage data distribution curve, failed chips and high-risk chips with a dispersion exceeding the first dispersion on the side with poorer first voltage data are screened out.

[0010] Establish a hotspot map of the distribution of the first voltage data on the wafer;

[0011] Based on the heat map, a first high-risk region is determined where the failed chips and high-risk chips on the wafer are concentrated.

[0012] The high-risk chip and the chips in the first high-risk area are subjected to reliability testing, and the second voltage data of the tested chips are obtained.

[0013] The defective chip is determined based on the second voltage data;

[0014] The target control value is determined based on the first voltage data of the defective chip, and is used to screen for early failure of wafer chips in the same batch.

[0015] In some implementations, the first voltage data is the worst threshold voltage of the chip before the reliability test; the second voltage data is the threshold voltage corresponding to the first voltage data after the reliability test, or the second voltage data is the worst threshold voltage of the chip after the reliability test, or the second voltage data is the attenuation value of the first voltage data after the reliability test.

[0016] In some implementations, the first dispersion is determined by a set multiple of the variance of the first voltage data distribution curve, or by a first threshold of the first voltage data; the chip is a NOR Flash memory chip or a NAND Flash memory chip.

[0017] In some implementations, the reliability test includes accelerated aging testing; the step of determining the defective chip based on the second voltage data specifically includes the following steps:

[0018] Based on the first voltage data and the second voltage data, a lifetime fitting extrapolation is performed to calculate the second voltage data threshold corresponding to the minimum lifespan of the chip product; and...

[0019] Chips whose second voltage data is worse than the second voltage data threshold are identified as unqualified chips.

[0020] In some implementations, determining the first high-risk area based on the heat map specifically includes the following steps:

[0021] The wafer is divided into a central region and several annular regions surrounding the central region;

[0022] Calculate the average first voltage data of all chips in the central region and the average first voltage data of all chips in each annular region;

[0023] The region where the average value of the first voltage data is lower than the second threshold or lower than the set percentile is designated as the first high-risk region.

[0024] In some implementations, determining the first high-risk area based on the heat map specifically includes the following steps:

[0025] Calculate the average first voltage data for each chip and all chips within a set distance around it;

[0026] If the average value of the first voltage data of the chip is worse than the second threshold or the set percentile, then the chip is located in the first high-risk area.

[0027] In some implementations, the target control value includes a first target control value, used to control the wafer chips in the same batch using first voltage data; the first target control value is not worse than the first voltage data of all the defective chips.

[0028] In some implementations, the target control value further includes a second target control value; the second target control value has a higher level of control than the first target control value, and the second target control value is used to further control the chip in the first high-risk area.

[0029] In some implementations, the method further includes the step of, after the reliability test, acquiring the distribution of attenuation values ​​of the first voltage data within the wafer to determine a second high-risk region; the target control value also includes a third target control value, the third target control value having a higher control stringency than the first target control value, the third target control value being used to further control the chip within the second high-risk region.

[0030] This application also provides a memory chip early failure testing system, including a voltage data acquisition module, a reliability testing module, an analysis and calculation module, and a screening module; the voltage data acquisition module is used to acquire voltage data of all chips on the wafer, the reliability testing module is used to perform reliability testing on the chips, the analysis and calculation module is used to determine a target control value according to any of the aforementioned memory chip early failure screening methods, and the screening module is used to perform early failure screening on wafer chips in the same batch according to the target control value.

[0031] The various embodiments of this application have at least one of the following technical effects:

[0032] 1. By combining the initial value distribution curve of the chip threshold voltage and its position distribution map within the wafer, high-risk chips are identified for reliability testing, thus narrowing down the range of chips for reliability testing while ensuring comprehensive screening of high-risk chips.

[0033] 2. By identifying high-risk areas based on the shape of the wafer and determining the first high-risk area based on the voltage data of surrounding chips, high-risk areas for chip failure caused by major influencing factors such as process and materials can be identified.

[0034] 3. By setting different target control values ​​for high-risk areas and other areas, screening efficiency can be further improved;

[0035] 4. Identifying the second highest-risk area by analyzing the distribution of threshold voltage data after reliability testing can further improve screening efficiency. Attached Figure Description

[0036] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of the present invention.

[0037] Figure 1 This is a schematic diagram of the voltage data of a memory cell containing one storage bit;

[0038] Figure 2 This is a schematic diagram of the voltage data of a memory cell containing two storage bits;

[0039] Figure 3 This is a flowchart of an embodiment of a method for screening early memory failures in memory chips;

[0040] Figure 4 This is a specific flow of one embodiment of step S700;

[0041] Figure 5 This is a specific flow of one embodiment of step S500;

[0042] Figure 6 This is a specific flow of another embodiment of step S500;

[0043] Figure 7 This is a schematic diagram of first voltage data, second voltage data, and first voltage attenuation value in one embodiment;

[0044] Figure 8 This is a schematic diagram of the first voltage data distribution curve of an embodiment;

[0045] Figure 9 This is a schematic diagram of the hotspot distribution of the first voltage data in one embodiment;

[0046] Figure 10 This is a schematic diagram of the reliability test results for one embodiment;

[0047] Figure 11 This is a schematic diagram of the attenuation value distribution of the first voltage data in one embodiment. Detailed Implementation

[0048] To more clearly illustrate the embodiments of this application or the technical solutions in the prior art, the specific implementation methods of this application will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort.

[0049] To keep the drawings concise, each drawing only schematically shows the parts relevant to this application and does not represent their actual structure as a product. In some drawings, only one of the components with the same structure or function is schematically depicted, or only one is labeled. In this document, "a" means not only "only one" but also "more than one." The term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. The terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0050] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0051] Non-volatile memory chips, such as Flash memory chips, consist of multiple memory cells, each capable of storing at least one bit of information, meaning they include at least one storage bit. Memory cells are typically constructed from field-effect transistors with floating gates. For example... Figure 1 As shown, the threshold voltage range of each NOR Flash memory cell 100 in a NOR Flash memory chip is divided into two regions. In the erase state, the threshold voltage of the memory cell is the erase state threshold voltage V1; in the programming state, the threshold voltage is the programming state threshold voltage V0; these represent whether the information stored in the memory bit is "1" or "0", respectively. RV is the read operation voltage, used to read the information from the memory bit. Typically, the threshold voltages of all memory bits in a memory chip or a wafer are... Figure 1 The reading shows a normal distribution. Furthermore, strictly speaking, the readout operating voltage RV also has a distribution range.

[0052] like Figure 2As shown, each NAND Flash memory cell 200 of the NAND Flash memory chip can store 2 bits of information, or store 1 or more bits of information within its memory cell. The threshold voltage of the memory cell in its erased state is V. 11 The threshold voltage for the programming state can be V. 10 V 00 or V 01 RV1, RV2, and RV3 are the read operation voltages. The screening method and testing system of this application can also be used for NAND Flash memory chips. This specification mainly uses NOR Flash memory chips as an example, and provides supplementary explanations for NAND Flash memory chips where there are differences.

[0053] When screening for early memory failures using the initial value of the programmed state threshold voltage V0 or its residual value after high-temperature baking, the screening efficiency is low and it is difficult to comprehensively identify potential early failure chips because there is no differentiation based on different locations on the wafer. This application uses big data statistical information from different locations on the wafer to set more reasonable target control values ​​and screening methods for early memory failure screening, which can complete the screening quickly, efficiently, and comprehensively.

[0054] Example 1. This example is a method for screening early memory failures in memory chips, such as... Figure 3 As shown, this embodiment includes the following steps:

[0055] S100: Obtain the first voltage data of all chips on one wafer from multiple wafers in the same batch. In this embodiment, the first voltage data is the worst-case threshold voltage for each chip. For NOR Flash memory chips, this worst-case threshold voltage is... Figure 1 The worst-case data for the programming state threshold voltage V0 shown is the threshold voltage closest to the read operation voltage RV among all the programming state threshold voltages V0 of all memory cells within the chip. For NAND Flash memory chips, this worst-case threshold voltage is... Figure 2 The worst-case data among the threshold voltage margins between the threshold voltages and corresponding read voltages for the multiple programming states is shown, and statistical comparisons are performed across the entire chip. A similar process can be applied to memory cells containing more storage bits. This step can be completed quickly using existing techniques.

[0056] S200, establish the first voltage data distribution curve 110 on the wafer. (Example) Figure 7 and Figure 8 As shown, across the entire wafer, the first voltage data, i.e., the worst-case threshold voltage for each chip, typically follows a normal distribution. The horizontal axis of the curve represents the first voltage data value, and the vertical axis represents the number of chips corresponding to each first voltage data value.

[0057] S300, based on the first voltage data distribution curve 110, filters out failed chips and high-risk chips whose dispersion exceeds the first dispersion on the side with poorer first voltage data. For example... Figure 8 As shown, the side with poorer first voltage data refers to the left side of the figure, i.e., the side with a smaller threshold voltage or threshold voltage margin. The first dispersion is determined by a set multiple of the variance of the first voltage data distribution curve 110. In this embodiment, the dispersion used for screening is 3σ, which is three times the variance of the normal distribution. Under an ideal normal distribution, the chips in region A of the figure are the failed chips and high-risk chips, accounting for approximately 0.14% of all chips on the wafer.

[0058] S400, establishes a hotspot map of the first voltage data distribution on the wafer. For example... Figure 9 As shown, the first voltage data of each chip is visually displayed as hotspots on the planar pattern of the wafer. Chips with reddish areas have lower first voltage data, while chips with greenish areas have higher first voltage data; in other words, chips with reddish areas have a higher risk of failure. Therefore, the areas with high failure risk can be intuitively identified from this hotspot distribution map. The distribution patterns of these areas are usually related to the wafer manufacturing process and the batch of wafer material. The main distribution patterns include anomalies in the central area, anomalies in the edge area, and local anomalies with a certain shape.

[0059] S500 identifies the first high-risk region on the wafer where failed and high-risk chips are concentrated based on the heat map. Since the heat map can be replaced by a two-dimensional depth image, it is easy to obtain the region where failed and high-risk chips are concentrated through image processing.

[0060] S600: High-risk chips and chips within the first high-risk area undergo reliability testing, and the second voltage data of the tested chips is obtained. The range of the high-risk chip and the range of chips within the first high-risk area may overlap, and the first high-risk area may consist of one or more regions. Through the preliminary screening steps described above, high-risk chips whose threshold voltage is closer to the read operation voltage and those located in high-risk areas can be identified. These chips undergo further comprehensive reliability testing to identify those high-risk chips that are likely to fail. The target control value is then determined based on the first voltage data of these chips.

[0061] The second voltage data can be the threshold voltage corresponding to the first voltage data after reliability testing. For example, if the first voltage data of a chip is the worst threshold voltage of a memory cell of that chip (and this voltage value is also the worst threshold voltage of the chip), then the second voltage data of the chip is the worst threshold voltage of the same memory cell after reliability testing. Alternatively, the second voltage data can also be the worst threshold voltage of the chip after reliability testing, but this worst threshold voltage may not have been the worst threshold voltage of the chip before the reliability testing. Furthermore, as... Figure 7 As shown, the second voltage data can also be the attenuation value of the first voltage data after reliability testing. Curve 111 in the figure represents the distribution curve of the first voltage data after attenuation following reliability testing. Specific adjustments can be made based on the content of the reliability test and the focus of chip quality control.

[0062] S700 identifies defective chips based on the second voltage data. Specifically, the assessment threshold for the second voltage data can be determined according to the type of reliability test and relevant standards, thereby identifying chips that do not meet the assessment standards as defective chips. Specific types of reliability tests can be selected and determined from existing technologies. For example... Figure 10 As shown, the reliability test in this embodiment includes a high-temperature baking test at 150°C for 1000 hours, which is a type of accelerated aging test.

[0063] When reliability testing only includes Figure 10 During high-temperature baking tests, memory cells exceeding the second dispersion on the second voltage data distribution curve can be considered chips that will experience early memory failure, i.e., unqualified chips. The second dispersion can be determined using the same method as the first dispersion. Furthermore, in Figure 8 The first voltage data of these defective chips is found on the first voltage data distribution curve 110. The point with the highest threshold voltage among these first voltage data is point B in the figure. The first voltage data at point B can be used as the first target control value (since other embodiments of this application include multiple target control values, the target control value in this embodiment is specifically referred to as the first target control value). When screening other wafer chips in the same batch for early memory failure, only the first voltage data needs to be obtained, and chips with first voltage data worse than the first target control value are screened out. From Figure 8 This can be intuitively understood as follows: if the first voltage data is lower than point B, then the chip to the left of point B is the unqualified chip in the early memory failure screening of the memory chip.

[0064] High-temperature baking tests can test the chip's threshold voltage lifespan in a relatively short time, for example, by... Figure 10The chip's lifetime is obtained by extrapolating the first and second voltage data from the decay curve of the programming state threshold voltage V0 using lifetime fitting. Multiple threshold voltage data points can be acquired during high-temperature baking tests to improve the accuracy of the extrapolation. Figure 4 As shown, step S700 specifically includes the following steps:

[0065] S710 determines the second voltage data threshold through lifetime fitting extrapolation. Based on the fitting extrapolation results, the second voltage data threshold corresponding to the minimum lifetime of the chip product can be calculated.

[0066] S720 determines defective chips based on a second voltage data threshold. Specifically, chips whose second voltage data is lower than the second voltage data threshold are determined to be defective chips.

[0067] If you want to control early write / erase failures of the chip, you can include write / erase endurance testing in the reliability testing. Reliability testing can also include other memory chip performance testing methods such as temperature and humidity testing, low temperature testing, and voltage stress testing.

[0068] To ensure the quality of qualified chips, the first target control value can be allowed a certain margin; that is, the first target control value is set to be slightly greater than the first voltage data at point B. However, the first target control value is never worse than the first voltage data of all unqualified chips.

[0069] S800: Based on the first voltage data of the defective chip, a target control value is determined for early failure screening of wafer chips in the same batch. At this time, only the first voltage data of all chips on the wafer to be controlled needs to be acquired and compared with the target control value to achieve rapid control screening. To avoid ambiguity, unless otherwise specified in this application, "wafer" refers to one or more wafers used to determine the target control value, while other wafers in the same batch are referred to as wafers to be controlled.

[0070] As a variation of this embodiment Figure 8 The dispersion of region A can also be selected as 4σ or other values ​​(σ is the variance of the first voltage data distribution curve 110); for NOR Flash memory chips, the first voltage data can also be the mean, median or a certain dispersion value of the distribution of the programming state threshold voltage V0 of all memory cells in the chip; for NAND Flash memory chips, the mean of the threshold voltage margin of each memory cell can be calculated first, and then the worst value of the mean can be determined in the whole chip as the first voltage data.

[0071] Alternatively, the first dispersion can also be determined based on a first threshold value of the first voltage data. For example, for NOR Flash memory chips, such as... Figure 1As shown, the first voltage data is the programming state threshold voltage V0, which needs to have a certain threshold voltage margin between it and the read operation voltage RV. Based on this threshold voltage margin, a suitable first threshold of the first voltage data can be determined, which is used as the first dispersion to perform preliminary screening of the chip.

[0072] Example 2. Based on Example 1, this example provides a specific method for determining the first high-risk area. For example... Figure 5 As shown, step S500, which determines the first high-risk area based on the heat map, specifically includes the following steps:

[0073] S510 divides the wafer into a central region and several annular regions surrounding the central region. The specific region a chip is located in is determined by the position of its center point. The radius of the central region, the inner diameter of each annular region, and its width can all be determined based on quality control data from production. The widths of the annular regions can be the same or different. For example, when chip quality is relatively unstable in the central and edge regions of the wafer, denser, narrower annular regions can be created, while wider annular regions can be created in the area between the central and edge regions where chip quality is more stable.

[0074] S520 calculates the average first voltage data of all chips in the central region and the average first voltage data of all chips in each annular region; that is, an average first voltage data is calculated for each divided region. At this time, a scatter plot curve between the region location (distance from the center point of the wafer) and the average first voltage data can be established to intuitively show the distribution of the average first voltage data.

[0075] S530, regions where the average value of the first voltage data is lower than the second threshold or lower than a set percentile are designated as the first high-risk regions. Both the second threshold and the set percentile can be determined based on actual production statistics. The set percentile refers to a specific percentile value obtained by sequentially decreasing the average value of the first voltage data.

[0076] Example 3. This example is a variation of Example 2. For example... Figure 6 As shown, step S500, which determines the first high-risk area based on the heat map, specifically includes the following steps:

[0077] S510 calculates the average first voltage data for each chip and all chips within a predetermined distance around it; similarly, the distances between chips are calculated with the center point of the chip as the reference. The specific predetermined distance can be determined based on the characteristics of factors that may affect chip quality in the manufacturing process. For example, a suitable predetermined distance can be determined based on factors such as potential mechanical damage and contamination damage.

[0078] S520: If the average value of the first voltage data of a chip is worse than the second threshold or the set percentile, the chip is considered to be located in the first high-risk area. In other words, if a cluster of chips with poor first voltage data is found around a certain chip, the chip is considered to be located in the first high-risk area. At this time, the first high-risk area is not necessarily a large area, but may be a collection of many small, scattered areas.

[0079] As a variation of this embodiment, the wafer can be divided into several grid-like or honeycomb-like regions; then the average first voltage data of all chips in each region is calculated, and the region with the poorest average first voltage data is identified as the first high-risk region.

[0080] Example 4. Based on the above examples, this example further includes a second target control value. The second target control value has a higher control stringency than the first target control value, and is used to further control chips within the first high-risk area. Since chips within the first high-risk area have a higher probability of failure, appropriately increasing the control stringency in these areas improves overall control efficiency and reduces the number of good chips that are incorrectly controlled.

[0081] As a variation of this embodiment, after reliability testing, the distribution of attenuation values ​​of the first voltage data within the wafer can be obtained to determine a second high-risk region; furthermore, the target control value includes a third target control value, which has a higher level of control stringency than the first target control value. This third target control value is used to further control the chips within the second high-risk region. For example, as... Figure 11 As shown in the figure (VTP Decay in the figure represents the decay value of the first voltage data), the reliability test adopted a high-temperature baking test at 85°C for 120 hours. The horizontal axis of the decay value distribution curve of the first voltage data is the distance of the annular region around the wafer center from the wafer center, and the vertical axis is the average value of the decay value of the first voltage data of the chip in each annular region. As can be seen from the figure, the chip at point C has a larger decay of the threshold voltage after the reliability test. Therefore, the wafer area corresponding to point C is regarded as the second high-risk area. Figure 11 Point C in the diagram is also a region near the edge of the wafer, therefore... Figure 9 The first high-risk area, which has a large number of reddish data points, also overlaps. This further illustrates that the edge area of ​​the wafer is a high-risk area, and the third target control value for the overlapping area can be set to be more stringent than both the first and second target control values.

[0082] When the target control value includes a second target control value, or further includes a third target control value, step S800 specifically includes the following steps:

[0083] S810: Obtain the first voltage data of all chips on the wafer to be controlled, and perform the first control using the first target control value;

[0084] S820, establishes a hotspot map of the first voltage data of the wafer to be controlled;

[0085] S830, based on the distribution hotspot map obtained in step S820, determine the first high-risk area in the chip concentration that failed the first control on the wafer to be controlled; see Example 3 for specific methods.

[0086] S840 uses the second target control value to perform a second control on the chip in the first high-risk area;

[0087] S850, when the target control value includes the third target control value, performs a third control on the chip in the second high-risk area using the third target control value.

[0088] The first high-risk area is determined based on the first voltage data of each wafer to be controlled, while the second high-risk area is directly adopted from the area determined after reliability testing, i.e., and Figure 11 The wafer edge region corresponding to point C in the diagram.

[0089] Example 5. This example is a memory chip early failure testing system, including a voltage data acquisition module, a reliability testing module, an analysis and calculation module, and a screening module. The voltage data acquisition module is used to acquire the voltage data of all chips on the wafer. The reliability testing module is used to perform reliability testing on the chips. The analysis and calculation module is used to determine the target control value according to the memory chip early failure screening method of any of the preceding embodiments. The screening module is used to perform early failure screening on the chips of the same batch of wafers to be controlled based on the target control value and the first voltage data that can be measured quickly.

[0090] The above description is merely a preferred embodiment and the technical principles employed in this application. Various obvious changes, readjustments, and substitutions can be made without departing from the concept of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. Where there is no conflict, the above embodiments and features in the embodiments can be combined with each other.

Claims

1. A method for screening early memory failures in memory chips, characterized in that, Including the following steps: Acquire the first voltage data of all chips on the wafer. The first voltage data is the worst threshold voltage of the chip before the reliability test. The worst threshold voltage is the worst data of the programming state threshold voltage. Establish the first voltage data distribution curve on the wafer; Based on the first voltage data distribution curve, failed chips and high-risk chips with a dispersion exceeding the first dispersion on the side with poorer first voltage data are screened out. The side with poorer first voltage data is the side of the first voltage data distribution curve where the threshold voltage or threshold voltage margin is less than a preset value. Establish a hotspot map of the distribution of the first voltage data on the wafer; Based on the heat map, a first high-risk region is determined where the failed chips and high-risk chips on the wafer are concentrated. Specifically including Step: Divide the wafer into a central region and several annular regions surrounding the central region; Calculate the average first voltage data of all chips in the central region and the average first voltage data of all chips in each annular region; designate regions where the average first voltage data is lower than a second threshold or lower than a set percentile as the first high-risk region; The high-risk chip and the chips in the first high-risk area are subjected to reliability testing, and the second voltage data of the chip after the test is obtained. The second voltage data is the threshold voltage corresponding to the first voltage data after the reliability test, or the second voltage data is the worst threshold voltage of the chip after the reliability test, or the second voltage data is the attenuation value of the first voltage data after the reliability test. The defective chip is determined based on the second voltage data; The target control value is determined based on the first voltage data of the defective chip, and is used to screen for early failure of wafer chips in the same batch.

2. The method for screening early memory failures in memory chips according to claim 1, characterized in that, The method for determining the first dispersion is either based on a set multiple of the variance of the first voltage data distribution curve, or based on a first threshold of the first voltage data. The chip is a NOR Flash memory chip or a NAND Flash memory chip.

3. The method for screening early memory failures in memory chips according to claim 1, characterized in that, The reliability testing includes accelerated aging testing; The method of determining the defective chip based on the second voltage data specifically includes the following steps: Based on the first voltage data and the second voltage data, a lifetime fitting extrapolation is performed to calculate the second voltage data threshold corresponding to the minimum lifespan of the chip product; and... Chips whose second voltage data is less than the second voltage data threshold are identified as unqualified chips.

4. The method for screening early memory failures in memory chips according to any one of claims 1 to 3, characterized in that, The method of determining the first high-risk area based on the heat map specifically includes the following steps: Calculate the average first voltage data for each chip and all chips within a set distance around it; If the average value of the first voltage data of the chip is less than the second threshold or less than the set percentile, then the chip is located in the first high-risk area.

5. The method for screening early memory failures in memory chips according to any one of claims 1 to 3, characterized in that, The target control value includes a first target control value, which is used to control the wafer chips in the same batch through the first voltage data; The first target control value is not less than the first voltage data of all the defective chips.

6. The method for screening early memory failures in memory chips according to claim 5, characterized in that, The target control value also includes a second target control value; The second target control value has a higher level of control than the first target control value, and the second target control value is used to control the chip in the first high-risk area.

7. The method for screening early memory failures in memory chips according to claim 6, characterized in that, The method also includes the step of, after the reliability test, acquiring the distribution of attenuation values ​​of the first voltage data within the wafer to determine a second high-risk area; The target control value also includes a third target control value, which has a higher level of control than the first target control value. The third target control value is used to control the chip in the second high-risk area.

8. A memory chip early failure testing system, characterized in that, It includes a voltage data acquisition module, a reliability testing module, an analysis and calculation module, and a screening module; The voltage data acquisition module is used to acquire voltage data of all chips on the wafer, the reliability testing module is used to perform reliability testing on the chips, the analysis and calculation module is used to determine the target control value according to the early memory failure screening method of memory chips according to any one of claims 1 to 7, and the screening module is used to perform early failure screening of wafer chips in the same batch according to the target control value.

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