An Inverted Soldering Bump Limiting Structure and Its Preparation Method

Abstract

The present invention relates to a flip-chip bump limiting structure and a preparation method thereof. The flip-chip bump limiting structure provides a substrate, and a bump limiting structure is formed on the surface of the substrate; an insulating layer is formed on the surface of the substrate and the surface of the bump limiting structure, and the insulating layer completely covers the surface of the substrate and the surface of the bump limiting structure; a metal layer is formed above the insulating layer, and the metal layer includes metal wirings and a limiting structure metallization layer; the metal wirings are located on the insulating layer directly above the substrate and are connected to the limiting structure metallization layer. The bump limiting structure of the present invention enables the controllability of the height consistency and the controllability of the flatness of the substrate, ensuring a high yield rate in flip-chip soldering quality.

Description

Technical Field

[0001] The present invention belongs to the field of electronic packaging, and particularly relates to a flip-chip bump limiting structure and a preparation method thereof. Background Art

[0002] With the development trend of electronic packaging towards miniaturization and high density, the integration level of semiconductor devices has been continuously improved, the number of units has increased, the required electrical connection leads have also increased accordingly, the number of I / O interfaces of the chip has also increased, and the size has become smaller and smaller. This has promoted the emergence of chip flip-chip packaging technology. Through bumps, the vertical space of the device is expanded. It has the advantages of high alignment accuracy, small device volume, small interconnect parasitic parameters, and fast transmission rate, and is a representative of contemporary advanced packaging forms.

[0003] The flip-chip interconnection technology is widely used in high-performance and consumer electronic products. The bumps in flip-chip solder chips are used to interconnect the chips or substrates to achieve electrical interconnection, signal transmission, physical support, and heat conduction, etc. Therefore, the research on bumps is particularly important. The existing bump connection technologies are mainly reflow soldering, thermocompression bonding, cold pressure welding, etc. Their common feature is to achieve the infiltration of bumps and pads by applying pressure or energy (heating) to the bumps, so as to achieve the interconnection between chips. Excessive pressure and energy will cause bump breakage, while insufficient pressure and energy will lead to poor interconnection effect or even chip delamination. Therefore, higher precision, reasonable bonding pressure and speed are required in chip bonding, which puts forward more requirements for bump protection and bonding process control during chip bonding.

[0004] At present, there has been some research on bump limiting structures, mainly by depositing metals with higher hardness to form limiting structures. However, its process is complex, the number of metal deposition process layers needs to be increased, which improves the process difficulty. At the same time, the height of the limiting structure obtained in this way is often only a few microns thick, which also limits the bump height and cannot play a limiting and protecting role for bumps of dozens or even hundreds of microns. Therefore, it is necessary to find a bump limiting technology with simple process, controllable height, and bump protection. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a flip-chip bump limiting structure and a preparation method thereof, in which the height consistency of the bump limiting structure is controllable, and the flatness of the substrate is controllable, so as to ensure a high yield rate of flip-chip soldering quality.

[0006] The present invention provides a flip-chip bump limiting structure,

[0007] A substrate is provided, and a bump limiting structure is formed on the surface of the substrate;

[0008] An insulating layer is formed on the surface of the substrate and the surface of the bump limiting structure, and the insulating layer completely covers the surface of the substrate and the surface of the bump limiting structure;

[0009] A metal layer is formed above the insulating layer. The metal layer includes metal wirings and a limiting structure metallization layer. Among them, the limiting structure metallization layer is located inside the bump limiting structure. The metal wirings are on the insulating layer directly above the substrate and are connected to the limiting structure metallization layer.

[0010] The substrate is a silicon wafer or other substrate materials that can be etched and processed.

[0011] The bump limiting structure is formed into a square dam structure with a bevel of 40° - 60° through wet etching; or a hollow cylindrical structure (including a cylinder, a square column, etc.) is formed through dry etching.

[0012] The height of the bump limiting structure is from 1 micron to 2000 microns, and the height is controllable and does not limit the height of the bump.

[0013] The insulating layer is formed of other non-organic materials such as silicon dioxide or silicon nitride. Further, a silicon dioxide layer can be formed by thermal oxidation or an insulating material such as silicon nitride can be deposited to form the insulating layer.

[0014] The metal layer is formed by sputtering metal and patterning. Preferably, the sputtered metal layer can be electroplated to thicken. The metal is Cu, Al, Nb or other metals suitable for deposition processes (including superconducting metals). Among them, the limiting structure is for flip-chip interconnection limitation and generally does not need to be metallized. If the limiting structure needs to be metallized, it can be formed synchronously with the substrate metal wirings and can be formed of the same material.

[0015] The present invention also provides a preparation method of a flip-chip bump limiting structure, including the following steps:

[0016] (1) Provide a substrate and clean the substrate;

[0017] (2) Form a bump limiting structure on the surface of the substrate through wet etching or dry etching;

[0018] (3) Perform thermal oxidation treatment on the surface of the substrate to form an insulating layer;

[0019] (4) Sputter metal on the insulation and pattern it to form a metal layer;

[0020] (5) Etch on the metal layer to form a limiting structure metallization layer and metal wirings.

[0021] The present invention also provides an application of a flip-chip bump limiting structure in flip-chip soldering.

[0022] It includes the following steps:

[0023] (1) Fill solder bumps at the positions of the bump limiting structures on the substrate;

[0024] (2) On the substrate of the bump limiting structure, the substrate and the flip chip are bonded by a flip chip bonder under normal pressure and at room temperature through a cold pressure welding method. The flip chip is bonded to the substrate by the solder bumps in the bump limiting structure and is electrically connected to the metallization layer of the limiting structure on the substrate. Then, electrical signal circuits are formed by interconnecting with other bumps through metal wiring, forming a flip chip bonding interconnect structure.

[0025] (3) In the interconnect structure formed by the substrate and the flip chip, fill and cure with underfill adhesive.

[0026] Beneficial effects

[0027] (1) The bump limiting structure of the present invention is directly formed by microfabrication on the substrate. The process method is simple and can be obtained by etching and metal deposition methods.

[0028] (2) The height consistency of the bump limiting structure of the present invention can be controlled by etching, and the flatness of the substrate can be controlled, ensuring a high yield rate of flip chip bonding quality.

[0029] (3) The bump limiting structure of the present invention defines the positions of solder balls, avoiding solder bridging with each other and improving the mounting yield rate.

[0030] (4) The bump limiting structure of the present invention can provide high support and has strong robustness to the pressure of flip chip bonding.

[0031] (5) The bump limiting structure of the present invention can protect the solder balls. After formation, the solder balls have good shape retention, reducing the risk of short circuit between adjacent solder balls caused by solder ball collapse.

[0032] (6) The shape of the bump limiting structure of the present invention is controllable and optimized, and thus the solder volume can be calculated to ensure welding reliability. Description of the Drawings

[0033] Figures 1 to 7 It shows a schematic diagram of the preparation process of the present invention;

[0034] Figures 8 to 11 It is a schematic diagram of the bump limiting structure of each optional embodiment;

[0035] Description of the Main Component Symbols:

[0036] 101 - Substrate

[0037] 102 - Bump Limiting Structure

[0038] 201 - Insulating Layer

[0039] 301 - Metal layer

[0040] 302 - Metallized layer of the limiting structure

[0041] 303 - Metal wiring

[0042] 401 - Solder bump

[0043] 402 - Flip chip

[0044] 501 - Underfill Detailed implementation manners

[0045] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0046] Embodiment 1

[0047] This embodiment provides a bump limiting structure, and its preparation method is as follows:

[0048] (1) Provide a substrate 101 and perform conventional cleaning on the substrate 101.

[0049] As an example, the substrate 101 is an n-type (100) silicon wafer.

[0050] (2) As shown in Figure 1 , form a bump limiting structure 102 on the surface of the substrate 101.

[0051] As an example, the bump limiting structure 102 is obtained by wet etching to form an annular dam structure.

[0052] (3) As shown in Figure 2 , form an insulating layer 201 on the substrate 101.

[0053] As an example, perform thermal oxidation treatment on the surface of the substrate 101 including the bump limiting structure 102 to form a surface silicon dioxide layer.

[0054] (4) As shown in Figure 3 , sputter metal on the insulating layer 201 to form a metal layer 301.

[0055] As an example, the metal layer 301 is TiW / Cu, where TiW is used as an adhesion layer and Cu is used as a seed layer.

[0056] (5) As shown in Figure 4As shown, a limiting structure metallization layer 302 and metal wirings 303 are etched and formed on the metal layer 301.

[0057] As an example, the limiting structure metallization layer 302 is located inside the bump limiting structure 102. The metal wirings 303 are located on the insulating layer 201 directly above the substrate 101 and are connected to the limiting structure metallization layer 302. Among them, the limiting structure metallization layer 302 and the metal wirings 303 are formed simultaneously and made of the same material. An interconnection line pattern is lithographically defined on the metal layer 301; after lithographic definition, the metal layer 301 can be electroplated to a certain thickness to obtain the limiting structure metallization layer 302 and the metal wirings 303; the photoresist is removed, and the metal layer 301 is etched to obtain the limiting structure metallization layer 302 and the metal wirings 303.

[0058] (6) As Figure 5 shown, solder bumps 401 are filled at the positions of the bump limiting structures 102 on the substrate 101.

[0059] As an example, the material of the solder bumps 401 is indium. Indium has excellent cold pressing performance, can wet many metals, and the appropriate solder filling amount can be calculated, and the indium solder bumps can be selectively reflowed.

[0060] (7) As Figure 6 shown, on the substrate 101 of the bump limiting structure 102, the solder bumps 401 are aligned and bonded with the flip chip 402.

[0061] As an example, the substrate 101 and the flip chip 402 are bonded by a flip chip bonder at normal pressure and room temperature through a cold pressure welding method. The solder bumps 401 in the bump limiting structure 102 bond and connect the flip chip 402 and the substrate 101, are electrically connected to the limiting structure metallization layer 302 on the substrate 101, and then the metal wirings 303 are interconnected with other bumps to form an electrical signal loop, forming a flip chip bonding interconnection structure.

[0062] (8) As Figure 7 shown, in the interconnection structure formed by the substrate 101 and the flip chip 402, underfill 501 is filled and cured.

[0063] According to the bump limiting structure and its preparation method provided by the embodiment, the deformation examples of the embodiment are discussed. In the entire drawings and the described embodiments, the same reference signs are used to designate the same elements, that is, the same elements as those in Figures 1 to 7 shown in the embodiment. Specifically, the structures, materials, and thicknesses of the insulating layer 201 and the metal layer 301 in these embodiments can also be basically the same as those Figures 1 to 7 shown therein.

[0064] InFigure 8 Among them, it is the bump limiting structure in the above-mentioned embodiment. The bump limiting structure 102 is a square dam structure, and the limiting structure metallization 302 and the metal wiring 303 are interconnected through an opening. The position and size of the opening can be adjusted by the lithography pattern during lithography definition. For example Figure 9 , the opening position of the bump limiting structure 102 can be adjusted to flexibly realize the interconnection and wiring of the limiting structure metallization layer 302 and the metal wiring 303. In Figure 10 , 11 Among them, the bump limiting structures 102 are respectively a hollow cylinder and a hollow square column structure, which can be prepared by processes such as deep silicon etching. Different from Figure 8 the side walls of the bump limiting structure 102 are basically perpendicular, and the shape structure, side wall opening position and size of the bump limiting structure 102 can also be flexibly adjusted according to the requirements of the flip chip to realize the cold flip-chip soldering technology.

[0065] Obviously, the described embodiments are only the basic concepts in the present invention, rather than an exhaustive list of all embodiments. The various detailed parameters and material types can be modified and adjusted according to actual needs and applications without departing from the spirit of the present invention.

Claims

1. A flip-chip bump limiting structure, characterized in that: A substrate is provided, and a bump limiting structure is formed on the surface of the substrate. The bump limiting structure has a square dam structure; An insulating layer is formed on the surface of the substrate and the surface of the bump limiting structure. The insulating layer completely covers the surface of the substrate and the surface of the bump limiting structure; A metal layer is formed above the insulating layer. The metal layer includes metal wiring and a limiting structure metallization layer. Among them, the limiting structure metallization layer is located inside the bump limiting structure and serves as a pad for solder bumps. The metal wiring is on the insulating layer directly above the substrate and is connected to the limiting structure metallization layer.

2. The flip-chip bump limiting structure according to claim 1, wherein: The substrate is a silicon wafer or other substrate material that can be etched and processed.

3. The flip-chip bump limiting structure according to claim 1, wherein: The bump limiting structure is formed by wet etching to form a square dam structure with a bevel of 40° to 60°.

4. The flip-chip bump limiting structure according to claim 1, wherein: The height of the bump limiting structure is 1 micron to 2000 microns.

5. The flip-chip bump limiting structure according to claim 1, wherein: The material of the insulating layer is silicon dioxide or silicon nitride.

6. The flip-chip bump limiting structure according to claim 1, characterized in that: The metal layer is formed by sputtering metal and patterning.

7. A preparation method of the flip-chip bump limiting structure according to claim 1, comprising the following steps: (1) Provide a substrate and clean the substrate; (2) Form a bump limiting structure on the surface of the substrate by wet etching or dry etching; (3) Perform thermal oxidation treatment on the surface of the substrate to form an insulating layer; (4) Sputter metal on the insulator and pattern it to form a metal layer; (5) Etch the metal layer to form a limiting structure metallization layer and metal wiring.

8. An application of the flip-chip bump limiting structure according to claim 1 in flip-chip bonding.

9. The application according to claim 8, characterized in that: It includes the following steps: (1) Fill solder bumps at the positions of the bump limiting structures on the substrate; (2) On the substrate of the bump limiting structure, the substrate and the flip-chip are bonded by a flip-chip bonder through a cold pressure welding method at normal pressure and room temperature. The solder bumps in the bump limiting structure bond and connect the flip-chip and the substrate, electrically connect to the limiting structure metallization layer on the substrate, and then the metal wiring is interconnected with other bumps to form an electrical signal loop, forming a flip-chip bonding interconnection structure; (3) In the interconnection structure formed by the substrate and the flip-chip, fill and cure with underfill.

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