Diode device and method of making the same

Abstract

The application provides a diode device and a manufacturing method thereof. The diode device comprises a cathode metal layer, an N+ substrate located above the cathode metal layer, an N-drift region epitaxially formed above the N+ substrate, a plurality of high-impedance cell structures arranged at intervals on the upper part of the N-drift region, each high-impedance cell structure comprising two P+ ion implantation regions and an impedance region between the two P+ ion implantation regions, and an anode metal layer located above the N-drift region. The application can enhance the surge capacity of the diode device.

Description

Technical Field

[0001] This invention relates to the field of diode chip technology, specifically to a diode device and a method for manufacturing a diode device. Background Technology

[0002] Compared to other semiconductor materials such as silicon, silicon carbide (SiC) has a wider bandgap, a higher critical breakdown electric field, and greater saturation drift velocity and thermal conductivity. These superior material properties make SiC devices extremely promising for applications in high-frequency, high-temperature, and radiation-resistant fields. Currently, due to the applications of charging piles and photovoltaics in production and daily life, SiC Schottky diodes require sufficiently high forward surge capability. One of the main bottlenecks currently facing SiC Schottky diodes is how to improve the surge capability of the devices. Summary of the Invention

[0003] To solve the above-mentioned technical problems, the present invention provides a diode device and a method for manufacturing the same, which can enhance the surge capability of the diode device.

[0004] The technical solution adopted in this invention is as follows:

[0005] A diode device includes: a cathode metal layer; an N+ substrate located on the cathode metal layer; an N-drift region epitaxially formed on the N+ substrate; multiple high-impedance cell structures arranged at intervals on the upper part of the N-drift region, each high-impedance cell structure including two P+ type ion implantation regions and an impedance region located between the two P+ type ion implantation regions; and an anode metal layer located on the N-drift region.

[0006] The impedance region is an N-region, the doping concentration of the impedance region is less than the doping concentration of the N-drift region, and the depth of the impedance region is the same as the depth of the P+ type ion implantation region.

[0007] The impedance region includes two P+ type ion layers, which are located within the N-drift region and are spaced apart. The upper P+ type ion layer is connected to the first of the two P+ type ion implantation regions but not connected to the second. The lower P+ type ion layer is connected to the second of the two P+ type ion implantation regions but not connected to the first.

[0008] A method for fabricating a diode device includes the following steps: epitaxially forming an N-drift region on the surface of an N+ substrate; photolithographically defining a P+ type ion implantation region within the N-drift region, and implanting aluminum ions of different energies to form the P+ type ion implantation region; photolithographically defining an impedance region within the N-drift region, and implanting aluminum ions of different energies; performing high-temperature annealing and deposition processes on the N-drift region and the N+ substrate; photolithographically defining a metal electrode region, and etching the metal electrode region to form the diode device.

[0009] The impedance region is an N-region, the doping concentration of the impedance region is less than the doping concentration of the N-drift region, and the depth of the impedance region is the same as the depth of the P+ type ion implantation region.

[0010] The impedance region includes two P+ type ion layers, which are located within the N-drift region and are spaced apart. The upper P+ type ion layer is connected to the first of the two P+ type ion implantation regions but not connected to the second. The lower P+ type ion layer is connected to the second of the two P+ type ion implantation regions but not connected to the first.

[0011] The implantation energy of the lower P+ type ion layer is greater than that of the upper P+ type ion layer.

[0012] The beneficial effects of this invention are:

[0013] This invention fixes an N+ substrate on a cathode metal layer and epitaxially forms an N-drift region. Multiple high-impedance cell structures are arranged alternately on the upper part of the N-drift region, and each high-impedance cell structure includes two P+ type injection regions and an impedance region located between the two P+ type injection regions. Then, an anode metal layer is fixed on the N-drift region. Thus, by setting the high-impedance cell structure, the resistance of the current path in a certain area of ​​the diode device can be increased, thereby enhancing the surge capability of the diode device. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a diode device according to an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of a diode device with an N-region impedance region according to an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the impedance region of a diode device according to another embodiment of the present invention, which consists of two layers of P+ type ion layers.

[0017] Figure 4 This is a flowchart illustrating a method for fabricating a diode device according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, the diode device of this embodiment includes: a cathode metal layer 10, an N+ substrate 20, an N- drift region 30, a high-impedance cell structure 40, and an anode metal layer 50. The N+ substrate 20 is located on the cathode metal layer 10, the N- drift region 30 is epitaxially formed on the N+ substrate 20, and there are multiple high-impedance cell structures 40. The multiple high-impedance cell structures 40 are arranged alternately on the upper part of the N- drift region 30. Each high-impedance cell structure 40 includes two P+ type ion implantation regions 41 and an impedance region 42 located between the two P+ type ion implantation regions 41. The anode metal layer 50 is located on the N- drift region 30.

[0020] In one embodiment of the present invention, the N-drift region 30 may contain only high-impedance cell structures 40, with multiple high-impedance cell structures 40 repeating adjacently within the N-drift region 30. In another embodiment of the present invention, the N-drift region 30 may contain ordinary cells, meaning that at least two high-impedance cell structures 40 may be separated by one or more ordinary cells. The structure of the ordinary cells is a common cell structure in the prior art.

[0021] In one embodiment of the present invention, the implantation depth of the P+ type ion implantation region 41 in the high impedance cell structure 40 is basically the same as the implantation depth of the P+ type ion implantation region 41 in the ordinary cell, and the spacing width between every two P+ type ion implantation regions 41 is basically the same.

[0022] In one embodiment of the present invention, such as Figure 2 As shown, impedance region 42 can be a low-doped N-region, and the doping concentration of impedance region 42 is less than that of N-drift region 30. Figure 2The impedance region 42 can be represented as N-, and its depth is the same as that of the P+ type ion implantation region 41. This increases the resistance of the path from the anode metal layer 50 to the bottom of the P+ type ion implantation region 41, making its resistance ratio with that of the N- drift region 30 larger. This allows the voltage difference between the bottom two sides of the P+ type ion implantation region 41 to reach the PN junction turn-on barrier height more quickly under high current conditions, thereby enhancing the surge capability of the diode device. Simulation methods can confirm that the depth of the impedance region 42 is the same as that of the P+ type ion implantation region 41.

[0023] In another embodiment of the invention, such as Figure 3 As shown, the impedance region 42 may also include two P+ type ion layers, which can be represented by P+U and P+D respectively. The two P+ type ion layers are located within the N-drift region 30, and there is a certain gap between the two P+ type ion layers. The upper P+ type ion layer P+U is connected to the first of the two P+ type ion implantation regions 41 and is not connected to the second of the two P+ type ion implantation regions 41. The lower P+ type ion layer P+D is connected to the second of the two P+ type ion implantation regions 41 and is not connected to the first of the two P+ type ion implantation regions 41.

[0024] In one embodiment of the present invention, the implantation energy of the lower P+ type ion layer P+D is greater than the implantation energy of the upper P+ type ion layer P+U.

[0025] In one embodiment of the present invention, the upper surface of the N-drift region 30 forms a Schottky contact with the anode metal layer 50, the upper surface of the P+ type ion implantation region 41 forms an ohmic contact with the anode metal layer 50, and the lower surface of the N+ substrate 20 forms an ohmic contact with the cathode metal layer 10.

[0026] According to an embodiment of the present invention, in the diode device, by fixing an N+ substrate on a cathode metal layer and epitaxially forming an N- drift region, multiple high-impedance cell structures are arranged alternately on the upper part of the N- drift region, and each high-impedance cell structure includes two P+ type injection regions and an impedance region located between the two P+ type injection regions. Then, an anode metal layer is fixed on the N- drift region. Thus, by setting the high-impedance cell structure, the resistance of the current path in a part of the diode device can be increased, thereby enhancing the surge capability of the diode device.

[0027] Corresponding to the diode device in the above embodiments, the present invention also proposes a method for manufacturing a diode device.

[0028] like Figure 4 As shown, the method for fabricating a diode device according to an embodiment of the present invention includes the following steps:

[0029] S1, an N- drift region is epitaxially formed on the surface of an N+ substrate.

[0030] S2, P+ type ion implantation region is defined by photolithography in N- drift region, and aluminum ions of different energies are implanted to form P+ type ion implantation region.

[0031] In one embodiment of the present invention, the implantation depth of the P+ type ion implantation regions is substantially the same, and the spacing width between every two P+ type ion implantation regions is also substantially the same.

[0032] S3, an impedance region is defined by photolithography within the N-drift region, and aluminum ions of different energies are injected.

[0033] In one embodiment of the present invention, aluminum ions of different energies or other P-type materials with insulating properties can be implanted to form an impedance region. The impedance region can be an N-region, the doping concentration of the impedance region is less than the doping concentration of the N-drift region, and the depth of the impedance region is the same as the depth of the P+ type ion implantation region. The same depth of the impedance region and the P+ type ion implantation region can be confirmed by simulation.

[0034] In another embodiment of the present invention, aluminum ions or other P-type materials with insulating properties of different energies can be implanted to form an impedance region. The impedance region may also include two P+ type ion layers, which are located within the N-drift region and are spaced apart. The upper P+ type ion layer is connected to the first of the two P+ type ion implantation regions but not to the second. The lower P+ type ion layer is connected to the second of the two P+ type ion implantation regions but not to the first. The implantation energy of the lower P+ type ion layer must be greater than that of the upper P+ type ion layer.

[0035] S4, high-temperature annealing and deposition processes are performed on the N- drift region and the N+ substrate.

[0036] Specifically, firstly, a carbon layer is coated on the lower surface of the N+ substrate and the upper surface of the N- drift region, and then annealed at a high temperature to activate the implanted aluminum ions. Next, after removing the carbon layer, an insulating dielectric layer is deposited on the silicon carbide surface. Hole regions are defined by photolithography, and the insulating dielectric layer within the hole regions is etched away. Finally, a metal layer is deposited on the hole regions and the remaining insulating dielectric layer.

[0037] S5, photolithography defines the metal electrode region, and etching is performed on the metal electrode region to form a diode device.

[0038] In summary, the method for fabricating a diode device according to embodiments of the present invention involves epitaxially forming an N-drift region on the surface of an N+ substrate, photolithographically defining a P+ type ion implantation region and implanting aluminum ions of different energies, photolithographically defining an impedance region within the N-drift region and implanting aluminum ions of different energies, then performing high-temperature annealing and deposition processes on the N-drift region and the N+ substrate, and finally photolithographically defining a metal electrode region and etching the metal electrode region to form a diode device. Thus, by implanting aluminum ions of different energies, the resistance of the current path in a portion of the diode device can be increased, thereby enhancing the surge capability of the diode device.

[0039] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0040] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0041] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0042] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0043] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0044] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0045] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0046] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0047] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0048] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A diode device, characterized in that, include: Cathode metal layer; An N+ substrate, wherein the N+ substrate is located on the cathode metal layer; The N-drift region is epitaxially formed on the N+ substrate; A high-impedance cell structure, wherein there are multiple high-impedance cell structures, and the multiple high-impedance cell structures are arranged alternately on the upper part of the N-drift region. Each high-impedance cell structure includes two P+ type ion implantation regions and an impedance region located between the two P+ type ion implantation regions. An anode metal layer, which is located above the N-drift region. The impedance region includes two P+ type ion layers, which are located within the N-drift region and are spaced apart. The upper P+ type ion layer is connected to the first of the two P+ type ion implantation regions but not connected to the second. The lower P+ type ion layer is connected to the second of the two P+ type ion implantation regions but not connected to the first.

2. The method for manufacturing a diode device according to claim 1, characterized in that, Includes the following steps: The N- drift region is epitaxially formed on the surface of the N+ substrate; A P+ type ion implantation region is defined by photolithography within the N-drift region, and aluminum ions of different energies are implanted to form the P+ type ion implantation region. The impedance region is defined by photolithography within the N-drift region, and aluminum ions of different energies are implanted. The N-drift region and the N+ substrate are subjected to high-temperature annealing and deposition processes; Photolithography defines the metal electrode region, and etching is performed on the metal electrode region to form the diode device.

3. The method for manufacturing a diode device according to claim 2, characterized in that, The injection energy of the lower P+ type ion layer is greater than that of the upper P+ type ion layer.

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