Light-emitting diode and light-emitting device

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and relates to a light-emitting diode (LED) comprising a semiconductor stack, the semiconductor stack comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence, the semiconductor stack having a plurality of through holes, each of which extends downward from the second semiconductor layer to the first semiconductor layer. When viewed from above the LED toward the semiconductor stack, an xy coordinate system is established with the center of the semiconductor stack as the origin, with a first pattern formed by offsetting the through holes by a first distance on either side of the x-axis and a second distance on either side of the y-axis, and a second pattern formed by offsetting the through holes by a third distance on either side of the x-axis and a fourth distance on either side of the y-axis, wherein a first spacing between the through holes within the first pattern is greater than a second spacing between the through holes between the first and second patterns. This enhances carrier conduction capability, equalizes local current density, avoids thermal effects caused by current concentration, prevents direct electrical damage from puncturing a PN junction, and improves the ESD resistance of the LED.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a light emitting diode and a light emitting device. Background Art

[0002] A light-emitting diode (LED) is a semiconductor light-emitting element typically made of semiconductors such as GaN, GaAs, GaP, and GaAsP. Its core is a PN junction, which is responsible for the light-emitting properties of the diode. LEDs offer advantages such as high luminous intensity, high efficiency, compact size, and long life, making them considered one of the most promising light sources. They are widely used in lighting, surveillance and control, high-definition broadcasting, high-end cinemas, office displays, interactive conferences, and virtual reality.

[0003] In recent years, the enormous application value of ultraviolet LEDs (UV LEDs), especially deep ultraviolet LEDs, has attracted great attention and become a new research hotspot. In the process of realizing the present invention, the inventors found that there are at least the following problems in the existing technology: Due to the serious light absorption problem of UV-band luminescent materials, UV LEDs require thinner wafers to emit light compared to conventional LED products, which will cause the P-type semiconductor layer, N-type semiconductor layer and light-emitting layer (MQW) to be relatively weak; at the same time, because the luminescent material of the P-type semiconductor layer is highly doped, it requires a low-temperature growth environment, and the atomic migration performance is insufficient, which in turn forms various defects, and the defects easily accelerate the formation of hot spots; if the thickness of the luminescent material is increased by directly imitating conventional LEDs, the excessive light-to-heat conversion will increase the junction temperature and reduce the life of the LED. All of the above problems have brought severe challenges to the anti-ESD (Electro-Static discharge) ability of UV LEDs.

[0004] It should be noted that the information disclosed in this background technology section is only intended to increase understanding of the overall background of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The present invention provides a light-emitting diode, comprising a semiconductor stack. The semiconductor stack comprises a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence. The semiconductor stack has a plurality of through holes, each of which extends downward from the second semiconductor layer to the first semiconductor layer, exposing a portion of the surface of the first semiconductor layer. A coordinate system is established with the center of the semiconductor stack as the origin, with the line perpendicular to the first side of the semiconductor stack as the x-axis of the coordinate system, and the line perpendicular to the second side of the semiconductor stack as the y-axis of the coordinate system. The first side is perpendicular to and connected to the second side. The first side is offset by a first distance on both sides of the x-axis and a second distance on both sides of the y-axis to form a first pattern. The second side is offset by a third distance on both sides of the x-axis and a fourth distance on both sides of the y-axis to form a second pattern. The third and fourth distances are both greater than the first and second distances. Adjacent through holes within the first pattern have a first spacing, and adjacent through holes between the first and second patterns have a second spacing, with the first spacing being greater than the second spacing.

[0006] The present invention also provides a light-emitting diode, which includes a semiconductor stack. The semiconductor stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence. The semiconductor stack has a plurality of through holes, each of which extends downward from the second semiconductor layer to the first semiconductor layer, and each through hole exposes a portion of the surface of the first semiconductor layer. Wherein, looking down at the semiconductor stack from above the light-emitting diode, the light-emitting diode has a pin region, the pin region is located at the center of the semiconductor stack, the through hole avoids the pin region, and a first circle is constructed with the distance between the centers of two adjacent through holes both close to the pin region as the radius and the center of one of the through holes as the center of the circle. A second circle is constructed with the distance between the centers of two adjacent through holes both close to the edge of the semiconductor stack as the radius and the center of one of the through holes as the center of the circle, and the first circle is larger than the second circle.

[0007] The present invention also provides a light-emitting device, which can adopt the light-emitting diode provided by any of the above embodiments.

[0008] An embodiment of the present invention provides a light-emitting diode and a light-emitting device that can enhance carrier conduction capability, thereby equalizing local current density, avoiding thermal effects caused by concentrated current, preventing the formation of melting holes or burn-through in the light-emitting layer, and avoiding direct electrical damage and direct breakdown of the PN junction, thereby improving the ESD resistance of the light-emitting diode.

[0009] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 is a schematic top view of the structure of a light emitting diode provided by the first embodiment of the present invention;

[0012] Figure 2 It is along Figure 1 A schematic longitudinal cross-sectional view taken along the interception line FF;

[0013] Figure 3 2. It is a schematic diagram comparing the thermal resistance curves of the conventional structure and the structure of the present invention;

[0014] Figure 4 Schematic diagram of the effect of the ratio of the first radius to the rated current of the structure of the present invention on the electro-optical conversion efficiency;

[0015] Figure 5 is a schematic top view of the structure of a light emitting diode provided by a second embodiment of the present invention;

[0016] Figure 6 It is along Figure 5 A schematic longitudinal cross-sectional view taken along the interception line FF;

[0017] Figure 7 is a schematic structural diagram of a boss offset provided by another embodiment of the present invention;

[0018] Figure 8 is a schematic structural diagram of a recessed structure provided in another embodiment of the present invention;

[0019] Figure 9 It is a schematic diagram of a partial structure in which a covering electrode is provided at a boss provided by another embodiment of the present invention;

[0020] Figures 10 to 13 yes Figure 5 The schematic diagram of the structure of the light emitting diode at each stage of the manufacturing process is shown;

[0021] Figure 14 is a schematic top view of the structure of a light emitting diode provided by a third embodiment of the present invention;

[0022] Figure 15 It is along Figure 14 A schematic longitudinal cross-sectional view taken along the interception line FF;

[0023] Figure 16 yes Figure 5Schematic diagram of the light emitting diode shown in the coordinate system;

[0024] Figure 17 yes Figure 5 A schematic diagram of a light emitting diode is shown with a first circle and a second circle;

[0025] Figure 18 is a schematic diagram of a through-hole layout structure provided by another embodiment of the present invention;

[0026] Figure 19 It is a schematic diagram comparing the voltage and current characteristic curves of the conventional structure and the structure of the present invention.

[0027] Reference numerals:

[0028] 10-substrate; 12-semiconductor stack; 121-first semiconductor layer; 122-light-emitting layer; 123-second semiconductor layer; 14-through hole; 16-boss; 17-groove structure; 21-first electrode; 22-second electrode; 24-cooling zone; 26-covering electrode; 31-first insulating layer; 32-second insulating layer; 41-first protective electrode; 42-second protective electrode; 51-first pad; 52-second pad; 61-first opening; 62-second opening; 63-third opening; 64-fourth Opening; 71-first side; 72-second side; 81-first figure; 82-second figure; 83-third figure; 90-thrust pin area; 91-first circle; 92-second circle; R1-first radius; R2-second radius; R3-third radius; R4, R5-radius; L1-first spacing; L2-second spacing; L3-third spacing; D-length of cooling zone; X1-first distance; X2-second distance; X3-third distance; X4-fourth distance; X5-fifth distance; X6-sixth distance. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0030] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof all mean "at least including".

[0031] See also Figure 1 and Figure 2 , Figure 1 is a schematic top view of the light emitting diode provided by the first embodiment of the present invention, Figure 2 It is along Figure 1 A first embodiment of the present invention provides a light emitting diode. As shown in the figure, the light emitting diode may include a substrate 10, a semiconductor stack 12, a first electrode 21, and a second electrode 22.

[0032] The substrate 10 may be an insulating substrate. Preferably, the substrate 10 may be made of a transparent material or a translucent material. In the illustrated embodiment, the substrate 10 is a sapphire substrate. In some embodiments, the substrate 10 may be a patterned sapphire substrate, but the present patent is not limited thereto. The substrate 10 may also be made of a conductive material or a semiconductor material. For example, the substrate 10 material may include at least one of silicon carbide, silicon, magnesium aluminum oxide, magnesium oxide, lithium aluminum oxide, aluminum gallium oxide, and gallium nitride. In some embodiments, the substrate 10 may be thinned or removed to form a thin film light emitting diode.

[0033] The semiconductor stack 12 is provided on the substrate 10. The semiconductor stack 12 includes a first semiconductor layer 121, a light emitting layer 122, and a second semiconductor layer 123 stacked in sequence on the substrate 10. In other words, the first semiconductor layer 121 is located between the substrate 10 and the light emitting layer 122, and the light emitting layer 122 is located between the first semiconductor layer 121 and the second semiconductor layer 123.

[0034] The first semiconductor layer 121 may be an N-type semiconductor layer that can provide electrons to the light-emitting layer 122 under the action of a power source. In some embodiments, the first semiconductor layer 121 includes an N-type doped nitride layer. The N-type doped nitride layer may include one or more N-type impurities of Group IV elements. The N-type impurities may include one or a combination of Si, Ge, and Sn. In some embodiments, a buffer layer may be provided between the first semiconductor layer 121 and the substrate 10 to reduce the lattice mismatch between the substrate 10 and the first semiconductor layer 121. The buffer layer may include an unintentionally doped GaN layer (un-doped GaN, abbreviated as: u-GaN) or an unintentionally doped AlGaN layer (un-doped AlGaN, abbreviated as: u-AlGaN). The first semiconductor layer 121 may also be connected to the substrate 10 via an adhesive layer.

[0035] The light-emitting layer 122 may be a quantum well structure (Quantum Well, abbreviated as QW). In some embodiments, the light-emitting layer 122 may also be a multiple quantum well structure (Multiple Quantum Well, abbreviated as MQW), wherein the multiple quantum well structure includes multiple quantum well layers (Well) and multiple quantum barrier layers (Barrier) alternately arranged in a repeated manner, for example, it may be a multiple quantum well structure of GaN / AlGaN, InAlGaN / InAlGaN or InGaN / AlGaN. In addition, the composition and thickness of the well layer in the light-emitting layer 122 determine the wavelength of the generated light. In order to improve the luminous efficiency of the light-emitting layer 122, it can be achieved by changing the depth of the quantum well, the number of layers, thickness and / or other features of the paired quantum wells and quantum barriers in the light-emitting layer 122. In some embodiments, the light-emitting diode is an ultraviolet light-emitting diode. The light-emitting wavelength range of the light-emitting diode can be 220 to 385 nm.

[0036] The second semiconductor layer 123 can be a P-type semiconductor layer, which can provide holes to the light-emitting layer 122 under the action of a power supply. In some embodiments, the second semiconductor layer 123 includes a P-type doped nitride layer. The P-type doped nitride layer may include one or more P-type impurities. The P-type impurities may include one or a combination of Mg, Zn, and Be. The second semiconductor layer 123 can be a single-layer structure or a multi-layer structure having different compositions. In addition, the setting of the epitaxial structure is not limited to this, and other types of epitaxial structures can be selected based on actual needs.

[0037] The semiconductor stack 12 has a plurality of through holes 14, each of which extends downward from the second semiconductor layer 123 to the first semiconductor layer 121, and each through hole 14 exposes a portion of the surface of the first semiconductor layer 121. The through holes 14 are used to provide the first electrode 21. Looking down at the semiconductor stack 12 from above the light-emitting diode, the plurality of through holes 14 can be arranged in an array, and the plurality of through holes 14 are located within the second semiconductor layer 123, that is, the through holes 14 are surrounded by the second semiconductor layer 123. In this embodiment, the layout of the through holes 14 adopts a multi-hole distributed layout. Compared with the traditional interdigitated layout, the multi-hole distributed layout can improve current distribution and reduce the occurrence of flash points. This is because the traditional interdigitated layout will cause the subsequent interdigitated electrodes to cause current congestion in the bend area of ​​the P / N semiconductor layer, which is prone to flash points when subjected to electrical shock or thermal shock. However, the distribution of the through holes 14 in this case is not limited to that shown in the figure, and the current and through hole size can also be designed accordingly according to the actual chip size and shape.

[0038] Looking down at the semiconductor stack 12 from above the LED, the through hole 14 has a first radius R1. In this embodiment, the through hole 14 is circular, and the first radius R1 is the radius of the through hole 14's outline. However, the shape of the through hole 14 is not limited to this. If the through hole 14 is a square-shaped hole or an irregular closed hole, the first radius R1 can be approximated by taking the radius of the inscribed circle thereof as the first radius R1. In some embodiments, to avoid current congestion, the first radius R1 ranges from 6 to 150 μm, preferably from 7 to 90 μm or from 15 to 40 μm, which is more conducive to improving the electrical characteristics of the LED. Considering the thermal and electrical characteristics of the LED, the area of ​​the through hole 14 accounts for 10 to 50% of the area of ​​the semiconductor stack 12. As shown in Table 1 below, the present invention optimizes the ratio of the area of ​​the through hole 14 to the area of ​​the semiconductor stack 12 (the area occupied by the through hole 14) through design comparison, which can further improve the operating voltage of the LED, increase the output light power and the electro-optical conversion efficiency, and enhance electrical overstress (a higher value indicates greater shock resistance). Preferably, the area of ​​the through hole 14 accounts for 26-34% of the area of ​​the semiconductor stack 12. When the area of ​​the through hole 14 is within this range, the photoelectric efficiency of the light emitting diode is better. Figure 2 The area of ​​the pattern formed by the bottom of the through hole 14 (where the first electrode 21 is set) is greater because the bottom of the through hole 14 is closer to the first semiconductor layer 121, which can better reflect the characteristics of the through hole 14. However, the present invention is not limited to this. In other embodiments, the area of ​​the through hole 14 can also refer to Figure 2 The pattern area formed at the top of the through hole 14 (on the upper surface of the second semiconductor layer 123).

[0039] Table 1

[0040]

[0041] like Figure 3 As shown ( Figure 3 The horizontal axis represents thermal resistance, and the vertical axis represents thermal capacitance). Compared with the traditional conventional structure, the design of the structure of the present invention can improve the package thermal resistance curve, so that the thermal resistance of the light-emitting diode is reduced by about 3 to 3.5K / W, thereby improving the stability of the light-emitting diode.

[0042] Compared with traditional light-emitting diodes, considering that the P-side expansion capability of ultraviolet light-emitting diodes is very different, it is necessary to introduce more N regions to shorten the conduction of P. By setting the ratio of the first radius R1 to the rated current in the range of 0.1 to 0.4, the carrier conduction capability can be enhanced, the local current density can be equalized, and the thermal effect caused by the current in the concentrated area can be avoided, the light-emitting layer 122 can be burned out of a molten hole or burned through, and the direct electrical damage can be avoided (the direct electrical damage can be understood as, when the lateral expansion performance of the semiconductor stack 12 is poor, the current is directly concentrated and injected downward, forming current congestion), directly breaking through the PN junction, and thus improving the anti-ESD performance of the light-emitting diode. Figure 4 As shown ( Figure 4 The horizontal axis is the ratio of the first radius R1 to the rated current, and the vertical axis is the electro-optical conversion efficiency). It is the influence of the ratio of the first radius R1 to the rated current on the electro-optical conversion efficiency. Considering that the ultraviolet diode adopts the heterojunction P-GaN:Mg / AlGaN, the growth difficulty brings about a high defect density, resulting in relatively low conductivity and poor injection efficiency. In order to better improve the electrical characteristics, the ratio of the first radius R1 to the rated current can be set in the range of 0.15 to 0.25 (such as forming a larger aperture to complete compensation under the current of the same specifications) to avoid outputting too high an operating voltage.

[0043] The rated current can refer to the rated operating current or rated terminal current of the LED. For example, the rated current can be converted from the lamp current in the end product's instruction manual. The number of UV device packages currently available on the market can be counted with the naked eye or identified through an optical microscope. By combining the number and arrangement of the lamp beads, the lamp current of a single component can be estimated. Preferably, to avoid current congestion, the rated current range can be 40-500mA.

[0044] The first electrode 21 is electrically connected to the first semiconductor layer 121. The first electrode 21 can have a single-layer, double-layer, or multi-layer structure, such as a stacked structure of Ti / Al, Ti / Al / Ti / Au, Ti / Al / Ni / Au, or V / Al / Pt / Au. In some embodiments, the first electrode 21 can be formed directly within the through-hole 14 of the epitaxial structure. The first semiconductor layer 121 has a high Al content. After being deposited within the through-hole 14, the first electrode 21 is subjected to high-temperature fusion to form an alloy, thereby forming a good ohmic contact with the first semiconductor layer 121.

[0045] The second electrode 22 is electrically connected to the second semiconductor layer 123. The second electrode 22 can be made of a transparent conductive material or a metal material (such as a Ni alloy metal structure or a Pa alloy metal structure). It can be adaptively selected according to the doping condition of the surface layer of the second semiconductor layer 123 (such as a p-type GaN surface layer). In some embodiments, the second electrode 22 is made of a transparent conductive material, and the material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium doped zinc oxide (GZO), tungsten doped indium oxide (IWO) or zinc oxide (ZnO), but the embodiments of the present disclosure are not limited thereto.

[0046] See also Figure 5 and Figure 6 , Figure 5 is a schematic top view of the light emitting diode provided by the second embodiment of the present invention, Figure 6 It is along Figure 5 Compared with Figure 1With respect to the light-emitting diode shown in the first embodiment, the main difference of the light-emitting diode provided in this embodiment is that, when looking down at the semiconductor stack 12 from above the light-emitting diode, a boss 16 is provided in each through hole 14. After the electrodes of the traditional light-emitting diode are set, a flat surface cannot be formed inside the device, and the unfilled space inside is large, forming a hollow structure inside, which affects the device packaging and thrust strength. In this case, a flattening effect is achieved by providing a boss 16. In addition, considering that the semiconductor stack 12 of the ultraviolet light-emitting diode is relatively thin, the depletion layer of the first semiconductor layer 121 and the second semiconductor layer 123 (the depletion layer of the P-type and N-type semiconductor layers) is relatively small, and the boss 16 can adjust the horizontal expansion vector to expand the current expansion propagation radius and avoid electrical damage directly below.

[0047] The inclination angle of the boss 16 can be in the range of 45 to 70°, preferably 55 to 60°, and the height of the boss 16 can be 500 to 800 nm. The upper surface of the boss 16 is in the same plane as the upper surface of the second semiconductor layer 123. The boss 16 has a second radius R2. When viewed from above, the outline of the boss 16 is also circular, and the second radius R2 is the radius of the circle. Taking into account the current congestion situation, the ratio of the second radius R2 to the first radius R1 can be in the range of 0.05 to 0.30. The size range of the second radius R2 can be 0.6 to 45 μm. If the boss 16 adopts a square-shaped hole or an irregular closed-shaped hole, the radius of the inscribed circle can be approximated as the second radius R2.

[0048] In this embodiment, looking down at the semiconductor stack 12 from above the light emitting diode, the boss 16 is located at the center of the through hole 14 to simplify the manufacturing process.

[0049] However, the present invention is not limited thereto. In other embodiments, Figure 7 As shown, the boss 16 can also be located at the edge of the through hole 14 near the semiconductor stack 12. That is, the boss 16 is offset toward the edge of the semiconductor stack 12. This allows the uniform electric injection field in the central region of the semiconductor stack 12 to flow toward its edge region, thereby increasing the carrier density per unit area in the edge region and improving the photoelectric properties of the light-emitting diode.

[0050] Furthermore, in some embodiments, Figure 8 As shown, a groove structure 17 can be used in place of the original boss 16 to similarly adjust the lateral expansion vector, thereby expanding the current propagation radius and preventing direct electrical damage. Both groove structure 17 and boss 16 are designed to form isolated islands in semiconductor stack 12, preventing device current from flowing through these areas. This, in turn, adjusts the lateral expansion vector to expand the current propagation radius and prevent direct electrical damage.

[0051] In some embodiments, as Figure 9 FIG. 1 is a schematic diagram of a partial structure of the boss 16 provided in another embodiment. Figure 6 While the platform 16 achieves flattening and diffraction optimization, its hollow structure is still noticeable. This embodiment, however, modifies the platform 16 surface (where the covering electrode 26 connects to the sidewall of the platform 16) by providing a covering electrode 26 to improve flatness and diffraction, thereby reducing the amount of first electrode 21 used and thus reducing the hollow area. The covering electrode 26 extends upward along the platform 16, with a height range of 100 to 400 nm. This increases the current spread directly below the platform 16, improving the photoelectric quality of the light-emitting diode.

[0052] The following discloses a method for making Figure 5 The LED method shown is shown in Figures 10 to 13 , Figures 10 to 13 yes Figure 5 The diagram shows the structure of a light-emitting diode at various stages in the manufacturing process.

[0053] First, if Figure 10 As shown in FIG. 1 , a substrate 10 is provided. Then, as shown in FIG. Figure 11 As shown, a semiconductor stack 12 is provided on a substrate 10, and the semiconductor stack 12 includes a first semiconductor layer 121, a light-emitting layer 122, and a second semiconductor layer 123 stacked in sequence on the substrate 10. Then, etching is performed downward starting from the second semiconductor layer 123 until the first semiconductor layer 121 is etched to form a plurality of through holes 14. The shaded filled area in the figure is the area of ​​the retained second semiconductor layer 123, and the retained second semiconductor layer 123 located in the through hole 14 is a boss 16, that is, the structure of the boss 16 can be the same as that of the semiconductor stack 12 to simplify the process. Subsequently, a chemical or physical etching method is used to selectively etch away the outer periphery of the semiconductor stack 12 to expose the substrate 10, so as to form an edge cutting path, which is convenient for subsequent cutting and other processes.

[0054] Furthermore, it should be noted that in other embodiments, the boss 16 may be added to the first semiconductor layer 121 by other methods to form the boss 16 structure. Furthermore, if the recess structure 17 is to be formed, the process steps may be to first form the through hole 14 and then further etch the recess structure 17 within the through hole 14.

[0055] Then, if Figure 12 As shown, a first electrode 21 is provided on the first semiconductor layer 121, and a portion of the first electrode 21 is located in the through hole 14. The shaded area in the figure is the area where the first electrode 21 is located.

[0056] Finally, if Figure 13 As shown, a second electrode 22 is provided on the second semiconductor layer 123. The area of ​​the second electrode 22 is smaller than the area of ​​the second semiconductor layer 123. The shaded area in the figure is the area where the second electrode 22 is located.

[0057] The above is only a public one for making Figure 5 The method for producing a light emitting diode shown in the figure is not limited to the present invention and is merely used to illustrate a method for producing a light emitting diode.

[0058] See also Figure 14 and Figure 15 , Figure 14 FIG. 1 is a schematic top view of the light emitting diode provided in the third embodiment of the present invention. Figure 15 It is along Figure 14 FF is a longitudinal cross-sectional view of the cutting line FF. As shown in the figure, compared with Figure 5 Compared to the light-emitting diode shown, the main difference of the light-emitting diode of this embodiment is that a cooling zone 24 is provided on the substrate 10. The cooling zone 24 refers to the upper surface area of ​​the substrate 10 not covered by the semiconductor stack 12. By designing a wide cooling zone 24 adjacent to the edge of the substrate 10 (taking into account the width of the cutting path, the width of the cooling zone can be 3% to 15% of the short side dimension of the chip), the path for side light emission is increased, heat accumulation is minimized, and a cold zone is formed on the periphery, which can accelerate heat diffusion and avoid thermal damage to the internal structure. Preferably, considering the heat dissipation layout, the ratio of the length D of the cooling zone 24 to the first radius R1 ranges from 1.2 to 1.5.

[0059] The cooling zone 24 can be formed in the following ways: 1. It can be formed by using electrode blocks separated by an edge design; 2. It can be formed by designing a heat sink structure in the aisle; 3. It can be formed by using a dam cooling glue. In this embodiment, the second scenario is adopted. The cooling zone 24 is provided with multiple heat dissipation structures. Each heat dissipation structure has a length ranging from 0.6 to 200 μm, a thickness ranging from 0.3 to 20 μm, and a width ranging from 0.6 to 200 μm. The lower limit of 0.6 μm for the length and width is based on photolithography accuracy considerations, and the upper limit of 200 μm is obtained based on the maximum size of the current chip of approximately 50 mil. Preferably, each heat dissipation structure has a length ranging from 10 to 50 μm, a thickness ranging from 3 to 9 μm, and a width ranging from 2.5 to 7.5 μm, to provide better heat dissipation performance while ensuring the photoelectric quality of the light-emitting diode. The spacing between the multiple heat dissipation structures ranges from 0.6 to 200 μm, with a preferred spacing range of 2.5 to 7.5 μm. Considering the absorption problem of the P-side of the UV LED, a differentiated design is required for the center and edge regions. A walkway is provided in the edge region to form a cooling zone 24 on the periphery (the cooling zone 24 can refer to an annular area radiating inward from the edge of the substrate 10 by 7.6 to 223.5 μm). The ratio of the walkway length to the first radius R1 ranges from 1.2 to 1.5 for optimal photoelectric effect, and is preferably 1.3.

[0060] In some embodiments, as Figure 7 As shown, the light-emitting diode may further include a first insulating layer 31, a second insulating layer 32, a first protective electrode 41, a second protective electrode 42, a first pad 51, and a second pad 52. The first insulating layer 31 covers the first electrode 21 and the second electrode 22. The first insulating layer 31 has a first opening 61 and a second opening 62. The first opening 61 exposes the first electrode 21, and the second opening 62 exposes the second electrode 22. The first protective electrode 41 is connected to the first electrode 21 through the first opening 61, and the second protective electrode 42 is connected to the second electrode 22 through the second opening 62. The second insulating layer 32 covers the first protective electrode 41 and the second protective electrode 42. The second insulating layer 32 has a third opening 63 and a fourth opening 64.

[0061] In addition to playing the role of current expansion, the first protective electrode 41 can also protect the first electrode 21 below, and play the role of support, padding, etc. Preferably, the first protective electrode 41 completely covers the first electrode 21 to prevent metal precipitation in the first electrode 21, such as preventing Al metal precipitation. The material of the first electrode 21 can be selected from one or more of Cr, Pt, Au, Ni, Ti, and Al. Preferably, the surface metal of the first electrode 21 is a Ti metal layer or a Cr metal layer, so that a stable adhesion relationship is formed between the first protective electrode 41 and the adjacent structural layer. The material of the second protective electrode 42 can be selected from one or more of Cr, Pt, Au, Ni, Ti, and Al. Preferably, the surface metal of the second protective electrode 42 is a Ti metal layer or a Cr metal layer, so that a stable adhesion relationship is formed between the second protective electrode 42 and the adjacent structural layer.

[0062] The first insulating layer 31 and the second insulating layer 32 are made of a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. The inorganic material may include silica gel. The dielectric material may include an electrically insulating material such as aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating layer may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof. The combination may be, for example, a Bragg reflector (DBR) formed by repeatedly stacking two materials with different refractive indices.

[0063] The first pad 51 is connected to the first protection electrode 41 through the third opening 63, and the second pad 52 is connected to the second protection electrode 42 through the fourth opening 64. The first pad 51 and the second pad 52 can be metal pads and can be formed in the same process using the same material, thus having the same layer structure.

[0064] Please combine Figure 5 See Figure 16 , Figure 16 yes Figure 5 Schematic diagram of the light emitting diode in the coordinate system. It should be noted that, in order to facilitate Figure 16 A clear display of Figure 16 No longer marked with Figure 5 The same structure of the label, that is, Figure 16 The component numbers in Figure 5 The label in Figure 16 Only the situation in the coordinate system is shown.

[0065] Looking down at the semiconductor stack 12 from above the light-emitting diode, a coordinate system is established with the center of the semiconductor stack 12 as the origin, the line perpendicular to the first side 71 of the semiconductor stack 12 as the x-axis of the coordinate system, and the line perpendicular to the second side 72 of the semiconductor stack 12 as the y-axis of the coordinate system. The xy coordinate system is thus established. The first side 71 of the semiconductor stack 12 is connected to the second side 72. Preferably, the first side 71 of the semiconductor stack 12 is substantially perpendicular to the second side 72. A first distance X1 is offset toward the positive and negative sides of the x-axis and a second distance X2 are offset toward the positive and negative sides of the y-axis to form a first pattern 81. A third distance X3 is offset toward the positive and negative sides of the x-axis and a fourth distance X4 are offset toward the positive and negative sides of the y-axis to form a second pattern 82. The third distance X3 and the fourth distance X4 are both greater than the first distance X1 and the second distance X2, that is, the third distance X3 and the fourth distance X4 are greater than the first distance X1, and the third distance X3 and the fourth distance X4 are also greater than the second distance X2. The third distance X3 may be 1.5 to 3.75 times the first distance X1, and the fourth distance X4 may be 1.5 to 3.75 times the second distance X2. The first distance X1 may range from 50 to 160 μm, the second distance X2 may range from 50 to 160 μm, the third distance X3 may range from 150 to 480 μm, and the fourth distance X4 may range from 150 to 480 μm. The first distance X1 may be the same as or different from the second distance X2, and the third distance X3 may be the same as or different from the fourth distance X4.

[0066] Adjacent through-holes 14 within the first pattern 81 have a first spacing L1, while adjacent through-holes 14 between the first pattern 81 and the second pattern 82 have a second spacing L2, with the first spacing L1 being greater than the second spacing L2. By adjusting the opening density from the inside out, carrier congestion is reduced, optimizing the distance distribution of through-holes 14 within different rectangles. This suppresses crowded injection in the center, avoids the thermal effects of concentrated current, and prevents the formation of melt holes or burn-throughs in the light-emitting layer 122. This prevents direct electrical damage and direct breakdown of the PN junction, thereby improving the ESD resistance of the light-emitting diode.

[0067] Preferably, the first figure 81 and the second figure 82 are rectangular in shape, but the present invention is not limited thereto. The first figure 81 and the second figure 82 may also be symmetrical figures, such as circles, polygons, etc., as long as the first spacing L1 of adjacent through holes 14 located in the first figure 81 is greater than the second spacing L2 of adjacent through holes 14 located between the first figure 81 and the second figure 82.

[0068] It should be noted that the ESD resistance of the light-emitting diode can be improved by simply ensuring that the first spacing L1 between the through-holes 14 within the first pattern 81 is greater than the second spacing L2 between the through-holes 14 between the first pattern 81 and the second pattern 82. That is, in this embodiment, the ratio of the first radius R1 to the rated current is not limited to a range of 0.1 to 0.4.

[0069] Furthermore, a fifth distance X5 can be offset toward the positive and negative sides of the x-axis, and a sixth distance X6 can be offset toward the positive and negative sides of the y-axis to enclose a third pattern 83. Both the fifth distance X5 and the sixth distance X6 are greater than the first distance X1 and the second distance X2, and less than the third distance X3 and the fourth distance X4. Adjacent through-holes 14 located between the first pattern 81 and the third pattern 83 have a third spacing L3. The first spacing L1 is greater than the third spacing L3, and the third spacing L3 is greater than or equal to the second spacing L2. This can further improve the thermal characteristics of the light-emitting diode. The fifth distance X5 can range from 100 to 320 μm, and the sixth distance X6 can range from 100 to 320 μm.

[0070] In some embodiments, to further improve the thermal characteristics of the LED, the through holes 14 within the first pattern 81 have a first radius R1, and the ratio of the first spacing L1 to the first radius R1 ranges from 0.8 to 1.5. The through holes 14 within the second pattern 82 have a third radius R3, and the ratio of the second spacing L2 to the third radius R3 ranges from 0.6 to 1.2.

[0071] Please combine Figure 5 See Figure 17 , Figure 17 yes Figure 5 Schematic diagram of a light emitting diode with a first circle 91 and a second circle 92. It should be noted that, for the sake of convenience Figure 17 A clear display of Figure 17 No longer marked with Figure 5 The same structure of the label, that is, Figure 17 The component numbers in Figure 5 The label in Figure 17Only the case with first circle 91 and second circle 92 is illustrated. Looking down at semiconductor stack 12 from above the LED, the LED has a pin region 90. Pin region 90 is located at the center of semiconductor stack 12, and through-hole 14 avoids pin region 90. First circle 91 is constructed with the center of one of the through-holes 14 as the center, using the distance between the centers of two adjacent through-holes 14 near pin region 90 as radius R4. Second circle 92 is constructed with the center of one of the through-holes 14 as the center, using the distance between the centers of two adjacent through-holes 14 near the edge of semiconductor stack 12 as radius R5. The first circle 91 is larger than the second circle 92, that is, the radius R4 of the first circle 91 is larger than the radius R5 of the second circle 92. By adjusting the opening density from the inside to the outside, carrier congestion is reduced, and the distribution of the through holes 14 in different circles is optimized to suppress the crowded injection in the central area. This can avoid the thermal effect caused by the current in the concentrated area, which may cause a molten hole to be burned in the light-emitting layer 122 or burn through the light-emitting layer 122, and can avoid direct electrical damage, which may cause direct breakdown of the PN junction, thereby improving the ESD resistance of the light-emitting diode.

[0072] Vias 14 near ejector pin region 90 may be spaced 15 to 60 μm from ejector pin region 90, preferably 35 to 40 μm. Vias 14 near the edge of semiconductor stack 12 may be spaced 20 to 70 μm from the edge of semiconductor stack 12, preferably 45 to 47 μm. To further improve the ESD resistance of the light-emitting diode, the area of ​​first circle 91 is preferably at least twice the area of ​​second circle 92.

[0073] It should be noted that the ESD resistance of the light emitting diode can be improved by simply satisfying the condition that the first circle 91 is larger than the second circle 92. That is, in this embodiment, the ratio of the first radius R1 to the rated current is not limited to the range of 0.1 to 0.4.

[0074] In some embodiments, the through holes 14 located within the first circle 91 are non-uniformly distributed, while the through holes located within the second circle 92 are uniformly distributed, thereby achieving a carrier density per unit area within the first circle 91 that is less than the carrier density per unit area within the second circle 92. By making the carrier density per unit area near the edge of the semiconductor stack 12 greater than the carrier density per unit area near the center of the semiconductor stack 12, the injection density at the boundary is enhanced (the waveguide effect of photons is considered here, and the light emission near the boundary is more significant), thereby improving the light emission characteristics of the light-emitting diode. In addition, the subsequently arranged solder pad will be formed in the area of ​​the second circle 92. Considering the heat dissipation effect of the solder pad, if the carrier density per unit area within the second circle 92 is greater, it is more conducive to heat dissipation.

[0075] The carrier density per unit area can be understood as the current density vertically injected into the light-emitting layer 122 per unit area. Because the position and distribution of the through-holes 14 affect the spread of current, the current density of the LED is not actually uniformly distributed. The current density P near a given through-hole 14 can be calculated approximately as the injected current I / the area of ​​the first semiconductor layer 121 within the auxiliary circles (e.g., first circle 91 and second circle 92) radiated by the through-hole 14. In this embodiment, the areas of the first semiconductor layer 121 within the two auxiliary circles 91 and 92 are substantially similar, approximately assuming the injected current is consistent, and R4 > R5 (i.e., the area of ​​the first circle 91 is larger than the area of ​​the second circle 92), resulting in a lower carrier density per unit area within the first circle 91 than within the second circle 92.

[0076] However, the arrangement of the through holes 14 in this case is not limited to Figure 17 In some embodiments, as shown in Figure 18 As shown, the through holes 14 located in the center may be arranged in a tetragonal orthogonal manner, and the through holes 14 located at the edge may be arranged in a hexagonal close-packed manner.

[0077] like Figure 19 As shown ( Figure 19 ), where the horizontal axis is voltage and the vertical axis is current, is a voltage-current characteristic curve. As can be seen from the figure, the light-emitting diode of the present invention requires a lower operating voltage, approximately 0.3V lower, under the same current conditions, compared to conventional diodes, thereby effectively improving the photoelectric quality of the light-emitting diode.

[0078] One embodiment of the present invention further provides a light-emitting device, which utilizes the light-emitting diode described in any of the above embodiments. The size of the light-emitting diode can be Micro LED, Mini LED, or conventional LED. The light-emitting diode can be used in backlight displays or RGB displays. Hundreds, thousands, or even tens of thousands of small-sized flip-chip light-emitting diodes can be integrated and mounted on an application substrate or a packaging substrate to form the light source portion of the backlight display device or RGB display device.

[0079] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention may be improved in only one or several aspects, without having to simultaneously solve all the technical problems listed in the prior art or background art. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as limiting the claim.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: A semiconductor stack, comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence, wherein the semiconductor stack has a plurality of through holes, each of the through holes extending downward from the second semiconductor layer to the first semiconductor layer, and the through holes exposing a portion of the surface of the first semiconductor layer; wherein, looking down toward the semiconductor stack from above the light-emitting diode, a coordinate system is established with the center of the semiconductor stack as the origin, a straight line from a perpendicular line segment from the origin to a first side of the semiconductor stack is the x-axis of the coordinate system, and a straight line from a perpendicular line segment from the origin to a second side of the semiconductor stack is the y-axis of the coordinate system, the first side is perpendicular to and connected to the second side; a first distance is offset toward the positive and negative sides of the x-axis and a second distance is offset toward the positive and negative sides of the y-axis to enclose a first figure, a third distance is offset toward the positive and negative sides of the x-axis and a fourth distance is offset toward the positive and negative sides of the y-axis to enclose a second figure, the third distance and the fourth distance are both greater than the first distance and the second distance, adjacent through holes within the first figure have a first spacing, adjacent through holes between the first figure and the second figure have a second spacing, and the first spacing is greater than the second spacing; In which, a fifth distance is offset toward the positive and negative sides of the x-axis and a sixth distance is offset toward the positive and negative sides of the y-axis to form a third figure, the fifth distance and the sixth distance are both greater than the first distance and the second distance, and both are smaller than the third distance and the fourth distance, and adjacent through holes located between the first figure and the third figure have a third spacing, the first spacing is greater than the third spacing, and the third spacing is greater than or equal to the second spacing.

2. The light emitting diode according to claim 1, wherein: The first distance ranges from 50 to 160 μm, the second distance ranges from 50 to 160 μm, the third distance ranges from 150 to 480 μm, and the fourth distance ranges from 150 to 480 μm.

3. The light emitting diode according to claim 1, wherein: The third distance is 1.5 to 3.75 times the first distance, and the fourth distance is 1.5 to 3.75 times the second distance.

4. The light emitting diode according to claim 1, wherein: The fifth distance ranges from 100 to 320 μm, and the sixth distance ranges from 100 to 320 μm.

5. The light emitting diode according to claim 1, wherein: The through hole in the first pattern has a first radius, and a ratio of the first spacing to the first radius ranges from 0.8 to 1.

5.

6. The light emitting diode according to claim 5, characterized in that: The first radius has a size range of 6 to 150 μm.

7. The light emitting diode according to claim 5, characterized in that: Looking down at the semiconductor stack from above the light-emitting diode, a boss is provided in the through hole, the boss has a second radius, and a ratio of the second radius to the first radius is in a range of 0.05 to 0.

30.

8. The light emitting diode according to claim 7, wherein: Looking down at the semiconductor stack from above the light emitting diode, the boss is located at an edge of the through hole adjacent to the semiconductor stack.

9. The light emitting diode according to claim 1, wherein: The through hole between the first figure and the second figure has a third radius, and a ratio of the second spacing to the third radius is in a range of 0.6 to 1.

2.

10. The light emitting diode according to claim 1, wherein: Looking down at the semiconductor stack from above the light-emitting diode, the area of ​​the through hole occupies 10% to 50% of the area of ​​the semiconductor stack.

11. The light emitting diode according to claim 5, characterized in that: The light-emitting diode further includes a substrate, a first electrode and a second electrode. The semiconductor stack is arranged on the substrate. The first semiconductor layer is located between the substrate and the light-emitting layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer.

12. The light emitting diode according to claim 11, characterized in that: Looking down at the semiconductor stack from above the light-emitting diode, the plurality of through holes are arranged in an array, and the substrate has a cooling zone, which refers to an upper surface area of ​​the substrate not covered by the semiconductor stack.

13. The light emitting diode according to claim 12, characterized in that: The ratio of the length of the cooling zone to the first radius is in a range of 1.2 to 1.

5.

14. The light emitting diode according to claim 12, wherein: The cooling zone is provided with a plurality of heat dissipation structures, each of which has a length ranging from 0.6 to 200 μm, a thickness ranging from 0.3 to 20 μm, and a width ranging from 0.6 to 200 μm, and a spacing range between the plurality of heat dissipation structures ranging from 0.6 to 200 μm.

15. The light emitting diode according to claim 11, wherein: The light-emitting diode also includes a first insulating layer, a second insulating layer, a first protective electrode, a second protective electrode, a first soldering pad and a second soldering pad, the first insulating layer covers the first electrode and the second electrode, the first insulating layer has a first opening and a second opening, the first protective electrode is connected to the first electrode through the first opening, and the second protective electrode is connected to the second electrode through the second opening, the second insulating layer covers the first protective electrode and the second protective electrode, the second insulating layer has a third opening and a fourth opening, the first soldering pad is connected to the first protective electrode through the third opening, and the second soldering pad is connected to the second protective electrode through the fourth opening.

16. A light emitting device, characterized in that: The light emitting device adopts the light emitting diode according to any one of claims 1 to 15.

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