A four-switch resonant gate drive circuit suitable for multi-channel driving

Abstract

This invention discloses a four-switch resonant gate drive circuit suitable for multi-channel driving. The first and second MOSFETs form a half-bridge, with the midpoint of the half-bridge connected to the same-name terminal of the primary winding of a transformer, and connected to the gate of the fourth switch of the main topology gate driver via the midpoint of the bridge arm. The third and fourth MOSFETs also form a half-bridge, with the midpoint of the half-bridge connected to the non-same-name terminal of the primary winding of the transformer via a port, and connected to the gate of the second switch of the main topology gate driver. The gate parasitic capacitance of the fourth switch of the main topology gate driver is considered to be connected in parallel across the second MOSFET, and the gate parasitic capacitance of the second switch of the main topology gate driver is considered to be connected in parallel across the fourth MOSFET. This invention solves the technical problems of existing resonant gate drive schemes, such as high drive loss, complex control and uncontrollable dead time, numerous magnetic and switching elements, low drive current, and inability to achieve multi-channel driving.

Description

TECHNICAL FIELD

[0001] The present application relates to a switching power supply, in particular to a four-switch resonant gate drive circuit suitable for multi-channel driving, belonging to the technical field of power generation, power transformation or power distribution. BACKGROUND

[0002] With the continuous development of portable devices, miniaturization and high efficiency have become the goal of continuous pursuit and development in the field of switching power supply. Increasing the switching frequency can reduce the size and weight of the switching power supply, but at the same time, the switching tube loss increases sharply, especially the gate drive loss will increase linearly with the increase of switching frequency.

[0003] The traditional drive loss is often proportional to the switching frequency, and the high drive loss caused by high switching frequency becomes one of the obstacles for further improving the frequency and power density of the power converter. When configuring the peripheral circuit, usually a half-bridge drive chip can drive a pair of half-bridge, and the drive loss is proportional to the switching frequency, which limits the further improvement of the switching frequency of the converter. In addition, for the input series type converter structure, the number of MOS tubes is large, and the drive signal is floating. If the traditional half-bridge drive chip is used, the number of drive chips required is large, the drive loss is large, the auxiliary power supply structure for supplying power to the drive chip is complex, the space occupied by the drive system is large, and the power density of the system will be reduced.

[0004] In the early 1990s, in order to reduce the system drive loss, people put forward the high-frequency resonant gate drive technology. The resonant gate driver recovers the energy on the gate capacitor through LC resonance, has lower gate drive loss, and has obvious advantages in high-frequency application scenarios. At present, there are many types of resonant gate drivers, such as the resonant gate drive circuit proposed by W. Eberle et al. in 2008 (W. Eberle, Y.-F. Liu and P. C. Sen, "A New Resonant Gate-Drive Circuit With Efficient Energy Recovery and Low Conduction Loss," in IEEE Transactions on Industrial Electronics, vol. 55, no. 5, pp. 2213-2221, May 2008, doi: 10.1109 / TIE.2008.918636.). It is composed of four control switches and a small resonant inductor. The proposed circuit also realizes fast turn-on and turn-off transition time to reduce switching and conduction losses in power MOSFETs. All MOS tubes of the drive circuit realize soft switching during the entire charging and discharging process, the circulating current is low, and 51% of the gate energy can be recovered at a 5V gate drive voltage. However, its control timing is complex, timing matching is difficult, and it does not have an isolation function, so it cannot realize multi-channel drive.

[0005] In 2019, Wu, Q. Wang, et al. proposed a new zero-current switching dual-channel push-pull isolated resonant gate driver (Q. Wu, Q. Wang, J. Zhu and X. Lan, "Dual-Channel Push-Pull Isolated Resonant Gate Driver for High-Frequency ZVS Full-Bridge Converters," in IEEE Transactions on Power Electronics, vol. 34, no. 5, pp. 4019-4024, May 2019, doi: 10.1109 / TPEL.2018.2873192.). The drive drives a pair of power MOSFETs in one bridge arm working at high switching frequency. The drive includes the ability to provide two isolated complementary drive signals, low gate drive loss and high reliability in the off state, and realizes low components, thereby reducing drive cost and improving reliability. However, this scheme requires additional transformer leakage inductance design and large excitation inductance design, which is difficult to design at high frequency. The control timing of the gate drive circuit needs to be determined to determine the dead zone, and the control is slightly complex.

[0006] In 2022, Wu's team proposed a new half-bridge type isolated resonant gate driver (G. Li and X. Wu, "A 98.4% Efficiency 380V-12V DCX With 1.3kW / in3 Power Density Using Low N FoM Devices and Resonant Drive Transformer," in IEEE Transactionson Power Electronics, vol. 37, no. 10, pp. 12346-12356, Oct. 2022, doi: 10.1109 / TPEL.2022.3178162.) to address the high driving loss of this multi-stage series DCX at high frequency (1MHz) and the need for multi-stage floating drive. By controlling the dead time of the driving signal through the design of the resonant parameters, a multi-channel gate drive based on a transformer is realized. The resonant gate driver structure is similar to the LLC topology, which charges and discharges the gate capacitance of the MOSFET through resonance, realizes the recovery of the gate drive energy, and improves the efficiency. Compared with the traditional half-bridge driver, the use of resonant gate driver significantly reduces the occupied space and improves the overall system power density. However, it does not have the level shift function, the circulating current causes large loss, and the turn-off loss and driving loss of the switch tube are not modeled and analyzed. SUMMARY

[0007] TECHNICAL PROBLEM: The present application aims to solve the technical problems of high driving loss, complex control, uncontrollable dead time, too many magnetic and switching elements, small driving current, and inability to achieve multi-channel driving in existing resonant gate drive schemes.

[0008] TECHNICAL SOLUTION: The four-switch resonant gate drive circuit for multi-channel driving according to the present application is composed of four metal oxide semiconductor field effect transistors (MOSFETs) and an isolated transformer. The first MOSFET and the second MOSFET form a half-bridge, with the half-bridge midpoint connected to the same end of the primary side of the transformer and connected to the fourth switch tube gate of the main topology gate driver through the bridge arm midpoint. The third MOSFET and the fourth MOSFET also form a half-bridge, with the half-bridge midpoint connected to the non-same end of the primary side of the transformer through the port and connected to the second switch tube gate of the main topology gate driver. The gate parasitic capacitance of the fourth switch tube of the main topology gate driver is considered to be connected in parallel across the second MOSFET, and the gate parasitic capacitance of the second switch tube of the main topology gate driver is considered to be connected in parallel across the fourth MOSFET.

[0009] The transformer, the first secondary side and the second secondary side are provided with coils to realize floating ground driving, realize multiple isolation driving design, when two complementary isolation drives, the secondary side is designed with two coils, the same name end of the upper end coil is connected to the gate parasitic capacitor of the first switch tube of the main topology, the non-same name end is connected to the other end of the gate parasitic capacitor for floating ground; the non-same name end of the lower end coil of the secondary side is connected to the gate parasitic capacitor of the third switch tube of the main topology, and the same name end is connected to the other end of the gate parasitic capacitor for floating ground. The gate input signals of the four MOSFETs are sent by a digital signal processing chip, and then pass through the main topology gate driver to generate; wherein the first MOSFET and the second MOSFET are complementary conduction, and the third MOSFET and the fourth MOSFET are complementary conduction.

[0010] The phase difference between the second MOSFET waveform and the fourth MOSFET waveform is 180°, and the phase difference between the first MOSFET waveform and the third MOSFET waveform is 180°.

[0011] The gate input signals are different, and the circuit works in different modes, and a total of eight working modes t0-t8 can be divided, in the eight working modes, the circuit resonates through the gate parasitic capacitor and the transformer inductance, and realizes the energy recovery of the main topology gate drive.

[0012] The gate signals of the four MOSFETs are controlled by changing the phase of the gate signals of the four MOSFETs, the difference between the second MOSFET turn-on time and the fourth MOSFET turn-off time is the first dead time, and the difference between the fourth MOSFET turn-on time and the second MOSFET turn-off time is the second dead time.

[0013] Advantages: the above technical scheme has the following advantages:

[0014] (1) The present application can realize the gate drive energy recovery.

[0015] (2) The present application is simple to control, and the dead zone is controllable.

[0016] (3) The present application uses less magnetic elements and switching elements.

[0017] (4) The driving current of the present application is large, and the fast turn-off capability can be realized.

[0018] (5) The present application can realize multiple driving ability by using transformer. DETAILED DESCRIPTION

[0019] Figure 1a It is the main topology structure of the present application, Figure 1b It is the resonant gate drive circuit of the present application.

[0020] Figure 2 is the structure diagram of the resonant gate drive circuit and input module of the application.

[0021] Figure 3 is the main signal waveform diagram of each mode of the application.

[0022] In the figure: first MOSFET Q1, second MOSFET Q2, third MOSFET Q3, fourth MOSFET Q4, primary side P1, first secondary side P2, second secondary side P3, first switch tube S1, second switch tube S2, third switch tube S3, fourth switch tube S4. DETAILED DESCRIPTION

[0023] The technical solutions of the application will be described in detail below with reference to the drawings.

[0024] The application is used for a four-switch resonant gate drive circuit suitable for multi-way drive as follows to achieve the above-mentioned application purposes.

[0025] In the specific implementation of the application scheme, it can be applied to drive four main switch tubes of LLC-DCX (resonant inductance, excitation inductance and resonant capacitor series topology under resonant frequency) converter. Figure 1a For the main topology part of LLC-DCX, the first switch tube S1, the second switch tube S2, the third switch tube S3 and the fourth switch tube S4 are four main switch tubes, the gates of which are connected to Vgs1, Vgs2, Vgs3 and Vgs4 ports respectively, two half bridges VHB1 and VHB2 are connected to two transformers of LLC (resonant inductance, excitation inductance and resonant capacitor series topology) through the secondary side synchronous rectifier tube and output to RL. Figure 1bFor the resonant gate drive circuit of the application, the first MOSFET Q1, the second MOSFET Q2, the third MOSFET Q3 and the fourth MOSFET Q4 are four MOSFETs, the gates of which are connected to ports Vg1, Vg2, Vg3 and Vg4 respectively. The first MOSFET Q1 and the second MOSFET Q2 form a pair of half-bridges, and the third MOSFET Q3 and the fourth MOSFET Q4 form a pair of half-bridges. The source of the first MOSFET Q1 is connected to port Vgs4 and to the same end of the primary coil of transformer P1. The drain of the fourth MOSFET Q4 is connected to port Vgs2 and to the non-same end of the primary coil of transformer P1. Cgs1, Cgs2, Cgs3 and Cgs4 are the gate parasitic capacitances of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 respectively, and Vgs1-VHB1, Vgs2, Vgs3-VHB2 and Vgs4 are the voltage values across these capacitors respectively, wherein Cgs4 is connected in parallel across the second MOSFET Q2, Cgs2 is connected in parallel across the fourth MOSFET Q4, Cgs1 is connected in parallel across the first secondary coil P2, and Cgs3 is connected in parallel across the second secondary coil P3. The current value on the primary coil is set as I L , the direction is from the same end to the non-same end, the current value on the first secondary coil P2 is set as I1, the direction is from the same end to the non-same end, and the current value on the secondary coil P3 is set as I2, the direction is from the same end to the non-same end. In subsequent simulation, the turns ratio of the transformer coil can be set as P1:P2:P3=1:1:1. The ports Vgs2 and Vgs4 of the main topology are interconnected with the ports Vgs2 and Vgs4 of the resonant gate drive. The port Vgs1 of the main topology is connected to the forward end of Cgs1, and the port VHB1 of the main topology is connected to the reverse end of Cgs1. The port Vgs3 of the main topology is connected to the forward end of Cgs3, and the port VHB2 of the main topology is connected to the reverse end of Cgs3.

[0026] Figure 2 The structure diagram of the resonant gate drive circuit and the input module of the application can first generate four PWM signals by using a DSP chip. In specific implementation, the period of all the PWM signals can be selected as high frequency (such as 2MHz), and appropriate amplitude, bias, duty cycle and phase can be selected to ensure that the first MOSFET and the second MOSFET are complementary to be turned on, and the third MOSFET and the fourth MOSFET are complementary to be turned on. Then the four PWM signals are connected to the gate drive module, and the output ports are connected to ports Vg1, Vg2, Vg3 and Vg4 respectively to drive the four MOSFETs of the resonant gate drive of the application.

[0027] In the specific implementation of this invention, an appropriate resonant gate drive circuit input power supply voltage VDD can be selected, and the gate parasitic capacitance of each main topology and the inductance of the primary and secondary coils of the transformer can be reasonably selected. The four MOSFETs are selected in a model that includes the body diode and the source-drain capacitance. A comprehensive simulation of the circuit after selecting appropriate parameters yields the following results: Figure 3 The diagram shows the main signal waveforms for each mode of the present invention. The horizontal axis represents time t, and the vertical axis represents the gate-source voltage values ​​of the first MOSFET (Vg1-VH1), the second MOSFET (Vg2), the third MOSFET (Vg3-VH2), and the fourth MOSFET (Vg4). L I1 is the current flowing into the primary side P1, I2 is the current flowing out of the first secondary side P2, and I3 is the current flowing into the second secondary side P3. Vgs2 and Vgs4 are the gate-source voltages of the second and fourth switches in the main topology, respectively. Vgs1-VHB1 and Vgs3-VHB2 are the gate-source voltages of the first and third switches S1 and S3 in the main topology, respectively.

[0028] As can be seen from the waveform diagram, the circuit can be divided into 8 different operating modes due to different input signals. The working principle of each mode is as follows:

[0029] During the t0 to t1 state, the first MOSFET Q1 and the fourth MOSFET Q4 are turned on. The voltage across the primary side P1 is clamped to VDD, with the corresponding terminal being positive. The power supply energizes the primary side P1, causing the current I in the primary side P1 to... L The reverse current rises linearly to the forward current. The voltages on the first secondary side P2 and the second secondary side P3 are also clamped to VDD and held, and the current flowing through the coil is 0. At this time, port Vgs2 is grounded, the second main switch remains off, port Vgs4 is connected to VDD, the fourth main switch remains on, the voltage between Vgs1 and VHB1 is VDD, the first main switch remains on, the voltage between Vgs3 and VHB2 is -VDD, and the third main switch remains off.

[0030] During states t1 to t2, only the fourth MOSFET, Q4, is turned on out of the four MOSFETs. The voltage across the primary side P1 is equal to Vgs4, with the corresponding terminal being positive. At this time, the primary side P1 resonates with Cgs4, and the resonant current I... LEnergy flows from the same terminal into the primary side P1. The energy stored in Cgs4 is recovered to the primary side P1 through resonance and transferred to the secondary side. Due to the change in clamping voltage on the first secondary side P2 and the second secondary side P3, the loop current I1 generates a negative current, discharging Cgs1 until the voltages across it are equal. The first main switch turns off, and I2 generates a positive current, charging Cgs3 until the voltages across it are equal. The third main switch remains off. Port Vgs2 remains grounded, and the second main switch remains off. The voltage at port Vgs4 drops, and the fourth main switch turns off.

[0031] During states t2 to t3, the second MOSFET Q2 and the fourth MOSFET Q4 are turned on out of the four MOSFETs. The voltage across the primary side P1 is clamped to ground. After resonance, the energy stored in the primary side P1 increases, I... L The current value increases compared to before resonance, and then I L The voltages remain unchanged. The voltages on the first secondary side P2 and the second secondary side P3 are also clamped to 0 and held. The voltages on Cgs1 and Cgs3 are already 0, therefore there is no current in the secondary circuits. The voltages at ports Vgs1, Vgs2, Vgs3, and Vgs4 are all 0, therefore all four main switches remain off. This is the first dead-time state.

[0032] During states t3 to t4, only the second MOSFET Q2 among the four MOSFETs is turned on. The voltage across the primary side P1 is equal to Vgs2, and the non-polarized terminals are positive. At this time, P1 and Cgs2 resonate, and the resonant current I... L The energy flows from the same-named end into the primary edge P1, and the energy stored on the primary edge P1 is transmitted through I... L Cgs2 is charged until the second main switch begins to conduct. Due to the change in clamping voltage on the first secondary side P2 and the second secondary side P3, the loop current I1 generates a negative current, which reverses the charge on Cgs1. The gate-source voltage of the first main switch continues to decrease to a negative value and remains off. I2 generates a positive current, which charges Cgs3, and the gate-source voltage gradually rises until the third main switch begins to conduct. Port Vgs4 is grounded, and the fourth main switch remains off.

[0033] During states t4 to t5, the second MOSFET Q2 and the third MOSFET Q3 are turned on. The voltage across the primary winding P1 is clamped to VDD, with the non-polarized terminals being positive. Therefore, I L First, reverse charge the power supply until I... L The current reverses, before the next state arrives |I LThe voltage increases continuously. The voltages of secondary coils P2 and P3 are also clamped, so there is no current in either circuit. Port Vgs2 is connected to VDD, so the second main switch remains on; port Vgs4 is grounded, so the fourth main switch remains off. The secondary circuit state is the same as the previous state, so the third main switch remains on, and the first main switch remains off.

[0034] During states t5 to t6, only Q2 among the four MOSFETs is turned on. The voltage across the primary winding P1 is equal to Vgs2, with the non-polarized terminals being positive. At this time, Cgs2 resonates with P1, and the resonant current I... L The voltage flowing into P1 from the non-corresponding terminal discharges through the resonant circuit on Cgs2, causing Vgs2 to gradually decrease, and the second main switch begins to turn off. Due to the change in clamping voltage between the secondary coils P2 and P3, the loop current I1 generates a positive current, positively charging Cgs1, and the gate-source voltage of the first main switch gradually rises to 0, remaining off. I2 generates a negative current, discharging Cgs3, and the gate-source voltage drops to 0, causing the third main switch to turn off. With port Vgs4 grounded, the fourth main switch remains off.

[0035] During states t6 to t7, Q2 and Q4 of the four MOSFETs are turned on. The voltage across the primary winding P1 is clamped to ground. After P1 resonates, the stored energy increases, and I... L The current value increases compared to before resonance, and then I L The voltages remain unchanged. The voltages of secondary-side P2 and P3 are also clamped to 0 and held. The voltages of Cgs1 and Cgs3 are already 0, therefore there is no current in the secondary-side circuits. The voltages of ports Vgs1, Vgs2, Vgs3, and Vgs4 are all 0, therefore all four main switches remain off. This state is the second dead zone state.

[0036] During states t7 to t8, only Q4 of the four MOSFETs is turned on. The voltage across the primary winding P1 is equal to Vgs4, with the corresponding terminal being positive. At this time, Cgs4 resonates with P1, and the resonant current I... L The voltage flowing into P1 from the non-corresponding terminal charges Cgs4 through the resonant circuit, causing Vgs4 to gradually increase, and the fourth main switch begins to conduct. Due to the change in clamping voltage between the secondary coils P2 and P3, the loop current I1 generates a positive current, positively charging Cgs1, and the gate-source voltage of the first main switch gradually rises, causing it to conduct; I2 generates a negative current, reversely charging Cgs3, and the gate-source voltage of the third main switch drops to a negative value, remaining off. With port Vgs2 grounded, the second main switch remains off.

[0037] In summary, this invention achieves gate drive energy recovery through a resonant circuit, resulting in a relatively simple circuit that is easy to control, uses fewer magnetic components, and can achieve multi-channel drive capability using a transformer. This invention has a wide range of applications and can be used in various multi-channel drive topologies.

Claims

1. A four-switch resonant gate drive circuit suitable for multi-channel drive, characterized by, The driving circuit is composed of four metal oxide semiconductor field effect transistors (MOSFET) and an isolation transformer; wherein, the first MOSFET (Q1) and the second MOSFET (Q2) constitute a half-bridge, the half-bridge midpoint is connected to the same end of the primary side (P1) of the transformer, and is connected to the gate of the fourth switch tube (S4) of the main topology gate driver through the bridge arm midpoint; the third MOSFET (Q3) and the fourth MOSFET (Q4) also constitute a half-bridge, the half-bridge midpoint is connected to the non-same end of the primary side (P1) of the transformer through the port, and is connected to the gate of the second switch tube (S2) of the main topology gate driver; the gate parasitic capacitance of the fourth switch tube (S4) of the main topology gate driver is considered to be connected in parallel between the two ends of the second MOSFET (Q2), and the gate parasitic capacitance of the second switch tube (S2) of the main topology gate driver is considered to be connected in parallel between the two ends of the fourth MOSFET (Q4); The transformer has a first secondary side (P2) and a second secondary side (P3) provided with coils to realize floating ground driving and realize multiple isolation driving design; when two complementary isolation drives, the secondary side is designed with two coils, the same end of the upper end coil is connected to the gate parasitic capacitance of the first switch tube (S1) of the main topology, and the non-same end is connected to the other end of the gate parasitic capacitance to float; the non-same end of the lower end coil of the secondary side is connected to the gate parasitic capacitance of the third switch tube (S3) of the main topology, and the same end is connected to the other end of the gate parasitic capacitance to float; The gate input signals of the four MOSFETs are sent by a digital signal processing chip, and then generated by the main topology gate driver; wherein, the first MOSFET (Q1) and the second MOSFET (Q2) are complementary on, and the third MOSFET (Q3) and the fourth MOSFET (Q4) are complementary on.

2. The four-switch resonant gate drive circuit suitable for multiphase driving according to claim 1, characterized in that The phase difference between the second MOSFET (Q2) waveform and the fourth MOSFET (Q4) waveform is 180°, and the phase difference between the first MOSFET (Q1) waveform and the third MOSFET (Q3) waveform is 180°.

3. The four-switch resonant gate drive circuit suitable for multiphase drive according to claim 1, characterized in that The gate input signals are different, and the circuit works in different modes, which can be divided into eight working modes t0-t8. In the eight working modes, the circuit realizes energy recovery of the main topology gate drive through the gate parasitic capacitance and transformer inductance resonance.

4. The four-switch resonant gate drive circuit suitable for multiphase drive according to claim 1, characterized in that The gate signals of the four MOSFETs are controlled by changing the phase of the gate signals of the four MOSFETs. The difference between the turn-on time of the second MOSFET (Q2) and the turn-off time of the fourth MOSFET (Q4) is the first dead time, and the difference between the turn-on time of the fourth MOSFET (Q4) and the turn-off time of the second MOSFET (Q2) is the second dead time.

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