Charge pump circuit

Abstract

The application discloses a charge pump circuit, comprising an auxiliary charge pump and a main charge pump. The power supply end of the auxiliary charge pump is connected with a first power supply voltage, and the output end outputs a first output voltage. The gate of a first NMOS tube is connected with the first output voltage, the drain is connected with a second power supply voltage, and the source outputs a third power supply voltage. The first NMOS tube has a first threshold voltage. The power supply end of the main charge pump is connected with the third power supply voltage, and the output end outputs a second output voltage. The second power supply voltage is greater than the first power supply voltage; the second power supply voltage has a first change range. The first output voltage is within the first change range, and when the second power supply voltage is greater than the first output voltage, the third power supply voltage is clamped at the first output voltage minus the first threshold voltage. The third power supply voltage has a second change range, and the second change range is less than the upper limit of the first change range. The application can prevent the output voltage from generating a ripple defect and improve the area efficiency.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a charge pump circuit. Background Technology

[0002] With the development of semiconductor technology, the operating voltage of devices is getting lower and lower. For memory, the power supply voltage required for operation is constantly shrinking to below 2.5V, 1.8V, or 1V. However, the programming and erasing voltages of memory are much higher than the power supply voltage. That is, the programming and erasing voltages of memory are high voltages relative to the power supply voltage. In this case, a charge pump circuit is usually required to convert the power supply voltage to the required programming or erasing voltage. In integrated circuits, it is often necessary to use both positive and negative voltages simultaneously.

[0003] like Figure 1 The diagram shown is a structural diagram of the first type of charge pump circuit; the power supply terminal of the charge pump 101 is connected to a lower power supply voltage VDD1. Figure 1 The document also shows that the power supply voltage VDD1 ranges from 0.9V to 1.1V, although this range can vary depending on the specific application. The charge pump, controlled by a switching circuit, charges the capacitor, creating a voltage difference between its two electrodes. When the capacitor stores charge, a sudden change in voltage at one electrode causes a sudden change in voltage at the other electrode, thus maintaining a constant voltage difference. When the voltage at one electrode is equal to the power supply voltage VDD1, the voltage at the other electrode is greater than VDD1, resulting in a voltage increase. By cascading multiple charge pump units, a much higher voltage HV than VDD1 can be obtained at the output. The magnitude of the high voltage HV is determined by the needs of the chip, such as memory, which includes flash memory.

[0004] like Figure 2 The diagram shown is a structural diagram of the existing second type of charge pump circuit; the power supply terminal of charge pump 201 is connected to a lower power supply voltage VDD2. Figure 1 The document also shows that the power supply voltage VDD2 ranges from 1.35V to 5.5V, although this range may vary depending on the specific application. Figure 2 The existing second type of charge pump circuit shown and Figure 1 The difference in the existing first type of charge pump circuit is that the power supply voltage VDD2 is greater than the power supply voltage VDD1. Thus, when the same high voltage HV is obtained, the ratio between the high voltage HV and the power supply voltage VDD2 will be less than the ratio between the high voltage HV and the power supply voltage VDD1. Therefore, the number of charge pump units that need to be cascaded in the existing second type of charge pump circuit will be reduced, and the capacitor area will also be reduced, thereby improving the area efficiency and reducing the area of ​​the entire charge pump.

[0005] but, Figure 2 While the existing second type of charge pump circuit shown can reduce the area, the power supply voltage VDD2 has a large variation range. When the power supply voltage VDD2 is high, such as close to 5.5V, it will cause large ripples in the output high voltage HV. That is, the high voltage HV will not be very stable, but will fluctuate up and down, i.e., it will have large jitter. This is not conducive to performing corresponding erase or write operations on the memory. Figure 1 In the existing first type of charge pump circuit shown, the value of the power supply voltage VDD1 is relatively small, even smaller than the lower limit of the power supply voltage VDD2, and the value of the final high voltage HV is very stable and does not fluctuate.

[0006] Therefore, both the existing first and second charge pump circuits have their own advantages and disadvantages. While the first charge pump circuit can generate a stable output voltage, its area efficiency is relatively low. When outputting the same high voltage HV, the area of ​​the first charge pump circuit is larger than that of the second charge pump circuit, increasing cost. Although the area efficiency of the second charge pump circuit is improved, it is prone to causing fluctuations in the output high voltage HV. Increased fluctuations in the high voltage HV affect reliability. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a charge pump circuit that can prevent ripple defects in the output voltage and improve area efficiency to reduce circuit area.

[0008] To solve the above-mentioned technical problems, the charge pump circuit provided by the present invention includes an auxiliary charge pump and a main charge pump.

[0009] The auxiliary charge pump is connected to a first power supply voltage at its power supply terminal, and outputs a first output voltage at its output terminal.

[0010] The first NMOS transistor has its gate connected to the first output voltage, its drain connected to the second power supply voltage, and its source outputting the third power supply voltage; the threshold voltage of the first NMOS transistor is the first threshold voltage.

[0011] The power supply terminal of the main charge pump is connected to the third power supply voltage, and the output terminal of the main charge pump outputs a second output voltage.

[0012] The second power supply voltage is greater than the first power supply voltage; the second power supply voltage has a first range of variation, the lower limit of the first range of variation is a first voltage value, and the upper limit of the first range of variation is a second voltage value.

[0013] The first output voltage is within the first variation range. When the second power supply voltage is greater than the first output voltage, the third power supply voltage is clamped at the first output voltage minus the first threshold voltage.

[0014] The third power supply voltage has a second variation range, the lower limit of the second variation range is the first voltage value, and the upper limit of the second variation range is the difference between the first output voltage and the first threshold voltage.

[0015] The auxiliary charge pump ensures the stability of the first output voltage and thus the stability of the upper limit of the second variation range. The second variation range eliminates the ripple defects in the second output voltage caused by the second power supply voltage located above the upper limit of the second variation range in the first variation range. The voltage in the second variation range being greater than the first power supply voltage increases the area efficiency of the main charge pump.

[0016] A further improvement is that the second power supply voltage is the chip's internal voltage.

[0017] A further improvement is that the chip includes a flash memory chip.

[0018] A further improvement is that the chip is a dual-power supply chip, and the first power supply voltage is also the internal voltage of the chip.

[0019] A further improvement is that the chip is a single-power-supply chip; the first power supply voltage is the output voltage of a low-dropout linear regulator (LDO) circuit, and the power supply terminal of the LDO circuit is connected to the second power supply voltage.

[0020] A further improvement is that the first NMOS transistor is an intrinsic NMOS transistor, and the first threshold voltage is equal to 0V.

[0021] A further improvement is that the auxiliary charge pump includes a multi-stage auxiliary charge pump unit, which includes a first switching circuit and a first capacitor. The first switching circuit is controlled by a first clock signal, and the high level of the first clock signal is the first power supply voltage.

[0022] A further improvement is that the main charge pump includes a multi-stage main charge pump unit, which includes a second switching circuit and a second capacitor. The second switching circuit is controlled by a second clock signal, and the high level of the second clock signal is the third power supply voltage.

[0023] A further improvement is that the input terminal of the first-stage auxiliary charge pump unit is also connected to the first power supply voltage, and the input terminals of the auxiliary charge pump units in the second and subsequent stages are connected to the output terminal of the previous-stage auxiliary charge pump unit.

[0024] A further improvement is that the main charge pump includes a positive voltage main pump, wherein the input terminal of the first-stage main charge pump unit is connected to the second power supply voltage, and the input terminals of the main charge pump units at the second stage and above are connected to the output terminal of the previous-stage main charge pump unit.

[0025] A further improvement is that the main charge pump includes a negative voltage main pump, wherein the input terminal of the first-stage main charge pump unit is connected to ground, and the input terminals of the second and subsequent stages of the main charge pump unit are connected to the output terminal of the previous stage of the main charge pump unit.

[0026] A further improvement is that the first variation range of the second power supply voltage is 1.35V to 5.5V.

[0027] The voltage of the first power supply varies from 0.9V to 1.1V.

[0028] The second output voltage is above 8V.

[0029] A further improvement is that the first output voltage is selected from 1.5V to 1.8V.

[0030] A further improvement is that the first variation range of the second power supply voltage is 1.35V to 5.5V;

[0031] The second output voltage is above 8V.

[0032] A further improvement is that the first power supply voltage is 1.35V; and the first output voltage is between 1.5V and 1.8V.

[0033] The charge pump circuit of this invention does not employ a single power supply voltage charge pump structure, but rather a dual power supply voltage charge pump structure, consisting of an auxiliary charge pump using a first power supply voltage and a main charge pump using a second power supply voltage. Since the second power supply voltage is higher, the area efficiency is higher. That is, when obtaining the same high voltage, the higher the power supply voltage, the smaller the required number of stages and capacitor area will be, thus resulting in higher area efficiency. Ultimately, this reduces the circuit area. In other words, compared to the existing single power supply voltage charge pump structure using a lower first power supply voltage, the charge pump circuit of this invention has a smaller area, and the reduced area lowers the chip cost.

[0034] Meanwhile, since the second power supply voltage has a large variation range, this invention does not directly connect the second power supply voltage to the power supply terminal of the main charge pump. Instead, it uses an auxiliary charge pump to clamp the upper limit of the second power supply voltage, so that the variation range of the third power supply voltage actually connected to the power supply terminal of the main charge pump, i.e. the second variation range, becomes smaller and the upper limit value is stable. This is different from the existing single power supply voltage charge pumps that use the second power supply voltage, which are prone to output voltage ripple. This invention can eliminate the ripple defect of the output voltage of the entire charge pump circuit, i.e. the second output voltage.

[0035] Therefore, the present invention can prevent ripple defects in the output voltage, and at the same time improve area efficiency to reduce circuit area. Attached Figure Description

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0037] Figure 1 This is a structural diagram of the first existing charge pump circuit;

[0038] Figure 2 This is a structural diagram of the existing second type of charge pump circuit;

[0039] Figure 3 This is a structural diagram of the charge pump circuit according to the first embodiment of the present invention;

[0040] Figure 4 This is a structural diagram of the charge pump circuit according to the second embodiment of the present invention. Detailed Implementation

[0041] like Figure 3 The diagram shown is a structural diagram of a charge pump circuit according to a first embodiment of the present invention. The charge pump circuit according to the first embodiment of the present invention includes an auxiliary charge pump 201 and a main charge pump.

[0042] In the first embodiment of the present invention, the main charge pump includes a positive voltage main pump 202a and a negative voltage main pump 202b. Figure 2 In this context, the auxiliary charge pump 201 is also referred to as charge pump1, the positive voltage main voltage pump 202a is also referred to as charge pump2, and the negative voltage main voltage pump 202b is also referred to as charge pump3.

[0043] The power supply terminal of the auxiliary charge pump 201 is connected to the first power supply voltage VDD1, and the output terminal of the auxiliary charge pump 201 outputs the first output voltage Vout1.

[0044] The first NMOS transistor has its gate connected to the first output voltage Vout1, its drain connected to the second power supply voltage VDD2, and its source outputting the third power supply voltage VDD3; the threshold voltage of the first NMOS transistor is the first threshold voltage.

[0045] In some embodiments, the first NMOS transistor is an intrinsic NMOS transistor, and the first threshold voltage is equal to 0V.

[0046] The power supply terminal of the main charge pump is connected to the third power supply voltage VDD3, and the output terminal of the main charge pump outputs a second output voltage. In the first embodiment of the present invention, the second output voltage output by the positive voltage main voltage pump 202a is a positive high voltage HV; the second output voltage output by the negative voltage main voltage pump 202b is a negative high voltage VNEG.

[0047] The second power supply voltage VDD2 is greater than the first power supply voltage VDD1; the second power supply voltage VDD2 has a first range of variation, the lower limit of the first range of variation is a first voltage value, and the upper limit of the first range of variation is a second voltage value.

[0048] The first output voltage Vout1 is within the first variation range. When the second power supply voltage VDD2 is greater than the first output voltage Vout1, the third power supply voltage VDD3 is clamped at the first output voltage Vout1 minus the first threshold voltage.

[0049] The third power supply voltage VDD3 has a second variation range, the lower limit of the second variation range is the first voltage value, and the upper limit of the second variation range is the difference between the first output voltage Vout1 and the first threshold voltage.

[0050] The auxiliary charge pump 201 ensures the stability of the first output voltage Vout1 and thus ensures the stability of the upper limit of the second variation range. The second variation range eliminates the ripple defects of the second output voltage caused by the second power supply voltage VDD2, which is above the upper limit of the second variation range in the first variation range. The voltage of the second variation range is greater than the first power supply voltage VDD1, which at the same time increases the area efficiency of the main charge pump.

[0051] In the first embodiment of the present invention, the auxiliary charge pump 201 includes a multi-stage auxiliary charge pump unit, the auxiliary charge pump unit includes a first switching circuit and a first capacitor, the first switching circuit is controlled by a first clock signal, and the high level of the first clock signal is the first power supply voltage VDD1.

[0052] The input terminal of the first-stage auxiliary charge pump unit is also connected to the first power supply voltage VDD1, and the input terminals of the auxiliary charge pump units of the second stage and above are connected to the output terminal of the previous stage auxiliary charge pump unit.

[0053] In the first embodiment of the present invention, the main charge pump includes a multi-stage main charge pump unit, and the main charge pump unit includes a second switching circuit and a second capacitor. The second switching circuit is controlled by a second clock signal, and the high level of the second clock signal is the third power supply voltage VDD3.

[0054] In the first embodiment of the present invention, in the positive voltage main voltage pump 202a, the input terminal of the first stage main charge pump unit is connected to the second power supply voltage VDD2, and the input terminals of the main charge pump units of the second stage and above are connected to the output terminal of the previous stage main charge pump unit. In this way, based on the second power supply voltage VDD2, the output voltage of the main charge pump units of each stage will increase step by step and finally output a positive high voltage HV.

[0055] The main charge pump includes a negative voltage main pump 202b. In the negative voltage main pump 202b, the input terminal of the first-stage main charge pump unit is connected to ground, and the input terminals of the second and subsequent stages of the main charge pump unit are connected to the output terminal of the previous stage of the main charge pump unit. In this way, based on grounding, the output voltage of each stage of the main charge pump unit will decrease step by step and finally output a negative high voltage VNEG.

[0056] In the first embodiment of the present invention, the charge pump circuit uses a dual-power supply chip. Both the first power supply voltage VDD1 and the second power supply voltage VDD2 are internal voltages of the chip.

[0057] The chip includes a flash memory chip.

[0058] In some embodiments, the first variation range of the second power supply voltage VDD2 is 1.35V to 5.5V, the first voltage value is 1.35V, and the second voltage value is 5.5V. The variation range of the first power supply voltage VDD1 is 0.9V to 1.1V. The second output voltage is 8V or higher. The first output voltage Vout1 is taken in the range of 1.5V to 1.8V.

[0059] In other embodiments, the variation range of the first power supply voltage VDD1 can also be changed according to actual process requirements, and the first variation range of the second power supply voltage VDD2 can also be changed according to actual process requirements. The magnitude of the first output voltage Vout1 can also be changed accordingly, as long as it is ensured that the second output voltage does not exhibit ripple defects.

[0060] The charge pump circuit of the first embodiment of the present invention does not employ a charge pump structure with a single power supply voltage, but rather a charge pump structure with dual power supply voltages. These are an auxiliary charge pump 201 using a first power supply voltage VDD1 and a main charge pump using a second power supply voltage VDD2. Since the second power supply voltage VDD2 is larger, the area efficiency is higher. That is, when the same high voltage is obtained, the larger the power supply voltage, the smaller the required number of stages and capacitor area will be, thus resulting in higher area efficiency. Ultimately, the circuit area can be reduced. In other words, compared to the existing charge pump structure with a lower first power supply voltage VDD1, the area of ​​the charge pump circuit of the first embodiment of the present invention is smaller, and the reduction in area will reduce the cost of the chip.

[0061] Meanwhile, since the second power supply voltage VDD2 has a large variation range, the first embodiment of the present invention does not directly connect the second power supply voltage VDD2 to the power supply terminal of the main charge pump. Instead, it uses the auxiliary charge pump 201 to clamp the upper limit of the second power supply voltage VDD2, so that the variation range of the third power supply voltage VDD3 actually connected to the power supply terminal of the main charge pump, i.e. the second variation range, becomes smaller and the upper limit value is stable. In this way, unlike the existing single power supply voltage charge pump that uses the second power supply voltage VDD2, which is prone to output voltage ripple, the first embodiment of the present invention can eliminate the ripple defect of the output voltage of the entire charge pump circuit, i.e. the second output voltage.

[0062] Therefore, the first embodiment of the present invention can prevent ripple defects in the output voltage, and at the same time improve area efficiency to reduce circuit area.

[0063] like Figure 4 The diagram shown is a structural diagram of the charge pump circuit according to the second embodiment of the present invention. The difference between the charge pump circuit of the second embodiment of the present invention and the charge pump circuit of the first embodiment of the present invention is as follows:

[0064] The chip is a single-power-supply chip; in this case, the chip has only one internal power supply voltage, namely the second power supply voltage VDD2. Since there is no first power supply voltage VDD1, an LDO circuit 203 is required in the second embodiment of the present invention. The first power supply voltage VDD1 is the output voltage of the LDO circuit 203, and the power supply terminal of the LDO circuit 203 is connected to the second power supply voltage VDD2.

[0065] In some embodiments, the first variation range of the second power supply voltage VDD2 is 1.35V to 5.5V. The second output voltage is 8V or higher. The LDO circuit 203 can obtain a relatively accurate first power supply voltage VDD1, such as the first power supply voltage VDD1 being 1.35V; the first output voltage Vout1 is taken in the range of 1.5V to 1.8V. In other embodiments, the value of the first power supply voltage VDD1 can also be changed according to actual process requirements, and the first variation range of the second power supply voltage VDD2 can also be changed according to actual process requirements. The magnitude of the first output voltage Vout1 can also be changed accordingly, as long as it is ensured that the second output voltage does not have ripple defects.

[0066] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A charge pump circuit, characterized by, The auxiliary charge pump and the main charge pump are included; The power supply end of the auxiliary charge pump is connected with the first power supply voltage, and the output end of the auxiliary charge pump outputs the first output voltage; The first NMOS tube has a gate connected with the first output voltage, a drain connected with the second power supply voltage, and a source outputting the third power supply voltage; and the threshold voltage of the first NMOS tube is the first threshold voltage; The power supply end of the main charge pump is connected with the third power supply voltage, and the output end of the main charge pump outputs the second output voltage; The second power supply voltage is greater than the first power supply voltage; The second power supply voltage has a first variation range, the lower limit value of the first variation range is the first voltage value, and the upper limit value of the first variation range is the second voltage value; The first output voltage is located in the first variation range, and when the second power supply voltage is greater than the first output voltage, the third power supply voltage is clamped at the first output voltage minus the first threshold voltage; The third power supply voltage has a second variation range, the lower limit value of the second variation range is the first voltage value, and the upper limit value of the second variation range is the difference between the first output voltage and the first threshold voltage; The auxiliary charge pump ensures the stability of the first output voltage and thereby ensures the stability of the upper limit value of the second variation range, the second variation range eliminates the ripple defects of the second output voltage caused by the second power supply voltage above the upper limit value of the second variation range in the first variation range; and the voltage of the second variation range is greater than the first power supply voltage, so that the area efficiency of the main charge pump is increased.

2. The charge pump circuit of claim 1, wherein: The second power supply voltage is an internal voltage of a chip.

3. The charge pump circuit of claim 2, wherein: The chip includes a flash memory chip.

4. The charge pump circuit of claim 2, wherein: The chip is a dual-power chip, and the first power supply voltage is also an internal voltage of the chip.

5. The charge pump circuit of claim 2, wherein: The chip is a single-power chip; the first power supply voltage is an output voltage of an LDO circuit, and the power supply end of the LDO circuit is connected with the second power supply voltage.

6. The charge pump circuit of claim 1, wherein: The first NMOS tube is an intrinsic NMOS tube, and the first threshold voltage is equal to 0V.

7. The charge pump circuit of claim 1, wherein: The auxiliary charge pump includes a plurality of auxiliary charge pump units, each of which includes a first switch circuit and a first capacitor, and the first switch circuit is controlled by a first clock signal, and the high level of the first clock signal is the first power supply voltage.

8. The charge pump circuit of claim 1, wherein: The main charge pump includes a plurality of main charge pump units, each of which includes a second switch circuit and a second capacitor, and the second switch circuit is controlled by a second clock signal, and the high level of the second clock signal is the third power supply voltage.

9. The charge pump circuit of claim 7, wherein: The input end of the first auxiliary charge pump unit is also connected with the first power supply voltage, and the input end of each auxiliary charge pump unit at a level higher than the second level is connected with the output end of the auxiliary charge pump unit at a level higher than the first level.

10. The charge pump circuit of claim 8, wherein: The main charge pump includes a positive pressure main voltage pump, in which the input end of the first main charge pump unit is connected with the second power supply voltage, and the input end of each main charge pump unit at a level higher than the second level is connected with the output end of the main charge pump unit at a level higher than the first level.

11. The charge pump circuit of claim 8, wherein: The main charge pump comprises a negative voltage main charge pump, in which the input end of the first stage main charge pump unit is connected to ground, and the input end of each stage main charge pump unit from the second stage onwards is connected to the output end of the previous stage main charge pump unit.

12. The charge pump circuit of claim 4, wherein: The first variation range of the second power supply voltage is 1.35V-5.5V. The variation range of the first power supply voltage is 0.9V-1.1V. The second output voltage is 8V or above.

13. The charge pump circuit of claim 12, wherein: The first output voltage is 1.5V-1.8V.

14. The charge pump circuit of claim 5, wherein: The first variation range of the second power supply voltage is 1.35V-5.5V. The second output voltage is 8V or above.

15. The charge pump circuit of claim 14, wherein: The first power supply voltage is 1.35V, and the first output voltage is 1.5V-1.8V.

Images