Content addressable storage, memory, and electronic devices

Abstract

The present disclosure relates to a content addressable memory device, a memory and an electronic device, the device comprising: a plurality of memory cells, each memory cell comprising a read-only memory device, a capacitor, the read-only memory device comprising a first input terminal, a second input terminal and an output terminal, the output terminal of the read-only memory device being connected to a first terminal of the capacitor, the read-only memory device storing data through a connection relationship between the first input terminal, the second input terminal and the output terminal; and a control module connected to each memory cell, configured to: control voltages of the first input terminal and the second input terminal of the read-only memory device of each memory cell to perform a target operation; and determine an operation result of the target operation according to a voltage of a second terminal of the capacitor. The embodiments of the present disclosure implement a content addressable memory device based on a read-only memory device, which can improve the area efficiency of the content addressable memory device, reduce or even eliminate unnecessary energy consumption caused by memory access, and reduce energy consumption.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and more particularly to a content-addressable storage device, memory, and electronic device. Background Technology

[0002] Content-Addressable Memory (CAM) is a type of memory with search capabilities. Its characteristic is that when performing a search operation, input data is used as the search content, the content stored in the memory is matched with the input data, and the address of the matching data in the memory is output as the search result.

[0003] Content-based lookup in CAM enables it to support the needs of some critical applications. In computer networks, a routing table is a collection of data stored in routers or networked computers. The routing table stores paths to specific network addresses, and looking up a routing table is a content-based search method, as described earlier. Traditional lookup methods, such as linear search and hash table search, are software-based lookup methods using Random-Access Memory (RAM), which are slow and insufficient for the lookup requirements of high-speed real-time communication systems. In contrast, the hardware lookup method based on CAM queries all data in memory within the same clock cycle, making the lookup speed unaffected by the size of the routing table. The lookup is completed within one clock cycle, resulting in an average lookup speed far faster than RAM-based lookup methods, significantly improving network transmission speed and network performance.

[0004] Currently, the most common CAMs in academia are mainly based on memory cells composed of Static Random-Access Memory (SRAM), Resistor Random-Access Memory (ReRAM), and Ferroelectric Gate Field-Effect Transistors (FeFETs). These memory cells typically consist of multiple devices, have a large area, and consume a lot of power. Since area determines the manufacturing cost of CAM chips, and power consumption affects the application value of CAM chips, it is essential to reduce the complexity of CAM memory cells, thereby improving the area efficiency and reducing the power consumption of CAMs. Summary of the Invention

[0005] According to one aspect of this disclosure, a content-addressable storage device is provided, the device comprising:

[0006] Multiple storage units are provided, each including a read-only memory device (ROM) and a capacitor. The ROM includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the ROM is connected to the first terminal of the capacitor. The ROM stores data through the connection relationship between the first input terminal, the second input terminal, and the output terminal. When the first input terminal of the ROM is connected to the output terminal, the ROM stores first stored data; or, when the second input terminal of the ROM is connected to the output terminal, the ROM stores second stored data. The voltage levels of the first stored data and the second stored data are different.

[0007] The control module, connected to each storage unit, is used for:

[0008] Voltage control is applied to the first and second input terminals of the read-only storage devices in each storage unit to execute the target operation;

[0009] The result of the target operation is determined based on the voltage at the second terminal of the capacitor.

[0010] In one possible implementation, the target operation includes an XOR logic operation, and the voltage control of the first and second input terminals of the read-only memory devices of each memory cell to execute the target operation includes:

[0011] Ground the first and second input terminals of the read-only memory device to discharge the capacitor;

[0012] Connect the first and second input terminals of the read-only storage device and leave them floating, so that the output terminal is electrically floating;

[0013] The level signal corresponding to the data to be operated on is output to the first input terminal and the second input terminal of the read-only storage device, so that the storage unit performs an XOR logic operation between the data to be operated on and the stored data.

[0014] The step of determining the operation result of the target operation based on the voltage at the second terminal of the capacitor includes:

[0015] The result of an XOR logic operation between the data to be operated input at the first input terminal and the second input terminal and the data stored in the storage device is obtained based on the voltage at the second terminal of the capacitor.

[0016] In one possible implementation, the control module is connected to a first input terminal of the read-only memory device via a first bit line, and to a second input terminal of the read-only memory device via a second bit line. The control module is also connected to a second terminal of the capacitor via a matching line.

[0017] The multiple storage cells are combined into a multi-row, multi-column layout through electrical connections, wherein the electrical connections are as follows: the matching lines of some or all storage cells in the same row are connected, and the first bit line and the second bit line of some or all storage cells in the same column are connected respectively.

[0018] In one possible implementation, the target operation includes a content addressing operation, wherein voltage control is applied to the first and second input terminals of the read-only storage devices of each memory cell to execute the target operation, including:

[0019] Ground the first and second input terminals of each read-only memory device in one or more rows of memory cells, and discharge each capacitor in one or more rows of memory cells;

[0020] Connect the first and second input terminals of each read-only memory device in one or more rows of memory cells to leave them floating, so that each matching line in one or more rows of memory cells is electrically floating.

[0021] Output the level signal corresponding to the data to be operated on to the first and second input terminals of each read-only memory device in one or more rows of memory cells, so that one or more rows of memory cells can perform content addressing operations.

[0022] The step of determining the operation result of the target operation based on the voltage at the second terminal of the capacitor includes:

[0023] The addressing calculation result of the data to be operated is obtained based on the voltage corresponding to the matching line of each row of storage cells.

[0024] In one possible implementation, the target operation includes a content addressing operation, wherein voltage control is applied to the first and second input terminals of the read-only storage devices of each memory cell to execute the target operation, including:

[0025] Ground the first and second input terminals of each read-only memory device in the memory cell connected to the same matching line, and discharge each capacitor in the memory cell connected to the same matching line.

[0026] The first and second input terminals of each read-only memory device in the memory cell connected to the same matching line are connected and left floating, so that each matching line in the memory cell connected to the same matching line is electrically floating.

[0027] The level signal corresponding to the data to be operated on is output to the first and second input terminals of each read-only memory device in the memory cell connected to the same matching line, so that the memory cell connected to the same matching line can perform content addressing operation.

[0028] The step of determining the operation result of the target operation based on the voltage at the second terminal of the capacitor includes:

[0029] The addressing calculation result of the data to be operated is obtained based on the voltage corresponding to the matching line.

[0030] In one possible implementation, the target operation further includes a read operation to read data stored in the storage unit, and the control module is further configured to:

[0031] The voltages of the first and second input terminals are kept complementary. The output terminal is connected to either the first or the second input terminal based on the voltage magnitude, thereby obtaining the stored data.

[0032] In one possible implementation, the control module is further configured to:

[0033] Control at least one storage unit to operate in either a working mode or an idle mode, wherein,

[0034] The target operation is performed in the storage unit in the operating mode, or

[0035] In the idle mode, the first input, second input, and output terminals of the read-only memory device of the storage unit are set to low level.

[0036] According to one aspect of this disclosure, a memory is provided that includes the content-addressable storage means.

[0037] According to one aspect of this disclosure, an electronic device is provided, the electronic device including a memory as described.

[0038] Various aspects of the embodiments of this disclosure implement content-addressable storage devices based on read-only storage devices, which can improve the area efficiency of content-addressable storage devices and reduce or even eliminate unnecessary energy consumption caused by memory access, thereby achieving the purpose of reducing energy consumption.

[0039] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0041] Figure 1 A schematic diagram of a content-addressable storage device according to an embodiment of the present disclosure is shown.

[0042] Figure 2 The diagram illustrates the structure of MIM capacitors and MOM capacitors that can be used in embodiments of this disclosure.

[0043] Figure 3 A schematic diagram is shown illustrating the XOR logic operation performed on the storage cells of a content-addressable storage device according to an embodiment of the present disclosure.

[0044] Figure 4 A schematic diagram of a content-addressable storage device according to an embodiment of the present disclosure is shown.

[0045] Figure 5 The diagram shows the equivalent capacitance that needs to be charged when the content-addressable storage device of this disclosure performs a multiply-accumulate operation and the scale of the storage cell whose logic operation result is '1'.

[0046] Figure 6 A schematic diagram illustrating a content addressing operation using a content addressable storage device according to an embodiment of the present disclosure is shown.

[0047] Figure 7 A schematic diagram of the idle mode of a content-addressable storage device utilizing an embodiment of the present disclosure is shown.

[0048] Figure 8 A schematic diagram of a content-addressable storage device utilizing an embodiment of the present disclosure is shown. Detailed Implementation

[0049] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0050] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0052] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0053] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0054] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0055] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0056] Please see Figure 1 , Figure 1 A schematic diagram of a content-addressable storage device according to an embodiment of the present disclosure is shown.

[0057] like Figure 1 As shown, the device includes:

[0058] Multiple storage units 10, each storage unit 10 including a read-only memory device M1 (ROM) and a capacitor C M The read-only memory device M1 includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the read-only memory device M1 and the capacitor C MThe first terminal is connected, and the read-only memory device M1 stores data through the connection relationship between the first input terminal, the second input terminal, and the output terminal. When the first input terminal of the read-only memory device M1 is connected to the output terminal (i.e., the read-only memory device M1 includes the connection relationship between the first input terminal and the output terminal), the memory device stores first stored data (e.g., high level '1'); or, when the second input terminal of the memory device is connected to the output terminal (i.e., the memory device includes the connection relationship between the second input terminal and the output terminal), the read-only memory device M1 stores second stored data (e.g., low level '0'). The levels of the first stored data and the second stored data are different.

[0059] Control module 20, connected to each storage unit 10, is used for:

[0060] Voltage control is applied to the first and second input terminals of the read-only memory device M1 in each memory cell 10 to execute the target operation;

[0061] According to the capacitor C M The voltage at the second terminal determines the operational result of the target operation.

[0062] The read-only memory device M1 used in this embodiment is a type of non-volatile memory that only reads data and does not write data. The read-only memory device M1 used in this embodiment features high storage density and low power consumption during read operations. This embodiment implements a content-addressable memory device based on the read-only memory device M1, which can improve the area efficiency of the content-addressable memory device and reduce or even eliminate unnecessary energy consumption caused by memory access, thereby achieving the goal of reducing energy consumption.

[0063] Currently, most CAMs using related technologies employ SRAM circuit structures based on at least six transistors (6T) for storage, requiring additional logic operation circuits. Therefore, they typically contain at least ten transistors per storage unit. However, the embodiments disclosed in this disclosure implement data storage based on electrical connections (e.g., for a three-terminal device, when the read-only memory device M1 includes a connection between the first input terminal and the output terminal, the memory device stores first stored data; or, when the memory device includes a connection between the second input terminal and the output terminal, the read-only memory device M1 stores second stored data), eliminating the need for transistors and thus further improving area efficiency. This disclosure does not limit the specific implementation of the read-only memory device M1, as long as a structure capable of storing data based on electrical connections is available.

[0064] It should be noted that, in the embodiments of the present invention, the read-only memory device implemented by electrical connection is only an example. In theory, all devices with similar electrical characteristics can be used to build the CAM circuit proposed in the embodiments of the present invention.

[0065] The matching addressing computation implemented in this embodiment has the advantages of high area efficiency and low power consumption, and can be used in various applications such as route search in high-speed real-time communication systems.

[0066] This disclosure does not limit the specific implementation of the control module 20. Exemplarily, the control module 20 may include a processing component. In one example, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0067] This disclosure embodiment addresses the capacitor C in each storage cell 10. M The implementation method is not limited; for example, such as Figure 3 As shown, capacitor C M This can be achieved using a metal-insulator-metal capacitor (MIM), a metal-oxide-metal capacitor (MOM), the gate capacitance of a transistor, or other forms of capacitance; no specific limitation is made here. Figure 2 The diagram illustrates the structure of MIM capacitors and MOM capacitors that can be used in embodiments of this disclosure.

[0068] It should be noted that the read-only memory device M1 includes an electrical connection (i.e., the connection relationship described above), and this electrical connection connects the output terminal of the read-only memory device M1 to either the first input terminal or the second input terminal of the read-only memory device M1, depending on the data stored in the read-only memory device M1. This disclosure embodiment... Figure 1The present invention provides an example of a read-only memory device M1 storing first stored data (e.g., high level '1') when the read-only memory device M1 includes a connection between the first input terminal and the output terminal; or storing second stored data (e.g., low level '0') when the read-only memory device M1 includes a connection between the second input terminal and the output terminal. However, the present invention is not limited to these embodiments. In actual use, the levels of the first stored data and the second stored data only need to be complementary (opposite). For example, in other embodiments, the first stored data can also be low level '0', and the second stored data can also be high level '1'.

[0069] For example, the operation of this disclosure embodiment may include a read operation to read the data stored in the storage unit 10. For instance, when performing a read operation on the storage unit 10, the voltages of the first input terminal and the second input terminal may be kept complementary (high level 1, low level 0), and the output terminal may be connected to the first input terminal or the second input terminal according to the voltage magnitude of the output terminal, thereby obtaining the stored data.

[0070] When using CAM for matched addressing calculations, the XOR logic computation and weighted summation required to calculate the matched value are critical operations and the main sources of power consumption. For the matched value calculation of input data and stored data, this embodiment can be decomposed into performing an XOR logic computation on each bit of the input data and stored data separately, and then weighted summing the results of the XOR logic computation to obtain the matched value. If both inputs to the XOR logic computation are '0' or '1', the output is '1'; otherwise, the output is '0'. Therefore, the closer the input data and stored data are, the higher the final matched value.

[0071] In one possible implementation, the target operation may include an XOR logic operation, and the voltage control of the first and second input terminals of the read-only storage device M1 of each storage cell 10 to execute the target operation may include:

[0072] Ground the first and second input terminals of the read-only memory device M1, and connect the capacitor C. M Discharge;

[0073] Connect the first and second input terminals of the read-only storage device M1 and leave them floating, so that the output terminal is electrically floating;

[0074] The level signal corresponding to the data to be operated is output to the first input terminal and the second input terminal (1) of the read-only storage device M1, so that the storage unit 10 performs an XOR logic operation between the data to be operated and the stored data.

[0075] Wherein, according to the capacitor C MThe voltage at the second terminal determines the operational result of the target operation, including:

[0076] According to the capacitor C M The voltage at the second terminal is used to obtain the XOR logic operation result between the data to be operated input at the first input terminal and the second input terminal and the data stored in the storage device.

[0077] Please see Figure 3 , Figure 3 A schematic diagram is shown of a storage cell 10 of a content-addressable storage device performing an XOR logic operation according to an embodiment of the present disclosure.

[0078] In one example, such as Figure 3 As shown in (a), the first and second input terminals of the read-only memory device M1 can both be set to VSS, and the capacitor C M The upper plate is first cleared of charge and then kept in a floating state; then the first input terminal of the read-only memory device M1 is kept at VSS, and the second input terminal of the read-only memory device M1 is set to VDD, which is complementary to the voltage of the first input terminal of the read-only memory device M1, indicating that the input data is '0'. Since the output terminal of the storage unit 10 is connected to the second input terminal, that is, the stored data is '0', the voltage of the output terminal of the storage unit 10 is high level VDD, indicating that the output data is '1'. This realizes the XOR logic operation between the input data of the first and second input terminals of the read-only memory device M1 and the data stored in the memory.

[0079] The CAM storage unit 10 proposed according to the embodiments of this disclosure has the advantages of high area efficiency and low power consumption, and can effectively improve the leakage current problem in the idle state. It is a type of in-memory computing circuit that can greatly improve area efficiency and reduce power consumption.

[0080] Of course, the embodiments of this disclosure can configure interfaces for each storage unit 10. For example, the interface of each storage unit 10 includes a first bit line BL, a second bit line BLB, and a matching line ML. In one possible implementation, the control module 20 is connected to the first input terminal of the read-only memory device M1 via the first bit line BL, connected to the second input terminal of the read-only memory device M1 via the second bit line BLB, and connected to the capacitor C via the matching line ML. M The second end.

[0081] Accordingly, in applications, the output terminal of storage unit 10 connected to the first bit line BL is equivalent to storing '1', and connected to the second bit line BLB is equivalent to storing '0'. In practical applications, the connection to the second bit line BLB can also represent '1', and the connection to the first bit line BL can represent '0'. When performing a read operation on storage unit 10, the voltages of the first bit line BL and the second bit line BLB are kept complementary. The voltage magnitude at the output terminal is used to distinguish whether the output terminal is connected to the first bit line BL or the second bit line BLB, thereby obtaining the stored information.

[0082] With this configuration, the control module 20 can directly control the interface of the storage unit 10, in order to Figure 3 Taking the XOR logic operation shown as an example, firstly, the control module 20 can set both the first bit line BL and the second bit line BLB to low level VSS, and the capacitor C... M The upper plate is first cleared of charge and then kept in a floating state; then the first bit line BL is kept at VSS, and the second bit line BLB is set to a high level VDD, which is complementary to the first bit line BL, indicating that the input data is '0'. Since the output terminal of the storage unit 10 is connected to the second bit line BLB, that is, the stored data is '0', the voltage at the output terminal of the storage unit 10 is VDD, which means that the output data is '1', realizing the XOR logic operation between the input data of the first bit line BL and the second bit line BLB and the data stored in the memory.

[0083] Please see Figure 4 , Figure 4 A schematic diagram of a content-addressable storage device according to an embodiment of the present disclosure is shown.

[0084] In one possible implementation, such as Figure 4 As shown, the plurality of storage cells 10 (also referred to as cell circuits) can be combined into a multi-row, multi-column layout by means of electrical connection, and the electrical connection means that the matching lines ML of some or all of the storage cells 10 in the same row are connected (e.g., the cell circuits in the first row have the same matching line ML0), and the first bit line BL and the second bit line BLB of some or all of the storage cells 10 in the same column are connected respectively (e.g., the cell circuits in the first column have the same first bit line BL0 and the second bit line BLB0).

[0085] For example, such as Figure 4 As shown, the control module can input buffers (including operation data) into each first bit line BL and second bit line BLB, and obtain and process the operation results through the matching value processing module in the control module 20.

[0086] Please see Figure 5 , Figure 5The diagram shows the equivalent capacitance that needs to be charged when the content-addressable storage device of this disclosure performs a multiply-accumulate operation and the scale of the storage cell whose logic operation result is '1'.

[0087] It is understood that the array power consumption of the matching addressing calculation circuit in the embodiments of this disclosure lies in the power consumption of capacitor C. M Charging, such as Figure 5 As shown, the equivalent capacitance in the storage cell 10 of this embodiment does not increase linearly with the increase of the proportion of logical operation results in "1". After the proportion of storage cells 10 with logical operation results in "1" exceeds a certain value, this embodiment can greatly reduce the power consumption during the calculation process.

[0088] It should be noted that the conclusion is... Figure 5 The parameters of the resulting device are: the capacitor C of storage cell 10. M The value is 1.2fF, and the array size is 128x128.

[0089] Furthermore, in the idle state, the matching addressing calculation circuit in this embodiment of the present disclosure has almost no leakage current, which can greatly improve the leakage current problem of SRAM memory cell 10 in the idle state.

[0090] In one possible implementation, the target operation may further include a content addressing operation. The voltage control of the first and second input terminals of the read-only storage device M1 of each storage cell 10 to execute the target operation may include:

[0091] Ground the first and second input terminals of each read-only memory device M1 in one or more rows of memory cells 10, and connect each capacitor C in one or more rows of memory cells 10. M Discharge;

[0092] The first and second input terminals of each read-only storage device M1 in one or more rows of storage units 10 are connected and left floating, so that each matching line ML in one or more rows of storage units 10 is electrically left floating.

[0093] The level signal corresponding to the data to be operated is output to the first input terminal and the second input terminal of each read-only memory device M1 in one or more rows of memory cells 10, so that one or more rows of memory cells 10 can perform content addressing operation.

[0094] Wherein, according to the capacitor C M The voltage at the second terminal determines the operational result of the target operation, including:

[0095] The addressing calculation result of the data to be operated is obtained based on the voltage corresponding to the matching line ML of each row of storage cell 10.

[0096] Please see Figure 6 , Figure 6 A schematic diagram illustrating a content addressing operation using a content addressable storage device according to an embodiment of the present disclosure is shown.

[0097] In one example, such as Figure 6 As shown in (a), in this embodiment of the present disclosure, the first bit line BL<0:M> and the second bit line BLB<0:M> of all unit circuit connections can be set to a low level VSS, and the matching line ML and capacitor C can be connected. M The upper plate is first cleared of charge and then kept in a suspended state, where M is an integer.

[0098] In one example, such as Figure 6 As shown in (b), the data that needs to be addressed and matched can be converted into binary numbers to obtain multiple data to be operated on. Each data to be operated on is one bit of the binary number. In this embodiment, the first bit line BL<0:M> and the second bit line BLB<0:M> can be set to different voltage values ​​according to the different data to be operated on. The voltages of the corresponding first bit line BL and the second bit line BLB are complementary, realizing the XOR logic operation between the data to be operated on and the stored data represented by the internal electrical connection method of the storage unit 10. The circuit connected to the entire matching line ML is normalized and accumulated. The control module 20 obtains a voltage value from VDD to VSS through the matching line ML. The closer the voltage value is to 1, the more successful the matching is.

[0099] Of course, in addition to arranging the storage units 10 in rows or columns, the embodiments of this disclosure can also arrange the storage units 10 in other ways. Correspondingly, when performing content addressing, the addressing and matching of a certain data can be performed according to the matching line ML. For example, assuming that multiple storage units 10 are distributed in different rows and columns, but connected to the same matching line ML, the data to be addressed and matched can be converted into binary numbers to obtain multiple data to be operated on. Each data to be operated on is one bit of the binary number, and each data to be operated on is assigned to each storage unit 10 on the matching line ML to perform logical XOR operations respectively. The circuit connected to the entire matching line ML is normalized and accumulated. The control module 20 obtains a voltage value from VDD to VSS through the matching line ML. The closer the voltage value is to 1, the more successful the matching is.

[0100] In one possible implementation, the target operation includes a content addressing operation, and the voltage control of the first and second input terminals of the read-only storage device M1 of each storage cell 10 to execute the target operation may include:

[0101] The first and second input terminals of each read-only memory device M1 in the memory cell 10 connected to the same matching line ML are grounded, and each capacitor CM in the memory cell 10 connected to the same matching line ML is discharged.

[0102] The first and second input terminals of each read-only storage device M1 in the storage cell 10 connected to the same matching line ML are connected and left floating, so that each matching line ML in the storage cell 10 connected to the same matching line ML is electrically floating.

[0103] The level signal corresponding to the data to be operated is output to the first and second input terminals of each read-only memory device M1 in the memory cell 10 connected to the same matching line ML, so that the memory cell 10 connected to the same matching line ML performs content addressing operation.

[0104] Wherein, according to the capacitor C M The voltage at the second terminal determines the operational result of the target operation, including:

[0105] The addressing calculation result of the data to be operated is obtained based on the voltage corresponding to the matching line ML.

[0106] The present invention does not limit the arrangement of the multiple storage units 10. They can be arranged in a multi-row, multi-column array or in other ways. For different arrangement methods, the present invention can achieve address matching of the data to be matched, which increases the flexibility.

[0107] In one possible implementation, the control module 20 can also be used for:

[0108] Control at least one storage unit 10 to operate in either a working mode or an idle mode, wherein,

[0109] The target operation is performed in the storage unit 10 in the operating mode, or

[0110] In the idle mode, the first input, second input, and output terminals of the read-only memory device M1 of the storage unit 10 are set to a low level VSS.

[0111] In the working mode, the configuration of the first bit line BL and the second bit line BLB of each storage unit 10 is as described above and will not be repeated here.

[0112] Please see Figure 7 , Figure 7 A schematic diagram of the idle mode of a content-addressable storage device utilizing an embodiment of the present disclosure is shown.

[0113] In one example, such as Figure 7As shown, in this embodiment of the present disclosure, the first input terminal, the second input terminal, and the output terminal of the read-only memory device M1 of the storage unit 10 are set to low level. That is, each bit line BL, the second bit line BLB, and the matching line ML are all set to low level, thereby reducing array power consumption. Moreover, the information stored in the circuit unit has non-volatile characteristics and will not cause data loss.

[0114] Please see Figure 8 , Figure 8 A schematic diagram of a content-addressable storage device utilizing an embodiment of the present disclosure is shown.

[0115] For example, such as Figure 8 As shown, the control module 20 can drive each first bit line BL and second bit line BLB through the bit line driver, configure each matching line ML through the matching value processing module (configure it as floating state in the same OR logic operation), and obtain the operation result from the matching line ML. For example, the data to be matched is input through the first bit line BL and the second bit line BLB, and the result of the matching value calculation is output to the matching value processing module for subsequent other operations.

[0116] According to one aspect of this disclosure, a memory is provided that includes the content-addressable storage means.

[0117] According to one aspect of this disclosure, an electronic device is provided, the electronic device including a memory as described.

[0118] The content-addressable memory device of the present disclosure has the advantages of high area efficiency and low power consumption, and can effectively improve the leakage problem of SRAM memory cell 10 in the idle state. It is a type of content-addressable memory circuit that can greatly improve area efficiency and reduce power consumption.

[0119] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Without departing from the scope and spirit of the described embodiments, further interpretation is possible.

[0120] Many modifications and variations will be apparent to those skilled in the art. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A content-addressable storage device, characterized in that, The device includes: Multiple storage units are provided, each including a read-only memory device (ROM) and a capacitor. The ROM includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the ROM is connected to the first terminal of the capacitor. The ROM stores data through the connection relationship between the first input terminal, the second input terminal, and the output terminal. When the first input terminal of the ROM is connected to the output terminal, the ROM stores first stored data; or, when the second input terminal of the ROM is connected to the output terminal, the ROM stores second stored data. The voltage levels of the first stored data and the second stored data are different. The control module, connected to each storage unit, is used for: Voltage control is applied to the first and second input terminals of the read-only storage devices in each storage unit to execute the target operation; The result of the target operation is determined based on the voltage at the second terminal of the capacitor. The target operation includes an XOR logic operation. The voltage control of the first and second input terminals of each memory cell's read-only storage device to execute the target operation includes: Ground the first and second input terminals of the read-only memory device to discharge the capacitor; Connect the first and second input terminals of the read-only storage device and leave them floating, so that the output terminal is electrically floating; The level signal corresponding to the data to be operated on is output to the first input terminal and the second input terminal of the read-only storage device, so that the storage unit performs an XOR logic operation between the data to be operated on and the stored data. The step of determining the operation result of the target operation based on the voltage at the second terminal of the capacitor includes: The result of an XOR logic operation between the data to be operated input at the first input terminal and the second input terminal and the data stored in the storage device is obtained based on the voltage at the second terminal of the capacitor.

2. The apparatus according to claim 1, characterized in that, The control module is connected to the first input terminal of the read-only memory device via a first bit line, and to the second input terminal of the read-only memory device via a second bit line. The control module is also connected to the second terminal of the capacitor via a matching line. The multiple storage cells are combined into a multi-row, multi-column layout through electrical connections, wherein the electrical connections are as follows: the matching lines of some or all storage cells in the same row are connected, and the first bit line and the second bit line of some or all storage cells in the same column are connected respectively.

3. The apparatus according to claim 2, characterized in that, The target operation includes a content addressing operation. The voltage control of the first and second input terminals of each read-only storage device in the memory cell to execute the target operation includes: Ground the first and second input terminals of each read-only memory device in one or more rows of memory cells, and discharge each capacitor in one or more rows of memory cells; Connect the first and second input terminals of each read-only memory device in one or more rows of memory cells to leave them floating, so that each matching line in one or more rows of memory cells is electrically floating. Output the level signal corresponding to the data to be operated on to the first and second input terminals of each read-only memory device in one or more rows of memory cells, so that one or more rows of memory cells can perform content addressing operations. The step of determining the operation result of the target operation based on the voltage at the second terminal of the capacitor includes: The addressing calculation result of the data to be operated is obtained based on the voltage corresponding to the matching line of each row of storage cells.

4. The apparatus according to any one of claims 1-2, characterized in that, The target operation includes a content addressing operation. The voltage control of the first and second input terminals of each read-only storage device in the memory cell to execute the target operation includes: Ground the first and second input terminals of each read-only memory device in the memory cell connected to the same matching line, and discharge each capacitor in the memory cell connected to the same matching line. The first and second input terminals of each read-only memory device in the memory cell connected to the same matching line are connected and left floating, so that each matching line in the memory cell connected to the same matching line is electrically floating. The level signal corresponding to the data to be operated on is output to the first and second input terminals of each read-only memory device in the memory cell connected to the same matching line, so that the memory cell connected to the same matching line can perform content addressing operation. The step of determining the operation result of the target operation based on the voltage at the second terminal of the capacitor includes: The addressing calculation result of the data to be operated is obtained based on the voltage corresponding to the matching line.

5. The apparatus according to claim 1, characterized in that, The target operation also includes a read operation to read data stored in the storage unit, and the control module is further configured to: The voltages of the first and second input terminals are kept complementary. The output terminal is connected to either the first or the second input terminal based on the voltage magnitude, thereby obtaining the stored data.

6. The apparatus according to any one of claims 1-3, characterized in that, The control module is also used for: Control at least one storage unit to operate in either a working mode or an idle mode, wherein, The target operation is performed in the storage unit in the operating mode, or In the idle mode, the first input, second input, and output terminals of the read-only memory device of the storage unit are set to low level.

7. A memory, characterized in that, The memory includes the content-addressable storage device as described in any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes the memory as described in claim 7.

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