Logic circuit for dc-dc converter and dc-dc converter

Abstract

Embodiments of the present disclosure provide a logic circuit for a DC-DC converter and the DC-DC converter. The logic circuit comprises a first step detection circuit, an upper tube off control circuit, and a lower tube off control circuit. The first step detection circuit is configured to detect a first step of an output voltage of the DC-DC converter in a soft start stage according to one of an upper tube off signal output by the upper tube off control circuit and a lower tube off signal output by the lower tube off control circuit, a feedback voltage of the DC-DC converter, and a first reference voltage from a first reference voltage terminal to generate a first step indication signal. The upper tube off control circuit is configured to make the upper tube off signal at a valid level to indicate to turn off an upper tube of the DC-DC converter in a case that the first step indication signal is at the valid level. The lower tube off control circuit is configured to make the lower tube off signal at the valid level to indicate to turn off a lower tube of the DC-DC converter in the case that the first step indication signal is at the valid level.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to logic circuits for DC-DC converters and DC-DC converters. Background Technology

[0002] DC-DC converters are widely used in various chip power supply applications. DC-DC converters include buck converters and boost converters. Buck converters convert higher DC voltages to lower DC voltages, while boost converters convert lower DC voltages to higher DC voltages. During the power-up process of a DC-DC converter, if its output voltage rises too quickly, the converter will draw excessive energy from the preceding stage (the power supply stage of the DC-DC converter). To protect the preceding stage power supply, the DC-DC converter has a soft-start process during power-up. Soft-start allows the DC-DC converter's output voltage to rise from zero volts to its rated value at a slower rate. This allows the DC-DC converter to transfer energy slowly, preventing it from drawing excessive energy from the input (the preceding stage) and damaging it. Summary of the Invention

[0003] The embodiments described herein provide a logic circuit for a DC-DC converter and a DC-DC converter.

[0004] According to a first aspect of this disclosure, a logic circuit for a DC-DC converter is provided. The logic circuit includes: a first-step detection circuit, an upper transistor turn-off control circuit, and a lower transistor turn-off control circuit. The first-step detection circuit is configured to: detect the first step of the output voltage of the DC-DC converter during the soft-start phase based on one of an upper transistor turn-off signal output by the upper transistor turn-off control circuit and a lower transistor turn-off signal output by the lower transistor turn-off control circuit, the feedback voltage of the DC-DC converter, and a first reference voltage from a first reference voltage terminal, to generate a first-step indication signal. The upper transistor turn-off control circuit is configured to: when the first-step indication signal is at an active level, enable the upper transistor turn-off signal to be at an active level to indicate the turn-off of the upper transistor of the DC-DC converter. The lower transistor turn-off control circuit is configured to: when the first-step indication signal is at an active level, enable the lower transistor turn-off signal to be at an active level to indicate the turn-off of the lower transistor of the DC-DC converter.

[0005] In some embodiments of this disclosure, the first step detection circuit includes: a ramp signal generation circuit, a start control circuit, a first RS flip-flop, an error amplifier, and an output circuit. The ramp signal generation circuit is configured to generate a ramp signal. The start control circuit is configured to generate a start detection signal based on the ramp signal and a first reference voltage. The start detection signal is at a first level when the ramp signal is below the first reference voltage. The start detection signal flips to a second level when the ramp signal rises to the first reference voltage. The set terminal of the first RS flip-flop is provided with the start detection signal. The reset terminal of the first RS flip-flop is provided with one of a lower transistor turn-off signal and an upper transistor turn-off signal. A first enable signal is output from the output terminal of the first RS flip-flop. The first input terminal of the error amplifier is provided with the ramp signal. The second input terminal of the error amplifier is provided with a feedback voltage. A soft-start control signal is output from the output terminal of the error amplifier. The output circuit is configured to make the first step indication signal active when both the soft-start control signal and the first enable signal are active.

[0006] In some embodiments of this disclosure, the start-up control circuit includes a voltage comparator and a first inverter. A ramp signal is provided to the first input terminal of the voltage comparator. The second input terminal of the voltage comparator is coupled to a first reference voltage terminal. The output terminal of the voltage comparator is coupled to the input terminal of the first inverter. The output terminal of the first inverter is coupled to the set terminal of a first RS flip-flop.

[0007] In some embodiments of this disclosure, the start-up control circuit includes a voltage comparator. A first input terminal of the voltage comparator is coupled to a first reference voltage terminal. A second input terminal of the voltage comparator is provided with a ramp signal. The output terminal of the voltage comparator is coupled to the set terminal of a first RS flip-flop.

[0008] In some embodiments of this disclosure, the ramp signal generation circuit includes a first current source and a first capacitor. The first current source is configured to provide a first current to a first terminal of the first capacitor. A second terminal of the first capacitor is coupled to a second voltage terminal. A ramp signal is generated at the first terminal of the first capacitor.

[0009] In some embodiments of this disclosure, the output circuit includes a second inverter and an AND gate. The input of the second inverter is coupled to the output of an error amplifier. The output of the second inverter is coupled to the first input of the AND gate. The second input of the AND gate is coupled to the output of a first RS flip-flop. A first step indication signal is output from the output of the AND gate.

[0010] In some embodiments of this disclosure, the upper transistor turn-off control circuit includes a second RS flip-flop. The set terminal of the second RS flip-flop is provided with a first-step indication signal. An upper transistor turn-off signal is output from the output terminal of the second RS flip-flop.

[0011] In some embodiments of this disclosure, the lower transistor turn-off control circuit includes a delay circuit and a third RS flip-flop. The delay circuit is configured to delay the first step indication signal to output a delayed first step indication signal. The set terminal of the third RS flip-flop is provided with the delayed first step indication signal. A lower transistor turn-off signal is output from the output terminal of the third RS flip-flop.

[0012] In some embodiments of this disclosure, the first RS flip-flop includes a first NOR gate and a second NOR gate. A first input terminal of the first NOR gate is provided with a start detection signal. The second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate. The output terminal of the first NOR gate is coupled to the first input terminal of the second NOR gate. The second input terminal of the second NOR gate is coupled to the output terminal of the second RS flip-flop. The output terminal of the second NOR gate is the output terminal of the first RS flip-flop.

[0013] In some embodiments of this disclosure, the first RS flip-flop includes a first NOR gate and a second NOR gate. A first input of the first NOR gate is provided with a start detection signal. The second input of the first NOR gate is coupled to the output of the second NOR gate. The output of the first NOR gate is coupled to the first input of the second NOR gate. The second input of the second NOR gate is coupled to the output of a third RS flip-flop. The output of the second NOR gate is the output of the first RS flip-flop.

[0014] In some embodiments of this disclosure, the second RS flip-flop includes a third NOR gate and a fourth NOR gate. The first input of the third NOR gate is provided with a first-step indication signal. The second input of the third NOR gate is coupled to the output of the fourth NOR gate. The output of the third NOR gate is coupled to the first input of the fourth NOR gate. The output of the fourth NOR gate is the output of the second RS flip-flop.

[0015] In some embodiments of this disclosure, the third RS flip-flop includes a fifth NOR gate and a sixth NOR gate. The first input of the fifth NOR gate is provided with a delayed first-step indication signal. The second input of the fifth NOR gate is coupled to the output of the sixth NOR gate. The output of the fifth NOR gate is coupled to the first input of the sixth NOR gate. The output of the sixth NOR gate is the output of the third RS flip-flop.

[0016] According to a second aspect of this disclosure, a logic circuit for a DC-DC converter is provided. The logic circuit includes: a first current source, a first capacitor, a voltage comparator, a first inverter, a second inverter, an AND gate, an error amplifier, a first RS flip-flop, a second RS flip-flop, a third RS flip-flop, and a delay circuit. The first current source is configured to provide a first current to a first terminal of the first capacitor. The second terminal of the first capacitor is coupled to a second voltage terminal. The first input terminal of the error amplifier is coupled to the first terminal of the first capacitor. The second input terminal of the error amplifier is coupled to the feedback voltage terminal of the DC-DC converter. The output terminal of the error amplifier is coupled to the input terminal of the second inverter. The first input terminal of the voltage comparator is coupled to the first terminal of the first capacitor. The second input terminal of the voltage comparator is coupled to a first reference voltage terminal. The output terminal of the voltage comparator is coupled to the input terminal of the first inverter. The output terminal of the first inverter is coupled to the set terminal of the first RS flip-flop. The reset terminal of the first RS flip-flop is coupled to one of the output terminals of the second and third RS flip-flops. The output terminal of the second inverter is coupled to the first input terminal of the AND gate. The second input of the AND gate is coupled to the output of the first RS flip-flop. The output of the AND gate is coupled to the set input of the second RS flip-flop and a delay circuit. A turn-off signal for the upper transistor is output from the output of the second RS flip-flop. The delay circuit is configured to delay the first-step indication signal output from the AND gate to output a delayed first-step indication signal. The set input of the third RS flip-flop is provided with a delayed first-step indication signal. A turn-off signal for the lower transistor is output from the output of the third RS flip-flop. The effective level of the upper transistor turn-off signal indicates the turn-off of the upper transistor of the DC-DC converter. The effective level of the lower transistor turn-off signal indicates the turn-off of the lower transistor of the DC-DC converter.

[0017] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes the logic circuitry described in the first or second aspect of this disclosure.

[0018] According to a fourth aspect of this disclosure, a chip is provided. The chip includes the DC-DC converter described in a third aspect of this disclosure.

[0019] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a fourth aspect of this disclosure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0021] Figure 1 This is the basic topology diagram of a buck converter;

[0022] Figure 2 This is an exemplary circuit diagram of a soft-start circuit;

[0023] Figure 3 Is using Figure 2 An exemplary timing diagram of the soft-start process performed by the soft-start circuit shown;

[0024] Figure 4 This is a schematic block diagram of a logic circuit for a DC-DC converter according to embodiments of the present disclosure;

[0025] Figure 5 yes Figure 4 A further schematic block diagram of the logic circuit shown;

[0026] Figure 6 yes Figure 5 An exemplary circuit diagram of the logic circuit shown;

[0027] Figure 7 This is an exemplary timing diagram of a soft-start process performed using logic circuitry according to embodiments of the present disclosure; and

[0028] Figure 8 yes Figure 3 and Figure 7 The diagram shows a comparison of the soft-start process.

[0029] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, statements that “connect” or “couple” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components. Furthermore, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0032] Figure 1 The basic topology of a buck converter is shown. In this buck converter, the upper transistor HS and the lower transistor LS are alternately turned on and off under the control of the upper transistor drive signal DH and the lower transistor drive signal DL, respectively. When the upper transistor HS is on, the inductor current IL rises, with a slope of (VIN-VO) / L. When the lower transistor LS is on, the inductor current IL falls, with a slope of VO / L. Here, VIN represents the input voltage, VO represents the output voltage, and L represents the inductance value of the inductor. Figure 1 In this circuit, the feedback voltage FB is equal to the voltage drop across the two resistors equal to the output voltage VO. The waveform of the feedback voltage FB follows the waveform of the output voltage VO. Figure 1 The output capacitor Cout and the load current source Iload are also shown.

[0033] As mentioned above, there is a soft-start process during the power-on of a DC-DC converter. Figure 2 An exemplary circuit diagram for a soft-start circuit of a DC-DC converter is shown. During soft-start, a first current I1 from a first current source I1 charges capacitor CSS, thereby generating a ramp signal VRAMP on the upper plate of capacitor CSS. The feedback voltage FB and the ramp signal VRAMP are compared by an error amplifier EA. When the feedback voltage FB is higher than the ramp signal VRAMP, the soft-start control signal SS_ctl is low, controlling the lower transistor LS to turn on. The lower transistor LS remains on until the inductor current IL drops to zero amperes or the ramp signal VRAMP rises to the feedback voltage FB. Therefore, the feedback voltage FB will not be much higher than the ramp signal VRAMP. The upper transistor HS only turns on when the feedback voltage FB is lower than the ramp signal VRAMP, so the feedback voltage FB and the ramp signal VRAMP rise very close together during soft-start. The ramp signal VRAMP is generated by charging the large capacitor CSS with a small current I1, so the feedback voltage FB rises slowly, and the output voltage VO also rises slowly.

[0034] In practical applications, the capacitor CSS may be located externally to the DC-DC converter. The pin connected to the capacitor CSS is labeled SS. If the upper plate of the capacitor CSS (pin SS) is shorted to ground, the ramp signal VRAMP will never rise. If switching of the upper and lower transistors is allowed at this time, various abnormal situations may occur, such as the upper and lower transistors continuously switching in Forced Continuous Conductive Mode (FCCM mode). Therefore, switching should only be allowed after the ramp signal VRAMP rises to a certain value. Therefore, in Figure 2 The soft-start circuit shown includes a voltage comparator CMP. The CMP compares the ramp signal VRAMP with the reference voltage Vref1 to generate the signal SS_shortb. The SS_shortb signal can be provided to the circuitry in the DC-DC converter used to generate the upper MOSFET drive signal DH and the lower MOSFET drive signal DL to indicate whether switching is permitted. When the ramp signal VRAMP rises to the reference voltage Vref1, the SS_shortb signal flips high, indicating that switching is permitted.

[0035] Figure 3 Showing the use Figure 2 An exemplary timing diagram of the soft-start process performed by the shown soft-start circuit. (See diagram for reference.) Figure 3 As shown, the stepped voltage (as indicated by the dashed line) is the feedback voltage FB, the sloping line is the ramp signal VRAMP, and the sawtooth current is the inductor current IL.

[0036] At time t1, all modules inside the DC-DC converter are enabled, and the ramp signal VRAMP begins to rise. At time t2, the ramp signal VRAMP rises to the threshold that allows switching to begin (…). Figure 2 When the reference voltage Vref1 is reached, the upper transistor HS turns on and begins to supply energy to the output of the DC-DC converter. Since the output voltage VO is zero at this time, the slope of the inductor current IL's rise is very large (equal to VIN / L), and the slope of the inductor current IL's fall is almost zero (equal to -VO / L). Therefore, the inductor current IL rises rapidly. At time t3, the feedback voltage FB rises to equal the ramp signal VRAMP, at which point the lower transistor turns on. Because the output voltage VO is not very high (e.g., 100mV to 200mV), the inductor current IL falls relatively slowly. It is not until time t4 that the inductor current IL drops to zero. At time t5, the ramp signal VRAMP rises above the feedback voltage FB, and the upper transistor HS continues to turn on to supply energy to the output.

[0037] from Figure 3It can be observed that at the very beginning of soft start (especially when the DC-DC converter has a small duty cycle), the height of the first step of the feedback voltage FB (the step before time t5) is much greater than that of subsequent steps (the step after time t5). This is because the inductor current IL has the highest rising slope at the beginning of soft start, and the ramp signal VRAMP needs to rise to a certain value ( Figure 2 The reference voltage Vref1 is required for the transistor to turn on. Therefore, the inductor current IL will be very high in the first few cycles. Furthermore, during the decrease of the inductor current IL after the feedback voltage FB exceeds the ramp signal VRAMP (between t3 and t4), all energy is transferred to the output, causing the feedback voltage FB to rise excessively. If the first step of the output voltage VO during soft start rises to the turn-on voltage of the next stage circuit, the next stage circuit will start working. However, the next stage circuit, acting as a load, will pull the output voltage VO down. When the output voltage VO is too low, the next stage circuit will stop working. This creates a risk of the next stage circuit turning on and off repeatedly. Moreover, if the DC-DC converter is soft-started under load, there is a risk of excessive ripple in the output voltage VO and inductor current IL at the beginning of the soft start.

[0038] Therefore, embodiments of this disclosure propose a logic circuit for a DC-DC converter designed to reduce the magnitude of the first step of the output voltage during the soft-start phase, thereby enabling the DC-DC converter to operate more stably. Figure 4 A schematic block diagram of a logic circuit 400 for a DC-DC converter according to an embodiment of the present disclosure is shown. The logic circuit 400 includes: a first-step detection circuit 410, an upper transistor turn-off control circuit 420, and a lower transistor turn-off control circuit 430.

[0039] The first step detection circuit 410 is coupled to the upper MOSFET turn-off control circuit 420 and the lower MOSFET turn-off control circuit 430. The first step detection circuit 410 is configured to detect the first step of the output voltage VO of the DC-DC converter during the soft-start phase based on one of the upper MOSFET turn-off signal CLOSE_H output by the upper MOSFET turn-off control circuit 420 and the lower MOSFET turn-off signal CLOSE_L output by the lower MOSFET turn-off control circuit 430, the feedback voltage FB of the DC-DC converter, and the first reference voltage Vref1 from the first reference voltage terminal Vref1, to generate a first step indication signal PFM_FIR. Upon detecting the first step of the output voltage VO, the first step indication signal PFM_FIR toggles to an active level. In some embodiments of this disclosure, the active level of the first step indication signal PFM_FIR is high.

[0040] The upper transistor turn-off control circuit 420 is coupled to the first-step detection circuit 410 and the lower transistor turn-off control circuit 430. The upper transistor turn-off control circuit 420 is configured to, when the first-step indication signal PFM_FIR is at an active level, cause the upper transistor turn-off signal CLOSE_H to be at an active level to indicate the turn-off of the upper transistor HS of the DC-DC converter. In some embodiments of this disclosure, the upper transistor turn-off control circuit 420 is further configured to, when the first-step indication signal PFM_FIR is at an inactive level, control the upper transistor turn-off signal CLOSE_H according to the upper transistor control signal in the DC-DC converter.

[0041] The lower MOSFET turn-off control circuit 430 is coupled to the first-step detection circuit 410 and the upper MOSFET turn-off control circuit 420. The lower MOSFET turn-off control circuit 430 is configured to, when the first-step indication signal PFM_FIR is at an active level, cause the lower MOSFET turn-off signal CLOSE_L to be at an active level to indicate the turn-off of the lower MOSFET LS of the DC-DC converter. In some embodiments of this disclosure, the lower MOSFET turn-off control circuit 430 is further configured to, when the first-step indication signal PFM_FIR is at an inactive level, control the lower MOSFET turn-off signal CLOSE_L according to the lower MOSFET control signal in the DC-DC converter.

[0042] According to an embodiment of this disclosure, the logic circuit 400 controls the shutdown of both the upper transistor HS and the lower transistor LS of the DC-DC converter when the output voltage VO reaches its first step (the feedback voltage FB reaches its first step). Reference Figure 1 In this case, the inductor current IL discharges through the body diode of the lower transistor LS, at which point VO = V. SW = -0.7V. Where V SW This represents the voltage value at point SW. If the lower transistor LS is turned on to discharge the inductor current IL, the slope of the inductor current IL is -VO / L. If both the upper transistor HS and the lower transistor LS are turned off to discharge the inductor current IL, the slope of the inductor current IL is (-V / L). SW -VO) / L. In this way, the slope of the inductor current IL increases several times, which can quickly discharge the inductor current IL to zero amperes.

[0043] Figure 7 An exemplary timing diagram is shown illustrating a soft-start process performed using logic circuitry according to embodiments of the present disclosure. Reference Figure 7 As can be seen, when the feedback voltage FB reaches its first step (at time t3), the slope of the inductor current IL (from time t3 to time t6) increases, thus dropping to zero ampere more quickly. At time t7, the ramp signal VRAMP rises above the feedback voltage FB, and the upper transistor HS continues to be turned on to deliver energy to the output.

[0044] In this way, the output voltage VO of the DC-DC converter using the logic circuit 400 of this embodiment increases slowly, preventing the next stage circuit from turning on and off repeatedly. It also avoids the risk of excessive ripple in the output voltage VO and inductor current IL.

[0045] Figure 8 Show Figure 3 and Figure 7 The diagram shows a comparison of the soft boot process. Figure 8 In the diagram, the decrease in inductor current between time t3 and t4 is represented by the shaded area. The energy in the shaded area is not transferred to the output terminal; therefore, the first step of the output voltage is significantly reduced. From Figure 8 As can be seen, the difference between the first step of the feedback voltage FB and the threshold (Vref1) at which the ramp signal VRAMP rises to start the switch is significantly reduced. This operation only needs to be performed once, so it will not affect subsequent soft starts or normal operation after the soft start.

[0046] In some embodiments of this disclosure, after the upper transistor turn-off signal CLOSE_H or the lower transistor turn-off signal CLOSE_L flips to an active level, the first step detection circuit 410 can control the first step indicator signal PFM_FIR to remain at an inactive level. Thus, the first step indicator signal PFM_FIR no longer affects the upper transistor turn-off signal CLOSE_H and the lower transistor turn-off signal CLOSE_L, thereby allowing the upper transistor HS and the lower transistor LS to normally alternately turn on and off.

[0047] Figure 5 Show Figure 4 A further schematic block diagram of the logic circuit shown. In logic circuit 500, the first step detection circuit 510 includes: a ramp signal generation circuit 511, a start control circuit 512, a first RS flip-flop 513, an error amplifier EA, and an output circuit 514.

[0048] The output of the ramp signal generation circuit 511 is coupled to the input of the start-up control circuit 512 and the first input of the error amplifier EA. The ramp signal generation circuit 511 is configured to generate a ramp signal VRAMP.

[0049] The input terminal of the startup control circuit 512 is coupled to the first input terminal of the ramp signal generation circuit 511 and the error amplifier EA. The output terminal of the startup control circuit 512 is coupled to the first RS flip-flop 513. The startup control circuit 512 is also coupled to the first reference voltage terminal Vref1. The startup control circuit 512 is configured to generate a startup detection signal SS_short based on the ramp signal VRAMP and the first reference voltage Vref1. The startup detection signal SS_short is at a first level when the ramp signal VRAMP is lower than the first reference voltage Vref1. The startup detection signal SS_short flips to a second level when the ramp signal VRAMP rises to the first reference voltage Vref1. In some embodiments of this disclosure, the first level is high, and the second level is low.

[0050] The set input of the first RS flip-flop 513 is provided with a start detection signal SS_short. The reset input of the first RS flip-flop 513 is provided with one of the lower transistor turn-off signal CLOSE_L and the upper transistor turn-off signal CLOSE_H (in... Figure 5 In the example, the reset terminal of the first RS flip-flop 513 is provided with a lower transistor turn-off signal CLOSE_L, but the reset terminal of the first RS flip-flop 513 can also be provided with an upper transistor turn-off signal CLOSE_H. A first enable signal EN1 is output from the output terminal of the first RS flip-flop 513. In some embodiments of this disclosure, the first enable signal EN1 is active when the set terminal of the first RS flip-flop 513 is active and the reset terminal of the first RS flip-flop 513 is inactive. The first enable signal EN1 is inactive when the set terminal of the first RS flip-flop 513 is inactive and the reset terminal of the first RS flip-flop 513 is active. The level of the first enable signal EN1 remains unchanged when both the set and reset terminals of the first RS flip-flop 513 are inactive. In some embodiments of this disclosure, the active level of the first RS flip-flop 513 is high.

[0051] The first input of error amplifier EA is supplied with a ramp signal VRAMP. The second input of error amplifier EA is supplied with a feedback voltage FB. A soft-start control signal SS_ctl is output from the output of error amplifier EA. Figure 5In the example, the first input terminal of the error amplifier EA is a non-inverting input terminal, and the second input terminal of the error amplifier EA is an inverting input terminal. In some embodiments of this disclosure, when the feedback voltage FB is lower than the ramp signal VRAMP, the soft-start control signal SS_ctl is at an invalid level. When the feedback voltage FB rises to the ramp signal VRAMP, the soft-start control signal SS_ctl flips to an active level. In some embodiments of this disclosure, the active level of the soft-start control signal SS_ctl is a low level, and the invalid level of the soft-start control signal SS_ctl is a high level.

[0052] The two inputs of output circuit 514 are coupled to the output of error amplifier EA and the output of first RS flip-flop 513, respectively. The output of output circuit 514 is coupled to upper transistor turn-off control circuit 520 and lower transistor turn-off control circuit 530. Output circuit 514 is configured to enable the first step indicator signal PFM_FIR when both the soft-start control signal SS_ctl and the first enable signal EN1 are active. Output circuit 514 is also configured to disable the first step indicator signal PFM_FIR when at least one of the soft-start control signal SS_ctl and the first enable signal EN1 is inactive.

[0053] The upper transistor turn-off control circuit 520 includes a second RS flip-flop 521. The set terminal of the second RS flip-flop 521 is provided with a first-step indication signal PFM_FIR. An upper transistor turn-off signal CLOSE_H is output from the output terminal of the second RS flip-flop 521. Furthermore, the set and reset terminals of the second RS flip-flop 521 can be provided with an upper transistor control signal for controlling the normal switching of the upper transistor HS. When the first-step indication signal PFM_FIR is at an invalid level, the upper transistor control signal can control the second RS flip-flop 521 to normally generate the upper transistor turn-off signal CLOSE_H, thereby controlling the normal conduction and cutoff of the upper transistor HS.

[0054] The lower transistor turn-off control circuit 530 includes a delay circuit 531 and a third RS flip-flop 532. The delay circuit 531 is configured to delay the first step indication signal PFM_FIR to output a delayed first step indication signal PFM_FIR. The delay duration can be set according to specific applications, and the embodiments of this disclosure are not limited thereto. The set terminal of the third RS flip-flop 532 is provided with the delayed first step indication signal PFM_FIR. The lower transistor turn-off signal CLOSE_L is output from the output terminal of the third RS flip-flop 532. The delay circuit 531 is used to ensure the dead time of the DC-DC converter. Furthermore, the set and reset terminals of the third RS flip-flop 532 can be provided with a lower transistor control signal for controlling the normal switching of the lower transistor LS. When the first step indication signal PFM_FIR is at an invalid level, the lower transistor control signal can control the third RS flip-flop 532 to normally generate the lower transistor turn-off signal CLOSE_L, thereby controlling the normal conduction and cutoff of the lower transistor LS.

[0055] exist Figure 5 In the example, the initial levels of the upper MOSFET turn-off signal CLOSE_H and the lower MOSFET turn-off signal CLOSE_L are both invalid levels (e.g., low levels). At the start of soft-start, the ramp signal VRAMP gradually rises. When the ramp signal VRAMP is below the first reference voltage Vref1, the start detection signal SS_short is at the first level. The start detection signal SS_short at the first level sets the first RS flip-flop 513, thereby making the first enable signal EN1 active. When the ramp signal VRAMP rises to the first reference voltage Vref1, the start detection signal SS_short flips to the second level. Since the lower MOSFET turn-off signal CLOSE_L is initially invalid at this time, the first RS flip-flop 513 keeps the first enable signal EN1 unchanged from its previous state (i.e., the first enable signal EN1 remains active). When the feedback voltage FB rises to the ramp signal VRAMP, the soft-start control signal SS_ctl output by the error amplifier EA flips to an active level. At this point, both the soft-start control signal SS_ctl and the first enable signal EN1 are at active levels, therefore the first step indicator signal PFM_FIR toggles to active level. The active first step indicator signal PFM_FIR causes the upper MOSFET turn-off signal CLOSE_H to toggles to active level, and also causes the lower MOSFET turn-off signal CLOSE_L to toggles to active level after a delay. In this situation, both the upper and lower MOSFETs are turned off, causing the inductor current IL to discharge rapidly.

[0056] The CLOSE_L signal, which flips to an active level, resets the first RS flip-flop 513, causing the first enable signal EN1 to flip to an inactive level. At this time, the first step indicator signal PFM_FIR also flips to an inactive level. Since the ramp signal VRAMP will no longer drop below the first reference voltage Vref1, the start detection signal SS_short will no longer flip to the first level. Therefore, the first RS flip-flop 513 will not be set again to control the first enable signal EN1 to flip to an active level. Thus, the first step indicator signal PFM_FIR will remain inactive, no longer affecting the CLOSE_H and CLOSE_L signals, allowing the upper MOSFET HS and lower MOSFET LS to alternately turn on and off normally.

[0057] Figure 6 Show Figure 5 An exemplary circuit diagram of the logic circuit is shown. In logic circuit 600, the start-up control circuit 612 in the first step detection circuit 610 includes: a voltage comparator CMP and a first inverter NG1. The first input terminal of the voltage comparator CMP is provided with a ramp signal VRAMP. The second input terminal of the voltage comparator CMP is coupled to a first reference voltage terminal Vref1. The output terminal of the voltage comparator CMP is coupled to the input terminal of the first inverter NG1. The output terminal of the first inverter NG1 is coupled to the set terminal of the first RS flip-flop 613. Figure 6 In the example, the first input of the voltage comparator CMP is a non-inverting input, and the second input is an inverting input. When the ramp signal VRAMP is lower than the first reference voltage Vref1, the output signal SS_shortb of the voltage comparator CMP is low, and the start detection signal SS_short is high. When the ramp signal VRAMP rises to the first reference voltage Vref1, the output signal SS_shortb of the voltage comparator CMP flips to high, and the start detection signal SS_short flips to low.

[0058] exist Figure 6In an alternative embodiment of the example, the startup control circuit 612 may consist of only a voltage comparator CMP. The first input of the voltage comparator CMP is coupled to a first reference voltage Vref1. A ramp signal VRAMP is provided to the second input of the voltage comparator CMP. The output of the voltage comparator CMP is coupled to the set input of a first RS flip-flop 613. In this alternative embodiment, the first input of the voltage comparator CMP is a non-inverting input, and the second input is an inverting input. When the ramp signal VRAMP is below the first reference voltage Vref1, the startup detection signal SS_short output by the voltage comparator CMP is high. When the ramp signal VRAMP rises to the first reference voltage Vref1, the startup detection signal SS_short output by the voltage comparator CMP flips to low.

[0059] The ramp signal generation circuit 611 includes a first current source I1 and a first capacitor CSS. The first current source I1 is powered by a first voltage V1. The first current source I1 is coupled to a first terminal (pin SS) of the first capacitor CSS. The first current source I1 is configured to provide a first current I1 to the first terminal of the first capacitor CSS. A second terminal of the first capacitor CSS is coupled to a second voltage terminal V2. As charge from the first current I1 is stored in the first capacitor CSS, a ramp signal VRAMP is generated at the first terminal of the first capacitor CSS.

[0060] The output circuit 614 includes a second inverter NG2 and an AND gate. The input of the second inverter NG2 is coupled to the output of the error amplifier EA. The output of the second inverter NG2 is coupled to the first input of the AND gate. The second input of the AND gate is coupled to the output of the first RS flip-flop 613. A first step indicator signal PFM_FIR is output from the output of the AND gate.

[0061] exist Figure 6 In the example, the first RS flip-flop 613 includes a first NOR gate NOR1 and a second NOR gate NOR2. The first input of the first NOR gate NOR1 is provided with a start detection signal SS_short. The second input of the first NOR gate NOR1 is coupled to the output of the second NOR gate NOR2. The output of the first NOR gate NOR1 is coupled to the first input of the second NOR gate NOR2. The second input of the second NOR gate NOR2 is coupled to the output of the second RS flip-flop 621. The output of the second NOR gate NOR2 is the output of the first RS flip-flop 613.

[0062] exist Figure 6 In an alternative embodiment of the example, the second input of the second NOR2 gate in the first RS flip-flop 613 may also be coupled to the output of the third RS flip-flop 632.

[0063] The second RS flip-flop 621 in the upper transistor turn-off control circuit 620 includes a third NOR gate (NOR3) and a fourth NOR gate (NOR4). The first input of the third NOR gate (NOR3) is provided with a first-step indication signal (PFM_FIR). The second input of the third NOR gate (NOR3) is coupled to the output of the fourth NOR gate (NOR4). The output of the third NOR gate (NOR3) is coupled to the first input of the fourth NOR gate (NOR4). The output of the fourth NOR gate (NOR4) is the output of the second RS flip-flop 621.

[0064] The third RS flip-flop 632 in the lower transistor turn-off control circuit 630 includes a fifth NOR gate (NOR5) and a sixth NOR gate (NOR6). The first input of the fifth NOR gate (NOR5) is provided with a delayed first-step indication signal (PFM_FIR). The second input of the fifth NOR gate (NOR5) is coupled to the output of the sixth NOR gate (NOR6). The output of the fifth NOR gate (NOR5) is coupled to the first input of the sixth NOR gate (NOR6). The output of the sixth NOR gate (NOR6) is the output of the third RS flip-flop 632.

[0065] exist Figure 6 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. Those skilled in the art will understand that, based on the above inventive concept... Figure 6 Any modifications to the circuit shown should also fall within the scope of this disclosure.

[0066] exist Figure 6 In the example, the initial levels of the upper transistor turn-off signal CLOSE_H and the lower transistor turn-off signal CLOSE_L are both low. At the start of soft-start, the first current I1 begins charging the first capacitor CSS, and the ramp signal VRAMP gradually rises. When the ramp signal VRAMP is lower than the first reference voltage Vref1, the output signal SS_shortb of the voltage comparator CMP is low, and the start-up detection signal SS_short is high. The high-level start-up detection signal SS_short sets the first RS flip-flop 613, thereby making the first enable signal EN1 high. When the ramp signal VRAMP rises to the first reference voltage Vref1, the output signal SS_shortb of the voltage comparator CMP flips to high (allowing the upper transistor HS and the lower transistor LS to begin switching operations), and the start-up detection signal SS_short flips to low. Since the lower transistor turn-off signal CLOSE_L is initially low at this time, the first RS flip-flop 613 keeps the first enable signal EN1 unchanged from its previous state (i.e., the first enable signal EN1 remains high). refer to Figure 7When the feedback voltage FB rises to the ramp signal VRAMP (at time t3), the soft-start control signal SS_ctl output by the error amplifier EA flips to a low level. At this time, both the signal output by the second inverter NG2 and the first enable signal EN1 are at a high level, therefore the first step indicator signal PFM_FIR flips to a high level. The high level of the first step indicator signal PFM_FIR causes the upper transistor turn-off signal CLOSE_H to flip to a high level, and also causes the lower transistor turn-off signal CLOSE_L to flip to a high level after a delay. In this situation, both the upper and lower transistors are turned off, causing the inductor current IL to discharge rapidly.

[0067] The high-level CLOSE_L signal, which turns the lower transistor off, resets the first RS flip-flop 613, causing the first enable signal EN1 to flip low. At this time, the first step indicator signal PFM_FIR also flips low. Since the ramp signal VRAMP will no longer drop below the first reference voltage Vref1, the start detection signal SS_short will not flip high again. Therefore, the first RS flip-flop 613 will not be set again to control the first enable signal EN1 to flip high. Thus, the first step indicator signal PFM_FIR will remain low, no longer affecting the upper transistor off signal CLOSE_H and the lower transistor off signal CLOSE_L, allowing the upper transistor HS and the lower transistor LS to alternately turn on and off normally.

[0068] Embodiments of this disclosure also provide a DC-DC converter. The DC-DC converter includes logic circuitry according to embodiments of this disclosure.

[0069] Embodiments of this disclosure also provide a chip. This chip includes a DC-DC converter according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0070] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0071] In summary, the logic circuit according to the embodiments of this disclosure reduces the magnitude of the first step of the output voltage during the soft-start phase by controlling the full shutdown of both the upper and lower transistors when the feedback voltage first rises to the ramp voltage. Furthermore, this operation is performed only once and does not affect subsequent soft starts or normal operation after the soft start. The DC-DC converter according to the embodiments of this disclosure effectively avoids the accidental opening of the next stage circuit and excessive ripple during soft start under load, enabling more stable operation.

[0072] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0073] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0074] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A logic circuit for a DC-DC converter, comprising: The circuit includes a first-step detection circuit, an upper transistor turn-off control circuit, and a lower transistor turn-off control circuit. The first step detection circuit is configured to detect the first step of the output voltage of the DC-DC converter during the soft-start phase based on one of the upper MOSFET turn-off signal output by the upper MOSFET turn-off control circuit and the lower MOSFET turn-off signal output by the lower MOSFET turn-off control circuit, the feedback voltage of the DC-DC converter, and the first reference voltage from the first reference voltage terminal, so as to generate a first step indication signal. The upper transistor turn-off control circuit is configured to, when the first step indicator signal is at an active level, cause the upper transistor turn-off signal to be at an active level to indicate the turn-off of the upper transistor of the DC-DC converter. The lower transistor turn-off control circuit is configured to, when the first step indicator signal is at an active level, enable the lower transistor turn-off signal to be at an active level to indicate the turn-off of the lower transistor of the DC-DC converter. The first step detection circuit includes: a ramp signal generation circuit, a start control circuit, a first RS flip-flop, an error amplifier, and an output circuit. The ramp signal generating circuit is configured to generate a ramp signal. The startup control circuit is configured to generate a startup detection signal based on the ramp signal and the first reference voltage, wherein the startup detection signal is at a first level when the ramp signal is lower than the first reference voltage, and the startup detection signal flips to a second level when the ramp signal rises to the first reference voltage; The set terminal of the first RS flip-flop is provided with the start detection signal, and the reset terminal of the first RS flip-flop is provided with one of the lower transistor turn-off signal and the upper transistor turn-off signal. A first enable signal is output from the output terminal of the first RS flip-flop. The ramp signal is provided at the first input terminal of the error amplifier, the feedback voltage is provided at the second input terminal of the error amplifier, and a soft-start control signal is output from the output terminal of the error amplifier. The output circuit is configured to make the first step indicator signal active when both the soft-start control signal and the first enable signal are active.

2. The logic circuit according to claim 1, wherein, The startup control circuit includes: a voltage comparator and a first inverter. The voltage comparator has a first input terminal where the ramp signal is provided, a second input terminal where the voltage comparator is coupled to the first reference voltage terminal, and an output terminal where the voltage comparator is coupled to the input terminal of the first inverter. The output of the first inverter is coupled to the set terminal of the first RS flip-flop.

3. The logic circuit according to claim 1, wherein, The startup control circuit includes: a voltage comparator, The voltage comparator has a first input terminal coupled to the first reference voltage terminal, a second input terminal provided with the ramp signal, and an output terminal coupled to the set terminal of the first RS flip-flop.

4. The logic circuit according to claim 1, wherein, The ramp signal generation circuit includes: a first current source and a first capacitor. The first current source is configured to provide a first current to the first terminal of the first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal; The ramp signal is generated at the first end of the first capacitor.

5. The logic circuit according to claim 1, wherein, The output circuit includes: a second inverter and an AND gate. Wherein, the input terminal of the second inverter is coupled to the output terminal of the error amplifier, and the output terminal of the second inverter is coupled to the first input terminal of the AND gate; The second input terminal of the AND gate is coupled to the output terminal of the first RS flip-flop, and the first step indication signal is output from the output terminal of the AND gate.

6. The logic circuit according to any one of claims 1 to 5, wherein, The upper transistor turn-off control circuit includes: a second RS flip-flop. The set terminal of the second RS flip-flop is provided with the first step indication signal, and the upper tube turn-off signal is output from the output terminal of the second RS flip-flop.

7. The logic circuit according to any one of claims 1 to 5, wherein, The lower transistor turn-off control circuit includes: a delay circuit and a third RS flip-flop. The delay circuit is configured to delay the first step indication signal to output the delayed first step indication signal. The set terminal of the third RS flip-flop is provided with the delayed first step indication signal, and the lower transistor turn-off signal is output from the output terminal of the third RS flip-flop.

8. A logic circuit for a DC-DC converter, comprising: The circuit includes a first current source, a first capacitor, a voltage comparator, a first inverter, a second inverter, an AND gate, an error amplifier, a first RS flip-flop, a second RS flip-flop, a third RS flip-flop, and a delay circuit. The first current source is configured to provide a first current to the first terminal of the first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal; The first input terminal of the error amplifier is coupled to the first terminal of the first capacitor, the second input terminal of the error amplifier is coupled to the feedback voltage terminal of the DC-DC converter, and the output terminal of the error amplifier is coupled to the input terminal of the second inverter. The first input terminal of the voltage comparator is coupled to the first terminal of the first capacitor, the second input terminal of the voltage comparator is coupled to the first reference voltage terminal, and the output terminal of the voltage comparator is coupled to the input terminal of the first inverter. The output of the first inverter is coupled to the set terminal of the first RS flip-flop; The reset terminal of the first RS flip-flop is coupled to one of the output terminals of the second RS flip-flop and the third RS flip-flop; The output of the second inverter is coupled to the first input of the AND gate; The second input terminal of the AND gate is coupled to the output terminal of the first RS flip-flop, and the output terminal of the AND gate is coupled to the set terminal of the second RS flip-flop and the delay circuit; Output the upper transistor turn-off signal from the output terminal of the second RS flip-flop; The delay circuit is configured to delay the first step indication signal output from the AND gate to output a delayed first step indication signal; The set terminal of the third RS flip-flop is provided with the delayed first step indication signal, and the lower transistor turn-off signal is output from the output terminal of the third RS flip-flop. The effective level of the upper transistor turn-off signal is used to indicate the turn-off of the upper transistor of the DC-DC converter, and the effective level of the lower transistor turn-off signal is used to indicate the turn-off of the lower transistor of the DC-DC converter.

9. A DC-DC converter, comprising: The logic circuit according to any one of claims 1 to 8.

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