Pulse distribution method and device based on three-level inverter

Abstract

The application provides a pulse distribution method and device based on a three-level inverter. The pulse distribution method based on the three-level inverter comprises: generating complementary outer tube intermediate drive signals and inner tube intermediate drive signals according to pulse width modulation control signals from an inverter controller; generating an inner tube target drive signal according to the inner tube intermediate drive signals to control the inner tube; after a first preset time, generating an outer tube target drive signal according to the outer tube intermediate drive signals to control the outer tube; generating a pulse fault signal according to the on time of the outer tube intermediate drive signals or the inner tube intermediate drive signals; and outputting a fault feedback signal to the inverter controller according to the pulse fault signal and a fault signal from a switch tube. The application can reduce the number of hardwires, reduce material costs, improve the efficiency of production and installation and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to a pulse distribution method and apparatus based on a three-level inverter. Background Technology

[0002] With the continuous development of rail transit vehicle traction technology, NPC (Neutral Point Clamped) three-level topology inverters are receiving increasing attention. Compared to traditional two-level inverters, NPC three-level inverters have advantages such as low output harmonics, high efficiency, and low cost. However, the switching timing, pulse distribution, and control methods of IGBTs (Insulated Gate Bipolar Transistors) in NPC three-level inverters are more complex than those in two-level inverters, especially in terms of distributing more PWM (Pulse Width Modulation) pulses and controlling IGBT switching timing.

[0003] The pulse distribution device of the rail transit traction inverter is an intermediate device between the inverter controller (TCU) and the IGBT and driver. It is used to receive the PWM pulses from the preceding TCU, perform dead-time filtering, and then output the drive signal to the IGBT driver. Figure 1 This is a diagram of an existing NPC three-level inverter single-phase topology. (Example:) Figure 1 As shown, a typical pulse distribution device, driver, IGBT, and main circuit topology are assembled together to form an IGBT power module device. As can be seen from the figure, four PWM control signals are used to receive the TCU, and four additional PWM feedback signals are needed to inform the TCU of IGBT failures. These eight signals reach the TCU through chassis wiring, which is long and numerous, resulting in high material costs, low production efficiency, and difficulties in later maintenance.

[0004] In addition, three-level inverters require specific IGBT switching timings to protect the switching transistors from over-earth operation, such as turning on the inner transistor first during startup. Figure 1 The process involves turning on the inner IGBTs (T2 and T3) first, then the outer IGBTs (T1 and T4); during shutdown, the outer IGBTs (T1 and T4) are turned off first, followed by the inner IGBTs (T2 and T3). Current technology uses a host computer controller (TCU) to manage IGBT switching timing. However, the TCU is typically located far from the IGBT module, and its control wiring harness is often long and susceptible to interference. Therefore, it's impossible to guarantee a completely correct switching sequence on the IGBT module side. Furthermore, if the TCU malfunctions, the lack of redundancy can lead to incorrect switching timing, causing IGBT damage or even failure. Summary of the Invention

[0005] The main objective of this invention is to provide a pulse distribution method and apparatus based on a three-level inverter, so as to reduce the number of hardwires, reduce material costs, improve production and installation efficiency, and enhance the safety, redundancy, and reliability of the three-level inverter.

[0006] To achieve the above objectives, embodiments of the present invention provide a pulse distribution method based on a three-level inverter, comprising:

[0007] Complementary external tube intermediate drive signal and internal tube intermediate drive signal are generated based on the pulse width modulation control signal from the inverter controller;

[0008] Generate the target drive signal for the inner tube based on the intermediate drive signal of the inner tube to control the inner tube;

[0009] After the first preset time, the target drive signal for the outer tube is generated based on the intermediate drive signal of the outer tube to control the outer tube;

[0010] A pulse fault signal is generated based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0011] The fault feedback signal is output to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes an inner transistor and an outer transistor.

[0012] In one embodiment, it further includes:

[0013] A fault blocking signal for the switching transistor is generated based on the fault signal from the switching transistor.

[0014] The intermediate drive signals of the outer tube and the inner tube are turned off based on the fault blocking signal of the switching tube.

[0015] In one embodiment, it further includes:

[0016] The target drive signal of the outer tube is turned off based on the intermediate drive signal of the shut-off outer tube and the fault blocking signal of the switching tube.

[0017] After a second preset time, the inner tube target drive signal is turned off according to the shut-off outer tube target drive signal, the shut-off inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0018] In one embodiment, it further includes:

[0019] The intermediate drive signals of the outer tube and the inner tube are turned off according to the pulse width modulation blocking signal and the minimum conduction time.

[0020] The target drive signal of the outer tube is turned off according to the intermediate drive signal of the shut-off outer tube and the pulse width modulation blocking signal;

[0021] After a second preset time, the inner tube target drive signal is turned off according to the shut-off outer tube target drive signal, the shut-off inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0022] This invention also provides a pulse distribution device based on a three-level inverter, comprising:

[0023] The intermediate drive signal generation module is used to generate complementary external tube intermediate drive signals and internal tube intermediate drive signals based on the pulse width modulation control signal from the inverter controller.

[0024] The inner tube target drive signal module is used to generate an inner tube target drive signal based on the inner tube intermediate drive signal to control the inner tube.

[0025] The outer tube target drive signal module is used to generate an outer tube target drive signal based on the outer tube intermediate drive signal after a first preset time to control the outer tube;

[0026] The pulse fault signal module is used to generate a pulse fault signal based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0027] The fault feedback signal module is used to output a fault feedback signal to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes an inner transistor and an outer transistor.

[0028] In one embodiment, it further includes:

[0029] The switching transistor fault blocking signal module is used to generate a switching transistor fault blocking signal based on the fault signal from the switching transistor.

[0030] The first intermediate drive signal shutdown module is used to shut down the intermediate drive signals of the outer tube and the inner tube according to the switch tube fault blocking signal.

[0031] In one embodiment, it further includes:

[0032] The first outer tube target drive signal shutdown module is used to shut down the outer tube target drive signal according to the shut-down outer tube intermediate drive signal and the switch tube fault blockade signal;

[0033] The first inner tube target drive signal shutdown module is used to shut down the inner tube target drive signal after a second preset time, based on the shut-down outer tube target drive signal, the shut-down inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0034] In one embodiment, it further includes:

[0035] The second intermediate drive signal shutdown module is used to shut down the outer tube intermediate drive signal and the inner tube intermediate drive signal according to the pulse width modulation blocking signal and the minimum conduction time.

[0036] The second outer tube target drive signal shutdown module is used to shut down the outer tube target drive signal according to the shut-down outer tube intermediate drive signal and the pulse width modulation blocking signal.

[0037] The second inner tube target drive signal shutdown module is used to shut down the inner tube target drive signal after a second preset time, based on the shut-down outer tube target drive signal, the shut-down inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0038] This invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of the pulse distribution method based on a three-level inverter.

[0039] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the pulse distribution method based on a three-level inverter.

[0040] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the pulse distribution method based on a three-level inverter.

[0041] The pulse distribution method and apparatus based on a three-level inverter in this invention first generates complementary external tube intermediate drive signals and internal tube intermediate drive signals according to the pulse width modulation control signal, and then sequentially generates corresponding internal tube target drive signals and external tube target drive signals to control the switching transistors. Then, a pulse fault signal is generated according to the conduction time of the external tube intermediate drive signal or the internal tube intermediate drive signal, and a fault feedback signal is output to the inverter controller along with the fault signal from the switching transistor. This can reduce the number of hardwires, reduce material costs, improve the efficiency of production and installation and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a diagram of the existing single-phase topology of an NPC three-level inverter;

[0044] Figure 2 This is a single-phase topology diagram of the NPC three-level inverter in an embodiment of the present invention;

[0045] Figure 3 for Figure 2 Schematic diagram of the medium pulse distribution device;

[0046] Figure 4 This is a flowchart of a pulse distribution method based on a three-level inverter in an embodiment of the present invention;

[0047] Figure 5 This is a control flowchart of the drive signal generation module in an embodiment of the present invention;

[0048] Figure 6 This is a control flowchart of the switch timing management module in an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of the generation and control of the driving signal in the first embodiment of the present invention;

[0050] Figure 8 This is a schematic diagram of the generation and control of the driving signal in the second embodiment of the present invention;

[0051] Figure 9 This is a flowchart illustrating the process of shutting down the intermediate drive signal based on a switch failure blocking signal in an embodiment of the present invention.

[0052] Figure 10 This is a flowchart illustrating the process of turning off the intermediate drive signal based on the pulse width modulation blocking signal in an embodiment of the present invention;

[0053] Figure 11 This is a schematic diagram of the switching timing in an embodiment of the present invention;

[0054] Figure 12 This is a control flowchart of the fault detection module in an embodiment of the present invention;

[0055] Figure 13 This is a structural block diagram of a pulse distribution device based on a three-level inverter in an embodiment of the present invention;

[0056] Figure 14 This is a schematic block diagram illustrating the system configuration of an electronic device 9600 according to an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0059] To address the issues of numerous control harnesses in existing NPC three-level pulse distribution devices, lack of redundancy in the switching sequence of three-level inverters, and inability to correctly guarantee the switching sequence of IGBTs, this invention provides a pulse distribution method based on a three-level inverter. Figure 2 This is a single-phase topology diagram of the NPC three-level inverter in an embodiment of the present invention. (See diagram below.) Figure 2 As shown, only two PWM control signals are needed to receive the TCU signal. Additionally, a PWM lockout signal and a fault feedback signal are required. Therefore, only four signals are needed to complete the control. Figure 1 Compared to other methods, this invention reduces the number of hard wires by half, lowers material costs, and improves production and installation efficiency as well as ease of maintenance. The invention will now be described in detail with reference to the accompanying drawings.

[0060] Figure 3 for Figure 2 A schematic diagram of the pulse distribution device. (See diagram below.) Figure 3 As shown, the pulse distribution device is connected to the TCU via PWM control signal 1, PWM control signal 2, PWM lockout signal, and fault feedback signal on the left; and connected to drivers 1-4 via T1 drive signal-T4 drive signal and T1 fault signal-T4 fault signal on the right, respectively, to drive transistors T1-T4. The pulse distribution device internally includes three modules: a drive signal generation module, a switching timing management module, and a fault signal detection module.

[0061] The drive signal generation module generates four drive signals from PWM control signal 1 and PWM control signal 2 through an internal control method and sends them to the switch timing management module. It also generates a long pulse fault signal and sends it to the fault detection module. At the same time, it receives the blocking signal from the TCU and the IGBT fault blocking signal from the fault signal detection module to determine whether to start or stop the drive signal.

[0062] The switching timing management module is a crucial module for controlling the timing of three-level switches, ensuring correct turn-on and turn-off timing of the internal and external transistors at the IGBT module side. Located within the IGBT power module device and adjacent to the IGBT, this invention reduces the probability of interference compared to existing technologies where this function is only available in the TCU and requires a long control harness for TCU control. It promptly ensures correct switching timing control of the internal and external transistors when IGBT switching errors occur, adding a layer of protection and improving redundancy and reliability. Specifically, it receives four drive signals (T1-T4) generated by the drive generation module; receives PWM blocking signals and IGBT fault blocking signals; and manages the switching timing through internal control methods.

[0063] The fault signal detection module specifically receives the T1 fault signal, the T4 fault signal, and the long pulse fault signal to determine whether a fault has occurred. It then sends the fault information to the fault feedback signal in a serially encoded manner using an internal control method. Furthermore, only when the T1 fault signal and the T4 fault signal are determined to be faulty is an IGBT fault considered to have occurred, and an IGBT fault blocking signal is output to other modules.

[0064] Figure 4 This is a flowchart of a pulse distribution method based on a three-level inverter in an embodiment of the present invention. Figure 5 This is a control flowchart of the drive signal generation module in an embodiment of the present invention. Figure 6 This is a control flowchart of the switch timing management module in an embodiment of the present invention. Figures 4-6 As shown, the pulse distribution method based on a three-level inverter includes:

[0065] S101: Generates complementary external tube intermediate drive signal and internal tube intermediate drive signal based on the pulse width modulation control signal from the inverter controller.

[0066] Figure 7 This is a schematic diagram of the generation and control of the driving signal in the first embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the generation and control of the driving signal in the second embodiment of the present invention. Figures 7-8 As shown, counting begins when the PWM blocking signal falls. During this period, both drive signals T1 and T3 remain low. After the counting time is satisfied, the drive signal is enabled, and PWM control signal 1 generates two complementary drive signals T1 and T3. Drive signal T1 and PWM control signal 1 are in phase, while drive signal T3 and PWM control signal 1 are out of phase. There is also a dead time between drive signals T1 and T3 to ensure that transistors T1 and T3 do not turn on simultaneously. Furthermore, the turn-on and turn-off times of transistors T1 and T3 must satisfy the minimum turn-on and minimum turn-off times shown in the shaded area of ​​the diagram.

[0067] Figure 9 This is a flowchart illustrating the process of shutting down the intermediate drive signal based on a switching transistor fault blocking signal in an embodiment of the present invention. For example... Figure 9 As shown, the pulse distribution method based on a three-level inverter also includes:

[0068] S201: Generates a switch fault blocking signal based on the fault signal from the switch.

[0069] S202: Turn off the intermediate drive signal of the outer tube and the intermediate drive signal of the inner tube according to the fault blocking signal of the switching tube.

[0070] like Figure 8 As shown, the IGBT fault blocking signal is a fault indication signal for the IGBT transistor in the main circuit. In this case, it is crucial to prioritize preventing damage to the IGBT transistor. When the rising edge of the IGBT blocking signal (switching transistor fault blocking signal) generates a blocking signal, transistor T1 is immediately turned off to ensure the safety of the three-level main circuit.

[0071] Figure 10 This is a flowchart illustrating the process of shutting off intermediate drive signals based on pulse width modulation blocking signals in an embodiment of the present invention. For example... Figure 10 As shown, the pulse distribution method based on a three-level inverter also includes:

[0072] S301: Turn off the intermediate drive signal of the outer tube and the intermediate drive signal of the inner tube according to the pulse width modulation blocking signal and the minimum conduction time.

[0073] like Figure 7 As shown, when the rising edge of the PWM blocking signal (pulse width modulation blocking signal) generates a blocking signal, the T1 drive signal (intermediate drive signal of the external tube) will not be turned off immediately, but will be turned off after a delay after the minimum conduction time is met. This is because the PWM blocking signal is the shutdown indication signal when the TCU is normal. The number of start-stop operations is frequent, and the minimum pulse is required to ensure the life of the IGBT tube.

[0074] S302: The target drive signal of the outer tube is turned off according to the intermediate drive signal of the outer tube and the pulse width modulation blocking signal.

[0075] S303: After a second preset time, the inner tube target drive signal is turned off according to the turned-off outer tube target drive signal, the turned-off inner tube intermediate drive signal and the pulse width modulation blocking signal.

[0076] In practice, after detecting the intermediate drive signal to turn off, the outer tube T1 turns off first, and after a certain delay, the inner tube T2 turns off.

[0077] S102: Generate the target drive signal for the inner tube based on the intermediate drive signal of the inner tube to control the inner tube.

[0078] S103: After a first preset time, generate an outer tube target drive signal based on the outer tube intermediate drive signal to control the outer tube.

[0079] Figure 11 This is a schematic diagram of the switching timing in an embodiment of the present invention. For example... Figure 11 As shown, when the falling edge of the PWM blocking signal is detected, the drive signal needs to be enabled. Therefore, the inner transistor T2 is turned on first, and the outer transistor T1 is turned on after a certain delay.

[0080] In one embodiment, the pulse distribution method based on a three-level inverter further includes:

[0081] The target drive signal of the outer tube is turned off based on the intermediate drive signal of the shut-off outer tube and the fault blocking signal of the switching tube.

[0082] After a second preset time, the inner tube target drive signal is turned off according to the shut-off outer tube target drive signal, the shut-off inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0083] like Figure 11 As shown, after detecting the rising edge of the PWM blocking signal, the drive signal needs to be disabled. The outer transistor T1 is turned off first, and after a certain delay, the inner transistor T2 is turned off.

[0084] S104: Generates a pulse fault signal based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0085] like Figures 7-8 As shown, when any drive signal is on for too long (the longer shaded area in the figure), the drive signal generation module will generate a long pulse fault signal.

[0086] S105: Outputs a fault feedback signal to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor.

[0087] The switching transistors include two inner transistors (T2, T3) located on the inside and two outer transistors (T1, T4) located on the outside.

[0088] Figure 12 This is a control flowchart of the fault detection module in an embodiment of the present invention. Figure 12 As shown, when any one of the long pulse fault signal or the fault signals T1-T4 from the switching transistor is at a high level, a fault is considered to have occurred. The IGBT fault bit, long pulse fault bit, and CRC check bit are sent to the inverter controller via a fault feedback signal through a serial port.

[0089] Figure 4 The pulse distribution method based on a three-level inverter, as shown, can be implemented by a pulse distribution device. Figure 4As shown in the process, the pulse distribution method based on a three-level inverter in this embodiment of the invention first generates complementary external tube intermediate drive signals and internal tube intermediate drive signals according to the pulse width modulation control signal, and then sequentially generates corresponding internal tube target drive signals and external tube target drive signals to control the switching tubes. Then, a pulse fault signal is generated according to the conduction time of the external tube intermediate drive signal or the internal tube intermediate drive signal, and a fault feedback signal is output to the inverter controller along with the fault signal from the switching tube. This can reduce the number of hardwires, reduce material costs, improve the efficiency of production and installation and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter.

[0090] Based on the same inventive concept, this embodiment of the invention also provides a pulse distribution device based on a three-level inverter. Since the principle of this device in solving the problem is similar to that of the pulse distribution method based on a three-level inverter, the implementation of this device can refer to the implementation of the method, and the repeated parts will not be described again.

[0091] Figure 13 This is a structural block diagram of a pulse distribution device based on a three-level inverter in an embodiment of the present invention. Figure 13 As shown, the pulse distribution device based on the three-level inverter includes:

[0092] The intermediate drive signal generation module is used to generate complementary external tube intermediate drive signals and internal tube intermediate drive signals based on the pulse width modulation control signal from the inverter controller.

[0093] The inner tube target drive signal module is used to generate an inner tube target drive signal based on the inner tube intermediate drive signal to control the inner tube.

[0094] The outer tube target drive signal module is used to generate an outer tube target drive signal based on the outer tube intermediate drive signal after a first preset time to control the outer tube;

[0095] The pulse fault signal module is used to generate a pulse fault signal based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0096] The fault feedback signal module is used to output a fault feedback signal to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes an inner transistor and an outer transistor.

[0097] In one embodiment, it further includes:

[0098] The switching transistor fault blocking signal module is used to generate a switching transistor fault blocking signal based on the fault signal from the switching transistor.

[0099] The first intermediate drive signal shutdown module is used to shut down the intermediate drive signals of the outer tube and the inner tube according to the switch tube fault blocking signal.

[0100] In one embodiment, it further includes:

[0101] The first outer tube target drive signal shutdown module is used to shut down the outer tube target drive signal according to the shut-down outer tube intermediate drive signal and the switch tube fault blockade signal;

[0102] The first inner tube target drive signal shutdown module is used to shut down the inner tube target drive signal after a second preset time, based on the shut-down outer tube target drive signal, the shut-down inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0103] In one embodiment, it further includes:

[0104] The second intermediate drive signal shutdown module is used to shut down the outer tube intermediate drive signal and the inner tube intermediate drive signal according to the pulse width modulation blocking signal and the minimum conduction time.

[0105] The second outer tube target drive signal shutdown module is used to shut down the outer tube target drive signal according to the shut-down outer tube intermediate drive signal and the pulse width modulation blocking signal.

[0106] The second inner tube target drive signal shutdown module is used to shut down the inner tube target drive signal after a second preset time, based on the shut-down outer tube target drive signal, the shut-down inner tube intermediate drive signal, and the pulse width modulation blocking signal.

[0107] In practical applications, the pulse distribution device based on the three-level inverter is used in pulse distribution devices, and its position in the single-phase topology of the NPC three-level inverter is as follows: Figure 2 As shown, the left side is connected to the TCU via PWM control signal 1, PWM control signal 2, PWM lockout signal, and fault feedback signal. The right side controls the T1 IGBT by connecting to driver 1 via the T1 drive signal and T1 fault signal; controls the T2 IGBT by connecting to driver 2 via the T2 drive signal and T2 fault signal; controls the T3 IGBT by connecting to driver 3 via the T3 drive signal and T3 fault signal; and controls the T4 IGBT by connecting to driver 4 via the T4 drive signal and T4 fault signal. The T1 to T4 IGBT switching connections are as follows: Figure 2 The diagram shows the single-phase topology of an NPC three-level inverter. In the NPC three-level circuit, transistors T1 and T4 are called external transistors, and transistors T2 and T3 are called internal transistors.

[0108] like Figure 3 As shown, the pulse distribution device includes three modules: a drive signal generation module, a switch timing management module, and a fault signal detection module.

[0109] The drive signal generation module includes an intermediate drive signal generation module, a pulse fault signal module, a first intermediate drive signal shutdown module, and a second intermediate drive signal shutdown module. It is used to generate four drive signals T1-T4 from PWM control signal 1 and PWM control signal 2 through an internal control method and send them to the switch timing management module. It also generates a long pulse fault signal and sends it to the fault detection module. At the same time, it receives the blocking signal from the TCU and the IGBT fault blocking signal from the fault signal detection module to determine whether to start or stop the drive signal.

[0110] The switching timing management module controls the timing of the three-level switch. It includes an inner tube target drive signal module, an outer tube target drive signal module, a first outer tube target drive signal turn-off module, a first inner tube target drive signal turn-off module, a second outer tube target drive signal turn-off module, and a second inner tube target drive signal turn-off module. It can ensure the correct timing of the inner and outer tubes turning on and off at the IGBT module side. It receives four drive signals T1-T4 generated by the drive signal generation block. It is used to receive PWM blocking signals and IGBT fault blocking signals. After completing the control and adjustment of the switching timing through internal control methods, it generates the processed T1 drive signal-T4 drive signal.

[0111] The fault signal detection module includes a fault feedback signal module and a switching transistor fault blocking signal module. It is used to receive T1 fault signal-T4 fault signal and long pulse fault signal to determine whether the module has failed. The fault information is sent to the fault feedback signal in a serial encoding manner through an internal control method.

[0112] The three modules and control methods inside the pulse distribution device can be implemented using an FPGA or CPLD. Switches T1-T4 are IGBTs, used to form an NPC three-level circuit structure. Drivers 1-4 are IGBT drivers, a type of driver board that needs to be used with IGBTs. The control signals generated by the TCU need to be converted into drive signals used by the drivers before they can further drive the IGBTs.

[0113] In summary, the pulse distribution device based on a three-level inverter in this embodiment of the invention first generates complementary external tube intermediate drive signals and internal tube intermediate drive signals according to the pulse width modulation control signal, and then sequentially generates corresponding internal tube target drive signals and external tube target drive signals to control the switching tubes. Then, it generates a pulse fault signal according to the conduction time of the external tube intermediate drive signal or the internal tube intermediate drive signal, and outputs a fault feedback signal to the inverter controller along with the fault signal from the switching tube. This can reduce the number of hardwires, reduce material costs, improve production and installation efficiency and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter.

[0114] Figure 14This is a schematic block diagram illustrating the system configuration of the electronic device 9600 according to an embodiment of this application. Figure 14 As shown, the electronic device 9600 may include a central processing unit 9100 and a memory 9140; the memory 9140 is coupled to the central processing unit 9100. It is worth noting that... Figure 14 This is an example; other types of structures can also be used to supplement or replace this structure to achieve telecommunications functions or other functions.

[0115] In one embodiment, the pulse distribution method function based on the three-level inverter can be integrated into the central processing unit 9100. The central processing unit 9100 can be configured to perform the following control:

[0116] Complementary external tube intermediate drive signal and internal tube intermediate drive signal are generated based on the pulse width modulation control signal from the inverter controller;

[0117] Generate the target drive signal for the inner tube based on the intermediate drive signal of the inner tube to control the inner tube;

[0118] After the first preset time, the target drive signal for the outer tube is generated based on the intermediate drive signal of the outer tube to control the outer tube;

[0119] A pulse fault signal is generated based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0120] The fault feedback signal is output to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes an inner transistor and an outer transistor.

[0121] As described above, the pulse distribution method for three-level inverters provided in this application first generates complementary external tube intermediate drive signals and internal tube intermediate drive signals according to the pulse width modulation control signal, and then sequentially generates corresponding internal tube target drive signals and external tube target drive signals to control the switching tubes. Then, a pulse fault signal is generated according to the conduction time of the external tube intermediate drive signal or the internal tube intermediate drive signal, and a fault feedback signal is output to the inverter controller along with the fault signal from the switching tube. This can reduce the number of hardwires, reduce material costs, improve the efficiency of production and installation and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter.

[0122] In another embodiment, the pulse distribution device based on the three-level inverter can be configured separately from the central processing unit 9100. For example, the pulse distribution device based on the three-level inverter can be configured as a chip connected to the central processing unit 9100, and the function of the pulse distribution method based on the three-level inverter can be realized through the control of the central processing unit.

[0123] like Figure 14As shown, the electronic device 9600 may further include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily need to include these components. Figure 14 All components shown; in addition, the electronic device 9600 may also include Figure 14 For components not shown, please refer to existing technologies.

[0124] like Figure 14 As shown, the central processing unit 9100, sometimes also referred to as a controller or operating control, may include a microprocessor or other processor device and / or logic device, which receives inputs and controls the operation of various components of the electronic device 9600.

[0125] The memory 9140 may be, for example, one or more of a cache, flash memory, hard drive, removable media, volatile memory, non-volatile memory, or other suitable devices. It may store the aforementioned failure-related information, and also store a program for executing that information. The central processing unit 9100 may execute the program stored in the memory 9140 to perform information storage or processing, etc.

[0126] Input unit 9120 provides input to central processing unit 9100. Input unit 9120 may be, for example, a keypad or touch input device. Power supply 9170 provides power to electronic device 9600. Display 9160 displays images and text. Display may be, for example, an LCD display, but is not limited thereto.

[0127] The memory 9140 can be a solid-state memory, such as a read-only memory (ROM), random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and contains more data; examples of this type of memory are sometimes referred to as EPROMs. The memory 9140 can also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142 for storing application programs and function programs or processes for executing the operation of the electronic device 9600 via the central processing unit 9100.

[0128] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for the electronic device's communication functions and / or for performing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0129] The communication module 9110 is a transmitter / receiver 9110 that transmits and receives signals via the antenna 9111. The communication module (transmitter / receiver) 9110 is coupled to the central processing unit 9100 to provide input signals and receive output signals, which can be the same as in a conventional mobile communication terminal.

[0130] Based on different communication technologies, multiple communication modules 9110 can be configured in the same electronic device, such as cellular network modules, Bluetooth modules, and / or wireless LAN modules. The communication module (transmitter / receiver) 9110 is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide audio output via the speaker 9131 and receive audio input from the microphone 9132, thereby realizing typical telecommunications functions. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. Additionally, the audio processor 9130 is coupled to a central processing unit 9100, enabling on-device recording via the microphone 9132 and on-device playback of stored sound via the speaker 9131.

[0131] This invention also provides a computer-readable storage medium capable of implementing all steps of the pulse distribution method based on a three-level inverter, where the execution subject is a server or client, as described in the above embodiments. The computer-readable storage medium stores a computer program that, when executed by a processor, implements all steps of the pulse distribution method based on a three-level inverter as described in the above embodiments. For example, when the processor executes the computer program, it implements the following steps:

[0132] Complementary external tube intermediate drive signal and internal tube intermediate drive signal are generated based on the pulse width modulation control signal from the inverter controller;

[0133] Generate the target drive signal for the inner tube based on the intermediate drive signal of the inner tube to control the inner tube;

[0134] After the first preset time, the target drive signal for the outer tube is generated based on the intermediate drive signal of the outer tube to control the outer tube;

[0135] A pulse fault signal is generated based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0136] The fault feedback signal is output to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes an inner transistor and an outer transistor.

[0137] In summary, the computer-readable storage medium of this invention first generates complementary external tube intermediate drive signals and internal tube intermediate drive signals according to the pulse width modulation control signal, and then sequentially generates corresponding internal tube target drive signals and external tube target drive signals to control the switching transistors. Then, it generates a pulse fault signal according to the conduction time of the external tube intermediate drive signal or the internal tube intermediate drive signal, and outputs a fault feedback signal to the inverter controller along with the fault signal from the switching transistor. This can reduce the number of hardwires, reduce material costs, improve production and installation efficiency and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter.

[0138] This invention also provides a computer program product capable of implementing all steps of the pulse distribution method based on a three-level inverter, where the execution subject is a server or client, as described in the above embodiments. The computer program product includes a computer program / instruction that, when executed by a processor, implements all steps of the pulse distribution method based on a three-level inverter as described in the above embodiments. For example, when the processor executes the computer program, it implements the following steps:

[0139] Complementary external tube intermediate drive signal and internal tube intermediate drive signal are generated based on the pulse width modulation control signal from the inverter controller;

[0140] Generate the target drive signal for the inner tube based on the intermediate drive signal of the inner tube to control the inner tube;

[0141] After the first preset time, the target drive signal for the outer tube is generated based on the intermediate drive signal of the outer tube to control the outer tube;

[0142] A pulse fault signal is generated based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube.

[0143] The fault feedback signal is output to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes an inner transistor and an outer transistor.

[0144] In summary, the computer program product of this invention first generates complementary external tube intermediate drive signals and internal tube intermediate drive signals according to the pulse width modulation control signal, and then sequentially generates corresponding internal tube target drive signals and external tube target drive signals to control the switching tubes. Then, it generates a pulse fault signal according to the conduction time of the external tube intermediate drive signal or the internal tube intermediate drive signal, and outputs a fault feedback signal to the inverter controller along with the fault signal from the switching tube. This can reduce the number of hardwires, reduce material costs, improve production and installation efficiency and the convenience of later maintenance, and improve the safety, redundancy and reliability of the three-level inverter.

[0145] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, hardware + program embodiments are relatively simple in description because they are fundamentally similar to method embodiments; relevant parts can be referred to the descriptions in the method embodiments.

[0146] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0147] While this application provides the method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual device or client product execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0148] While this specification provides method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive means. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual device or end product execution, the methods shown in the embodiments or drawings may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed data processing environment). The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, product, or apparatus. Without further limitations, the presence of other identical or equivalent elements in the process, method, product, or apparatus that includes said elements is not excluded.

[0149] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing the embodiments of this specification, the functions of each module can be implemented in one or more software and / or hardware components, or a module that performs the same function can be implemented by a combination of multiple sub-modules or sub-units. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0150] Those skilled in the art will also know that, besides implementing the controller using purely computer-readable program code, the same functions can be achieved by logically programming the method steps, making the controller function as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers (PLCs), and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the devices within it used to implement various functions can also be considered structures within that hardware component. Alternatively, the devices used to implement various functions can be considered as both software modules implementing the method and structures within a hardware component.

[0151] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0152] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0153] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0154] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0155] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0156] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0157] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments of this specification can take the form of computer program products implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0158] The embodiments described in this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0159] The embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0160] The above description is merely an embodiment of the present specification and is not intended to limit the embodiments of the present specification. For those skilled in the art, various modifications and variations can be made to the embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of the present specification should be included within the scope of the claims of the embodiments of the present specification.

Claims

1. A pulse distribution method based on a three-level inverter, characterized in that, include: Complementary external tube intermediate drive signal and internal tube intermediate drive signal are generated based on the pulse width modulation control signal from the inverter controller. Generate the target drive signal for the inner tube based on the intermediate drive signal of the inner tube to control the inner tube; After the first preset time, the target drive signal for the outer tube is generated based on the intermediate drive signal of the outer tube to control the outer tube; A pulse fault signal is generated based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube. A fault feedback signal is output to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes the inner transistor and the outer transistor.

2. The pulse distribution method based on a three-level inverter according to claim 1, characterized in that, Also includes: A fault blocking signal for the switching transistor is generated based on the fault signal from the switching transistor. The intermediate drive signals of the outer tube and the inner tube are turned off according to the fault blocking signal of the switching tube.

3. The pulse distribution method based on a three-level inverter according to claim 2, characterized in that, Also includes: The target drive signal of the outer tube is turned off according to the intermediate drive signal of the shut-off outer tube and the fault blockade signal of the switch tube. After a second preset time, the inner tube target drive signal is turned off according to the shut-off outer tube target drive signal, the shut-off inner tube intermediate drive signal, and the pulse width modulation blocking signal.

4. The pulse distribution method based on a three-level inverter according to claim 2, characterized in that, Also includes: The intermediate drive signals of the outer tube and the inner tube are turned off according to the pulse width modulation blocking signal and the minimum conduction time. The target drive signal of the outer tube is turned off according to the intermediate drive signal of the shut-off outer tube and the pulse width modulation blocking signal; After a second preset time, the inner tube target drive signal is turned off according to the shut-off outer tube target drive signal, the shut-off inner tube intermediate drive signal, and the pulse width modulation blocking signal.

5. A pulse distribution device based on a three-level inverter, characterized in that, include: The intermediate drive signal generation module is used to generate complementary external tube intermediate drive signals and internal tube intermediate drive signals based on the pulse width modulation control signal from the inverter controller. The inner tube target drive signal module is used to generate an inner tube target drive signal based on the inner tube intermediate drive signal to control the inner tube. The outer tube target drive signal module is used to generate an outer tube target drive signal based on the outer tube intermediate drive signal after a first preset time to control the outer tube; The pulse fault signal module is used to generate a pulse fault signal based on the conduction time of the intermediate drive signal of the outer tube or the intermediate drive signal of the inner tube. The fault feedback signal module is used to output a fault feedback signal to the inverter controller based on the pulse fault signal and the fault signal from the switching transistor; wherein the switching transistor includes the inner transistor and the outer transistor.

6. The pulse distribution device based on a three-level inverter according to claim 5, characterized in that, Also includes: The switching transistor fault blocking signal module is used to generate a switching transistor fault blocking signal based on the fault signal from the switching transistor. The first intermediate drive signal shutdown module is used to shut down the intermediate drive signal of the outer tube and the intermediate drive signal of the inner tube according to the switch tube fault blocking signal.

7. The pulse distribution device based on a three-level inverter according to claim 6, characterized in that, Also includes: The first outer tube target drive signal shutdown module is used to shut down the outer tube target drive signal according to the shut-down outer tube intermediate drive signal and the switch tube fault blockade signal. The first inner tube target drive signal shutdown module is used to shut down the inner tube target drive signal after a second preset time, based on the shut-down outer tube target drive signal, the shut-down inner tube intermediate drive signal, and the pulse width modulation blocking signal.

8. The pulse distribution device based on a three-level inverter according to claim 6, characterized in that, Also includes: The second intermediate drive signal shutdown module is used to shut down the outer tube intermediate drive signal and the inner tube intermediate drive signal according to the pulse width modulation blocking signal and the minimum conduction time. The second outer tube target drive signal shutdown module is used to shut down the outer tube target drive signal according to the shut-down outer tube intermediate drive signal and the pulse width modulation blocking signal. The second inner tube target drive signal shutdown module is used to shut down the inner tube target drive signal after a second preset time, based on the shut-down outer tube target drive signal, the shut-down inner tube intermediate drive signal, and the pulse width modulation blocking signal.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the pulse distribution method based on a three-level inverter as described in any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the pulse distribution method based on a three-level inverter as described in any one of claims 1 to 4.

11. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the pulse distribution method based on a three-level inverter as described in any one of claims 1 to 4.

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