Low-power crystal oscillator drive circuit with self-check function

Abstract

The present application discloses a low-power crystal oscillator driving circuit with a self-checking function, which relates to the field of circuits. The crystal oscillator circuit includes a variable gain driving module, a shaping module, and a frequency self-checking module. The OSCI and OSCO terminals of the variable gain driving module are connected in parallel with the crystal oscillator module, and are used to control the oscillation of the crystal oscillator module and adjust the driving gain according to the gain feedback signal of the frequency self-checking module. The shaping module is connected in parallel between the OSCI and OSCO terminals and is used to convert the OSCI and OSCO signals into square wave signals. The frequency self-checking module is connected to the output terminal of the shaping module and is used to detect the frequency of the square wave signal, output the status signal of the crystal oscillator according to the measured frequency, and update the gain feedback signal. This solution can detect the working frequency of the crystal oscillator in real time and generate a gain feedback signal in a timely manner according to the detected frequency to change the driving current of the crystal oscillator, which can not only shorten the startup time of the crystal oscillator, but also reduce the gain after the crystal oscillator is stable, thereby reducing the system loss.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of oscillators, and particularly to a low-power crystal oscillator driving circuit with a self-checking function. Background Art

[0002] A quartz crystal resonator, abbreviated as a crystal oscillator, is a piezoelectric device that can convert mechanical energy and electrical energy into each other, and the energy conversion occurs at the resonance frequency point. A crystal oscillator belongs to a passive device, and it needs to cooperate with a crystal oscillator driving circuit inside the circuit to generate oscillation. The crystal oscillator has extremely high frequency stability and is widely used in the field of electronic communication.

[0003] In the related art, the crystal oscillator circuit adopts a classic Pierce oscillator structure, and a feedback resistor is connected in parallel with an inverter inside, so that the inverter is in the linear region and used as an amplifier. However, the gain of the inverter will affect the start-up time of the oscillation. The larger the gain, the shorter the start-up time. Therefore, in order to obtain a shorter start-up time of the crystal oscillator, the power consumption has to be increased. Since the crystal oscillator circuit needs to cooperate with an external crystal oscillator and an internal driving circuit, and is not entirely integrated inside the circuit, there will be some unstable factors when the circuit is working normally. For example, the crystal oscillator is desoldered due to the circuit being impacted, or the contact is poor during operation due to the solder joint being insecure. The related art cannot monitor the working condition of the crystal oscillator in real time and cannot ensure the stable operation of the circuit. Summary of the Invention

[0004] The embodiments of the present application provide a low-power crystal oscillator driving circuit with a self-checking function to solve the problems of long start-up time, large power consumption, and instability of the crystal oscillator. The crystal oscillator driving circuit is connected to an external crystal oscillator circuit through two multiplexing ports; the crystal oscillator driving circuit includes a variable gain driving module, a shaping module, and a frequency self-checking module;

[0005] The oscillation input OSCI terminal and the oscillation output OSCO terminal of the variable gain driving module are connected in parallel with the crystal oscillator module, and are used to control the oscillation of the crystal oscillator module and adjust the driving gain according to the gain feedback signal of the frequency self-checking module;

[0006] The shaping module is connected in parallel between the OSCI terminal and the OSCO terminal, and is used to convert the OSCI signal and the OSCO signal of the variable gain driving module from sine wave signals into square wave signals for output;

[0007] The frequency self-checking module is connected to the output terminal of the shaping module, and is used to detect the frequency of the square wave signal output by the shaping module, output the status signal of the crystal oscillator according to the comparison between the measured frequency and the preset frequency, and update the gain feedback signal.

[0008] Specifically, the variable gain driving module includes an amplifier module and a feedback resistor connected in parallel at the input and output ends; the amplifier module is used to provide starting oscillation energy to the crystal oscillator circuit, and a feedback channel is formed between the feedback resistor and the crystal oscillator module to determine the oscillation frequency.

[0009] Specifically, the amplifier module is a common-source amplifier with a current source as the load, including at least two current sources and an NMOS transistor N0;

[0010] The outputs of at least two current sources are commonly connected to the source electrode of N0, and the OSCO terminal of the amplifier module is led out from the source electrode; a controllable switch is provided on the first current source I1 in the current sources, and is commonly connected to the source electrode of the NMOS transistor through the controllable switch and the second current source I2;

[0011] The controllable switch is connected to the frequency self-checking module, and is controlled to be turned off or on according to the received gain feedback signal. The gate input terminal of N0 is led out as the OSCI terminal of the amplifier module.

[0012] Specifically, the shaping module includes a signal comparator, a first Schmitt trigger, and a first inverter; the output of the signal comparator is cascaded with the first Schmitt trigger, and the first inverter is cascaded at the output end of the first Schmitt trigger and outputs a converted square wave signal;

[0013] The signal comparator is a cascode current mirror structure, including PMOS transistors P1 and P2 connected in common gate, NMOS transistors N1 and N2 connected in common source, and the gate of P1 is connected to the drain of N1, and the source of P2 is connected to the drain of N2, and outputs a converted level signal;

[0014] The common-source output of the NMOS transistor is grounded through a third current source I3; the gate of N1 is connected to the OSCI signal, and the gate of N2 is connected to the OSCO signal.

[0015] Specifically, when the voltage of the OSCI signal is greater than the voltage of the OSCO signal, N2 is turned off, and the output converted level signal is a high-level signal; when the voltage of the OSCI signal is less than the voltage of the OSCO signal, N1, P1, and P2 are turned off, and the output converted level signal is a low-level signal.

[0016] Specifically, the first Schmitt trigger and the first inverter process and shape based on the input converted level signal and output a converted square wave signal; wherein, when the converted level signal is a high-level signal, the square wave signal is a high level; when the converted level signal is a low-level signal, the square wave signal is a low level.

[0017] Specifically, when the frequency of the square wave signal input to the frequency self-checking module is greater than the set frequency, an abnormal crystal oscillator status signal is output; when the frequency of the square wave signal is less than the set frequency, a normal crystal oscillator status signal is output.

[0018] When the frequency self-checking module outputs a normal crystal oscillator status signal, a first gain feedback signal for reducing the driving gain is generated and fed back to the variable gain driving module; when the frequency self-checking module outputs an abnormal crystal oscillator status signal, a second gain feedback signal for increasing the gain is generated and fed back to the variable gain driving module.

[0019] Specifically, the frequency self-checking module includes a first detection branch, a second detection branch, and a status detection branch connected in parallel.

[0020] The first detection branch includes an NMOS transistor N2 and a PMOS transistor P2 connected in cascode, with the square wave signal input to the common gate and the output of the common source connected to a second Schmitt trigger, and the output of the second Schmitt trigger connected to a second inverter; the drain of P2 is connected to the input power supply VDD, and the drain of N2 is grounded through a fourth current source I4.

[0021] The second detection branch includes an NMOS transistor N3 and a PMOS transistor P3 connected in cascode, with the square wave signal input to the common gate and the output of the common source connected to a third Schmitt trigger, and the output of the third Schmitt trigger connected to a third inverter; the drain of P3 is connected to the input power supply VDD and a cascaded fifth current source I5, and the drain of N3 is grounded.

[0022] Specifically, the outputs of the second inverter and the third inverter are connected to the status detection branch.

[0023] Specifically, the status detection branch includes a NAND gate, a fourth inverter, and a first AND gate cascaded in sequence; the outputs of the second inverter and the third inverter are connected to the inputs of the first NAND gate, and the first NAND gate outputs the status signal of the crystal oscillator; the inputs of the first AND gate are respectively connected to the output of the fourth inverter and the square wave signal output of the shaping module.

[0024] The beneficial effects brought by the technical solution provided by the embodiment of the present application at least include: when it is detected that the crystal oscillator frequency is too low, the driving ability of the variable gain driving module is increased, a larger driving current is used to start the crystal oscillator, and the start-up time is shortened.

[0025] When it is detected that the frequency is normal, the driving ability of the variable gain driving module is reduced to ensure the normal oscillation of the crystal oscillator and reduce the power consumption of the entire system.

[0026] When the currently detected crystal oscillator frequency is greater than the preset value, the crystal oscillator works normally. When the currently detected crystal oscillator frequency is less than the preset value, the crystal oscillator frequency error status signal ERROR is output and the output of CLKOUT is stopped to prevent the wrong waveform from causing disorder in the subsequent digital circuit.

[0027] By detecting the ERROR signal, it is determined whether the clock source can be switched to the crystal oscillator, or whether to switch from the crystal oscillator to other clock sources, thereby improving the stability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the classic Pierce oscillator structure

[0029] Figure 2 A low-power crystal oscillator drive circuit with a self-test function provided in an embodiment of the present application;

[0030] Figure 3 is a schematic structural diagram of a variable gain driving module provided in an embodiment of the present application;

[0031] Figure 4 It is a structural diagram of the amplifier module provided by this application;

[0032] Figure 5 This is a schematic diagram of the structure of the shaping module provided in an embodiment of the present application;

[0033] Figure 6 is the relationship curve between OSCI-OSCO and output CK1;

[0034] Figure 7 It is the waveform diagram of the CK1 signal obtained based on the sampled OSCI and OSCO signals;

[0035] Figure 8 Schematic diagram of the structure of the frequency self-test module provided in the embodiment of the present application;

[0036] Figure 9 This is a schematic diagram of the structure after the state detection branch is added to the TFF trigger;

[0037] Figure 10 This is a timing diagram of each point recorded using a low-power crystal oscillator drive circuit with a self-test function. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0039] As used herein, "a plurality of" means two or more. "And / or" describes the relationship between associated objects and indicates that there can be three relationships. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates an "or" relationship between the associated objects before and after.

[0040] As Figure 1 shown, it is a classic Pierce oscillator structure. Inside the driving circuit part, a feedback resistor RF is connected in parallel with an inverter INV, making the inverter operate in the linear region and used as an amplifier. However, the gain of the inverter will affect the start-up time of the crystal oscillator module (the gain is inversely proportional to the crystal oscillator start-up time), and setting a larger gain must be achieved at the cost of sacrificing system power consumption to achieve fast start-up. Moreover, since the crystal oscillator circuit requires cooperation between an external crystal oscillator and an internal driving circuit and is not fully integrated inside the circuit, there will be some unstable factors when the circuit is working normally. For example, the crystal oscillator may be desoldered due to the circuit being impacted, or the contact may be poor during operation due to the solder joints being loose. The related technology cannot monitor the working condition of the crystal oscillator in real time.

[0041] To address the above problems, referring to Figure 2 , it is a low-power crystal oscillator driving circuit with a self-check function provided by this application. The crystal oscillator driving circuit is connected to an external crystal oscillator circuit through two multiplexed ports (Port 1 and Port 2). C L1 and C L2 are external load capacitors. They are connected to both ends of the crystal oscillator module and then connected to the driving circuit together with the crystal oscillator module through Port 1 and Port 2. The built-in crystal oscillator driving circuit includes a variable-gain driving module, a shaping module, and a frequency self-check module. The OSCI terminal and the OSCO terminal of the variable-gain driving module are connected in parallel with the crystal oscillator module through the multiplexed ports, used to excite and control the start-up of the crystal oscillator module, and to adjust the driving gain according to the gain feedback signal of the frequency self-check module.

[0042] The two sampling terminals of the shaping module are connected in parallel to the OSCI terminal and the OSCO terminal of the variable-gain driving module, used to sample the OSCI signal and the OSCO signal of the variable-gain driving module and convert them from sine wave signals to square wave signals for output.

[0043] The frequency self-check module is connected to the output terminal of the shaping module, used to detect the frequency of the square wave signal output by the shaping module, output the status signal of the crystal oscillator according to the comparison between the measured frequency and the preset frequency, and update the gain feedback signal. The status signal is used to indicate the specific working state of the crystal oscillator module, such as too low frequency, too high frequency, or crystal oscillator damage, etc. The gain feedback signal acts on the variable-gain driving module in the reverse direction, used to change the magnitude of the driving gain and achieve the function of adaptive adjustment.

[0044] Referring toFigure 3 As shown, it is a schematic structural diagram of a variable gain driving module provided by this application, including an amplifier module and a feedback resistor RF connected in parallel at the input (OSCI) and output (OSCO) ends of the amplifier module. The amplifier module is used to provide starting oscillation energy to the crystal oscillator closed-loop circuit system, stimulate and maintain the oscillation of the crystal oscillator module, and is expressed by the following formula:

[0045] A(f) = |A(f)| * e jfα(f)

[0046] A feedback channel is formed between the feedback resistor RF and the crystal oscillator module to determine the crystal oscillator oscillation frequency, and is expressed by the following formula:

[0047] B(f) = |B(f)| * e jfβ(f)

[0048] To meet the Barkhausen criterion, the closed-loop gain should be greater than 1, and the total phase shift should be 360°. From this, we can obtain:

[0049] |A(f)| * |B(f)| ≥ 1, and α(f) + β(f) = 2π

[0050] From this, it can be determined that the open-loop gain of this amplifier module should be much greater than 1, and the time to reach stability depends on the magnitude of this open-loop gain.

[0051] Figure 4 It is a schematic structural diagram of the amplifier module provided by this application. In a possible implementation manner, the amplifier module adopts a common-source amplifier structure with a current source as the load, including at least two current sources and an NMOS transistor N0. The outputs of at least two current sources ( Figure 4 illustrated by taking current sources I1 and I2 as examples) are commonly connected to the source electrode of N0, and the OSCO end of this amplifier module is led out from the source electrode. A controllable switch S1 is provided on the first current source I1 in the current sources, and is commonly connected to the source electrode of the NMOS transistor through the controllable switch S1 and the second current source I2. The controllable switch S1 is connected to the gain feedback signal output of the frequency self-checking module, and controls the switch to be turned off or on according to the received gain feedback signal. The gate input end of N0 is led out as the OSCI end of the amplifier module.

[0052] When the controllable switch S1 = 1 and the switch is closed, the current I = I1 + I2;

[0053] When the controllable switch S1 = 0 and the switch is opened, the current I = I2;

[0054] Transconductance

[0055] Gain A V = g m × R o; where U is the carrier mobility, Cox is the unit gate capacitance, and W and L are the width and length of the MOS, respectively.

[0056] It can be seen that the larger the current I, the larger the transconductance and the gain of the operational amplifier. Therefore, when S1 = 1, both the gain and power consumption are relatively large, and the power consumption is equal to VDD * (I1 + I2); when S1 = 0, both the gain and power consumption are relatively small, equal to VDD * I2.

[0057] Among them, the first current source I1 and the second current source I2 can be provided by a reference circuit external to the module and can be generated by modules similar to Bandgap, etc. The specific method is not elaborated in detail in this application. Moreover, this application only shows one possible form of the variable gain driving module, and the NMOS transistor N0 can also be replaced by a current source.

[0058] Figure 5 is a schematic structural diagram of the shaping module provided by an embodiment of the present application. The shaping module includes a signal comparator, a first Schmitt trigger, and a first inverter. The output of the signal comparator is cascaded with the first Schmitt trigger, and the first inverter is cascaded at the output of the first Schmitt trigger and outputs a converted square wave signal.

[0059] The signal comparator is a cascode current mirror structure, including PMOS transistors P1 and P2 connected in common gate, NMOS transistors N1 and N2 connected in common source, and the gate of P1 is connected to the drain of N1, and the source of P2 is connected to the drain of N2, and a converted level signal is output. This current mirror structure can convert a high-level large-voltage signal into a low-level small-voltage signal, and then through the Schmitt trigger and inverter for signal conversion, thereby reducing the power consumption of the entire system.

[0060] The common-source output of the NMOS transistor is grounded through a third current source I3 (provided externally). The gate of N1 is connected to the sampled OSCI signal, and the gate of N2 is connected to the sampled OSCO signal. Since P1 and P2 are two PMOS transistors with the same size, when the voltage of the OSCI signal is the same as the voltage of the OSCO signal, V GSP1 = V GSP2 , at this time, P1 and P2 are in the saturation region, the currents flowing through the two gate input terminals of OSCI and OSCO are equal, and they are also in the saturation region, I DSN1 = I DSN2 = 0.5 * I3. That is, both the left and right paths are allocated a current of 0.5 * I3.

[0061] When the OSCI signal voltage is greater than the OSCO signal voltage, N2 is cut off. At this time, P2 enters the deep linear region, and Vout outputs a high level. After being processed and shaped by the first Schmitt trigger and the first inverter, the conversion level signal (square wave signal) output by CK1 is at a high level (VDD); when the OSCI signal voltage is less than the OSCO signal voltage, N1, P1, and P2 are cut off, and no current flows out through P2, causing Vout to output a low level. After being processed and shaped by SMT and INV, the conversion level signal (square wave signal) output by CK1 is at a low level (GND). Refer to Figure 6 , which is a relationship curve diagram of OSCI - OSCO and the output CK1. Figure 7 It is a waveform diagram of obtaining the CK1 signal based on the sampled OSCI and OSCO signals.

[0062] It should be noted that the structure of the signal comparator is not limited to the above current mirror structure, and forms such as source followers, Schmitt triggers, and inverters can also be used to complete it. Specifically, the embodiments of this application do not make limitations.

[0063] The setting of the frequency self - detection module is mainly to detect the working state of the crystal oscillator module in real - time and give a reminder and self - correction in case of abnormalities. Therefore, in this application, when the frequency of the square wave signal input to the frequency self - detection module is greater than the set frequency, the module outputs a crystal oscillator abnormal state signal; when the frequency of the square wave signal is less than the set frequency, the module outputs a crystal oscillator normal state signal.

[0064] When the frequency self - detection module detects that the crystal oscillator frequency is normal, the driving gain of the variable - gain driving module can be appropriately reduced to ensure normal oscillation and reduce the power consumption of the module. Specifically, a first gain feedback signal for reducing the driving gain is generated and fed back to the variable - gain driving module. When the frequency self - detection module detects that the crystal oscillator frequency is too low, a second gain feedback signal for increasing the gain is generated and fed back to the variable - gain driving module, aiming to increase the driving gain of the variable - gain driving module and use a larger driving current to start the crystal oscillator module and shorten the start - up time of the crystal oscillator.

[0065] The crystal oscillator status signal output is represented by the ERROR signal. When ERROR = 0, it indicates that the crystal oscillator driving module is working normally at this time; when ERROR = 1, it indicates that the crystal oscillator driving module is working abnormally at this time. In addition, the frequency self - detection module is also provided with a CLKOUT output, representing the converted square wave signal. When the frequency of CK1 is greater than the set frequency, CLKOUT outputs CK1, and at this time ERROR = 0; when the frequency of CK1 is less than the set frequency, CLKOUT outputs 0 (no waveform diagram is output), and ERROR = 1.

[0066] Specifically refer to Figure 8, which is a schematic structural diagram of the frequency self - detection module provided by an embodiment of the present application. The module includes a first detection branch, a second detection branch, and a status detection branch connected in parallel.

[0067] The first detection branch includes an NMOS transistor N2 and a PMOS transistor P2 connected in cascode configuration, and a square - wave signal CK1 is input to the common gate. The common - source output V1 is connected to a second Schmitt trigger, and the output V3 of the second Schmitt trigger is connected to a second inverter. The drain of P2 is connected to the input power supply VDD, and the drain of N2 is grounded through a fourth current source I4.

[0068] The second detection branch includes an NMOS transistor N3 and a PMOS transistor P3 connected in cascode configuration, and a square - wave signal CK1 is input to the common gate. The common - source output V2 is connected to a third Schmitt trigger, and the output V4 of the third Schmitt trigger is connected to a third inverter. The drain of P3 is connected to the input power supply VDD and a cascaded fifth current source I5, and the drain of N3 is grounded.

[0069] The outputs of the second inverter and the third inverter are connected to the status detection branch. The status detection branch includes a NAND gate, a fourth inverter, and a first AND gate cascaded in sequence. The outputs of the second inverter and the third inverter are connected to the inputs of the first NAND gate. The output V5 of the first NAND gate is the status signal (ERROR signal) representing the crystal oscillator. The inputs of the first AND gate are respectively connected to the output of the fourth inverter and the square - wave signal output CK1 of the shaping module.

[0070] When CK1 = GND (low level), P2 and P3 are turned on, and N2 and N3 are turned off. At this time, V1 = VDD, and V2 starts to rise from 0, and the rising speed depends on the grounding capacitor C2 and the current I5. When the time that CK1 = GND is long enough and the voltage of V2 rises above the flip - point of the SMT, then V4 will output 0 (low level) at this time, and V5 will output 0 at this time, resetting the T - flip - flop. When the T - flip - flop is reset, Q outputs 0. At this time, ERROR = 1, indicating that the frequency of CK1 is incorrect, and at this time, CLKOUT will be pulled to 0.

[0071] When CK1 = VDD (high level), P1 and P2 are turned off, and N1 and N2 are turned on. At this time, V2 = GND, and V1 starts to drop from VDD, and the dropping speed depends on the grounding capacitor C1 and the magnitude of the current I4. When the time that CK1 = VDD is long enough, then V1 will be lower than the flip - point of the SMT. Then V3 outputs 1 (high level) at this time, V5 outputs 0 (low level) at this time, and ERROR = 1, indicating that the frequency of CK1 is incorrect, and at this time, CLKOUT will be pulled to 0.

[0072] In the above embodiments, by configuring the inversion points of I4, I5, C1, C2, and SMT, the detection frequency of CK1 is set, and SMT is used instead of INV to process the V1 and V2 signals because the hysteresis function of SMT can enhance the anti-interference ability and prevent noise spikes from causing incorrect error reports.

[0073] Exemplarily, assuming the frequency of the crystal oscillator is Fosc and the duty cycle requirement is 40% < duty cycle < 60%, then we can obtain:

[0074] High-level time

[0075] Low-level time

[0076] V smt is the switching voltage of the Schmitt trigger. Substituting it into we get F OSC value, as follows:

[0077]

[0078] Similarly, calculating Substituting into we get F OSC value, as follows:

[0079]

[0080] Assuming the crystal oscillator frequency is 1 MHZ, the switching point of SMT is designed as 0.5 * VDD, and the operating voltage is 5V. Based on the above, we can obtain T 高 < 600 ns and T 低 < 600 ns. Substituting into the calculation, we get the values of each resistance: C1 = C2 = 0.24 pf, I4 = I5 = 1 uA. Only when T 高 < 600 ns and T 低 < 600 ns, ERROR will output 0 and CLKOUT can output CK1. When any one of the conditions is not met, ERROR = 1, indicating that the frequency is incorrect at this time and CLKOUT outputs 0.

[0081] In some other embodiments, in order to prevent the crystal oscillator frequency from fluctuating and causing the CLKOUT output to be disordered, several TFF flip-flops are added as warm-up delay time in the frequency self-check module of the present application. Figure 9It is a schematic diagram of the structure after adding a TFF flip-flop to the status detection branch. The outputs of the first and second detection branches are connected to an AND gate. The output of the AND gate is respectively input to a number of cascaded TFF flip-flops. The V6 output by the flip-flop outputs an ERROR signal through an inverter, and the V6 signal is output again through an inverter and used as two outputs of a NAND gate together with the CK1 signal output. The output of the NAND gate is used as the clock input of the first cascaded flip-flop.

[0082] Based on the above circuit configuration, if the number of configured flip-flops is n, then after the frequency meets the condition, it is necessary to count 2 n more oscillation periods before ERROR can change from 1 to 0. Once the frequency is lower than the preset value, ERROR will immediately become 1. These 2 n oscillation periods are called the warm-up time. The setting of the warm-up time can increase the stability of the output signal of the system.

[0083] Figure 10 It is the timing diagram of each point obtained by using a low-power crystal oscillator driving circuit with a self-check function.

[0084] Stage T1: The frequency of CK1 (square wave) is normal. V1 is always higher than the SMT flip point, V2 is always lower than the SMT flip point, V3 = 0, V4 = 1. At this time, V5 = 1, ERROR = 0, and CLKOUT normally outputs the waveform of CK1.

[0085] Stage T2: The frequency of CK1 is abnormal and the high-level time is too long. At this time, V1 drops below the SMT flip point, V2 is lower than the SMT flip point, V3 = 1, V4 = 1, V5 outputs 0, and at this time ERROR immediately becomes 1, and CLKOUT outputs 0.

[0086] Stage T3: The frequency of CK1 returns to normal. V1 is always higher than the SMT flip point, V2 is always lower than the SMT flip point, V3 = 0, V4 = 1. At this time, V5 = 1, ERROR is in the warm-up state at this time and still equals 1, and CLKOUT outputs 0.

[0087] Stage T4: The normal time of the frequency of CK1 exceeds the warm-up duration, the warm-up time ends, ERROR changes from 1 to 0, and CLKOUT outputs CK1.

[0088] Stage T5: The frequency of CK1 is abnormal and the low-level time is too long. At this time, V1 is always higher than the SMT flip point, V2 rises above the SMT flip point, V3 outputs 1, V4 outputs 1, V5 outputs 0, and at this time ERROR immediately becomes 1, and CLKOUT outputs 0.

[0089] T6 stage: The frequency of CK1 returns to normal, V1 is always higher than the SMT flip point, V2 is always lower than the SMT flip point, V3 = 0, and V4 = 1. At this time, V5 = 1, ERROR is in the warm-up state and still equals 1, and CLKOUT outputs 0.

[0090] T7 stage: The normal time of the frequency of CK1 exceeds the warm-up duration, the warm-up time ends, ERROR changes from 1 to 0, and CLKOUT outputs CK1.

[0091] Based on the above working principle, during the startup process of the crystal oscillator module of the circuit, when it is detected that the crystal oscillator frequency is too low at startup, ERROR = 1. At this time, a second gain feedback signal with increased gain is generated based on the ERROR signal and acts on the controllable switch S1. S1 closes the switch and conducts the first current source I1 based on this second gain feedback signal. At this time, the drive current I = I1 + I2, which speeds up the startup and shortens the crystal oscillator stabilization time. When the crystal oscillator starts and works stably, ERROR = 0. At this time, a first gain feedback signal with reduced gain is generated based on the ERROR signal, and S1 disconnects. At this time, the drive current I = I2, and the drive current decreases, reducing the overall power consumption of the circuit.

[0092] The preferred embodiments of the present invention have been described above; it should be understood that the present invention is not limited to the above specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any person skilled in the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes, which does not affect the essence of the present invention; therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

Claims

1. A low-power crystal oscillator drive circuit with a self-check function, characterized in that The crystal oscillator driving circuit is connected to an external crystal oscillator circuit through two multiplexed ports; the crystal oscillator driving circuit includes a variable gain driving module, a shaping module, and a frequency self-checking module; The oscillation input OSCI terminal and the oscillation output OSCO terminal of the variable gain driving module are connected in parallel with the crystal oscillator module, and are used to control the crystal oscillator module to start oscillating and adjust the driving gain according to the gain feedback signal of the frequency self-checking module; The shaping module is connected in parallel between the OSCI terminal and the OSCO terminal, and is used to convert the OSCI signal and the OSCO signal of the variable gain driving module from sine wave signals into square wave signals for output; The frequency self-checking module is connected to the output terminal of the shaping module, and is used to detect the frequency of the square wave signal output by the shaping module, output the status signal of the crystal oscillator according to the magnitude of the measured frequency and the preset frequency, and update the gain feedback signal; specifically, when the frequency of the square wave signal input to the frequency self-checking module is greater than the set frequency, an abnormal status signal of the crystal oscillator is output; when the frequency of the square wave signal is less than the set frequency, a normal status signal of the crystal oscillator is output; When the frequency self-checking module outputs a normal status signal of the crystal oscillator, a first gain feedback signal for reducing the driving gain is generated and fed back to the variable gain driving module; when the frequency self-checking module outputs an abnormal status signal of the crystal oscillator, a second gain feedback signal for increasing the gain is generated and fed back to the variable gain driving module.

2. The low-power crystal oscillator driving circuit with a self-checking function according to claim 1, wherein The variable gain driving module includes an amplifier module and a feedback resistor connected in parallel between the input and output terminals; the amplifier module is used to provide starting oscillation energy to the crystal oscillator circuit, and a feedback channel is formed between the feedback resistor and the crystal oscillator module to determine the oscillation frequency.

3. The low-power crystal oscillator driving circuit with a self-check function according to claim 2, characterized in that, The amplifier module is a common-source amplifier with a current source as the load, and includes at least two current sources and an NMOS transistor N0; The outputs of at least two current sources are commonly connected to the source electrode of N0, and the OSCO terminal of the amplifier module is led out from the source electrode; A controllable switch is provided on the first current source I1 in the current sources, and is commonly connected to the source electrode of the NMOS transistor through the controllable switch and the second current source I2; The controllable switch is connected to the frequency self-checking module, and is controlled to be turned off or on according to the received gain feedback signal. The gate input terminal of N0 is led out as the OSCI terminal of the amplifier module.

4. The low-power crystal oscillator driving circuit with a self-check function according to claim 1, characterized in that, The shaping module includes a signal comparator, a first Schmitt trigger, and a first inverter; the output of the signal comparator is cascaded with the first Schmitt trigger, and the first inverter is cascaded at the output terminal of the first Schmitt trigger and outputs the converted square wave signal; The signal comparator is a common-source common-gate current mirror structure, and includes a PMOS transistor P1 and a PMOS transistor P2 connected in common-gate, an NMOS transistor N1 and an NMOS transistor N2 connected in common-source, and the gate of P1 is connected to the drain of N1, the source of P2 is connected to the drain of N2, and a converted level signal is output; The common-source output of the NMOS transistor is grounded through a third current source I3; the gate of N1 is connected to the OSCI signal, and the gate of N2 is connected to the OSCO signal.

5. The low-power crystal oscillator driving circuit with a self-checking function according to claim 4, wherein, When the OSCI signal voltage is greater than the OSCO signal voltage, N2 is cut off, and the output conversion level signal is a high-level signal; when the OSCI signal voltage is less than the OSCO signal voltage, N1, P1, and P2 are cut off, and the output conversion level signal is a low-level signal.

6. The low-power crystal oscillator driving circuit with a self-checking function according to claim 5, characterized in that The first Schmitt trigger and the first inverter process and shape the input conversion level signal to output a converted square wave signal; wherein, when the conversion level signal is a high-level signal, the square wave signal is a high level; when the conversion level signal is a low-level signal, the square wave signal is a low level.

7. The low-power crystal oscillator driving circuit with a self-check function according to claim 1, wherein The frequency self-checking module includes a first detection branch, a second detection branch, and a state detection branch connected in parallel. The first detection branch includes an NMOS transistor N2 and a PMOS transistor P2 connected in common-gate and common-source, with the square wave signal input at the common gate and the output at the common source connected to a second Schmitt trigger, and the output of the second Schmitt trigger is connected to a second inverter; the drain of P2 is connected to the input power supply VDD, and the drain of N2 is grounded through a fourth current source I4. The second detection branch includes an NMOS transistor N3 and a PMOS transistor P3 connected in common-gate and common-source, with the square wave signal input at the common gate and the output at the common source connected to a third Schmitt trigger, and the output of the third Schmitt trigger is connected to a third inverter; the drain of P3 is connected to the input power supply VDD and a cascaded fifth current source I5, and the drain of N3 is grounded.

8. The low-power crystal oscillator driving circuit with a self-check function according to claim 7, wherein The outputs of the second inverter and the third inverter are connected to the state detection branch.

9. The low-power crystal oscillator driving circuit with a self-checking function according to claim 8, characterized in that, The state detection branch includes a NAND gate, a fourth inverter, and a first AND gate cascaded in sequence; the outputs of the second inverter and the third inverter are connected to the inputs of the first NAND gate, and the first NAND gate outputs the state signal of the crystal oscillator; the inputs of the first AND gate are respectively connected to the output of the fourth inverter and the square wave signal output of the shaping module.

Images