Method for generating a divided signal and clock generating circuit

Abstract

Embodiments of the invention disclose a method for generating divided signals and a clock generation circuit. In embodiments of the invention, the clock generation circuit generates a plurality of divided signals, each divided signal satisfying a respective desired offset, which can be specified by a specification from an external source. A phase-locked loop (PLL) is used to generate a PLL output at a desired multiple of the frequency of a reference clock. The clock generation circuit receives a corresponding desired time offset for each divided signal.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims priority to Indian Provisional Patent Application No. 202141050628, filed November 3, 2021, entitled “Management of Input to Output Delay of Multiple PLLs with Same Input Clock and Single PLL,” and U.S. Patent Application No. 17 / 806,735, filed June 14, 2022, entitled “Generation of a Divided-down signal from a phase-locked loop output when a reference clock is unavailable.” The above-mentioned Indian Provisional Patent Application and U.S. Patent Application are incorporated herein by reference to the extent not inconsistent with the description herein. TECHNICAL FIELD

[0003] Embodiments of the present invention relate generally to phase-locked loops (PLLs), and more particularly to generation of a divided-down signal from a PLL output when a reference clock is unavailable. BACKGROUND

[0004] PLLs are commonly used to generate clock signals. A PLL receives an input (reference) clock and generates an output clock (PLL output) that is in phase with the input signal, but the frequency of the output clock is a desired multiple of the frequency of the input clock. As is well known in the related art, PLLs are used in a variety of communication scenarios.

[0005] Divided-down (clock) signals are often generated from a PLL output, each divided-down signal having a time period that is an integer multiple of the time period of the PLL output. Such divided-down signals are often needed when it is specified that each divided-down signal is to satisfy a corresponding phase offset, e.g., relative to the input clock.

[0006] However, there are often situations in which the input clock becomes unavailable. Aspects of the present invention are used to generate a divided-down signal in such situations. SUMMARY

[0007] Embodiments of the invention relate to a method for generating frequency-divided signals. The method comprises: generating a phase-locked loop (PLL) output using a PLL; a frequency of the PLL output is a desired multiple of a frequency of a reference clock; receiving a respective desired time offset corresponding to each of a plurality of frequency-divided signals; dividing the PLL output by a divisor to generate a respective frequency-divided signal of the plurality of frequency-divided signals, wherein each frequency-divided signal is offset from a common reference by at least the associated desired time offset. A timing of the common reference is set with respect to the reference clock when the reference clock is available; a timing of the common reference is set with respect to a time reference signal when the reference clock is not available. The time reference signal is generated externally to the reference clock. In some embodiments, a first edge of each frequency-divided signal has the associated desired time offset from a first edge of the PLL output and the first edge of each frequency-divided signal follows the first edge of the PLL output; a second edge of each frequency-divided signal has the associated desired time offset from a second edge of the PLL output and the second edge of each frequency-divided signal follows the second edge of the PLL output. When the reference clock is not available, the second edge of the PLL output follows a second edge of the time reference signal.

[0008] In some embodiments, frequency dividing comprises counting a number of clock cycles of the PLL output from a first time instant at which the frequency divider reset signal is received.

[0009] In some embodiments, generating the frequency divider reset signal comprises: selecting one of the reference clock and the time reference signal as the common reference under control of a selection signal; synchronizing a first reset signal to the common reference to generate a first synchronized signal; synchronizing the first synchronized signal to the PLL output to generate a second synchronized signal; and delaying the second synchronized signal by the associated desired time offset to set the first time instant.

[0010] In some embodiments, when the reference clock is not available, the PLL is operated in a holdover mode, wherein the holdover mode requires the PLL to continue generating the PLL output without using the reference clock, wherein the first reset signal is generated upon receiving an external reset signal after the PLL is operated in the holdover mode for at least a duration.

[0011] In some embodiments, each frequency-divided signal is offset from the common reference by the associated desired time offset plus a number of cycles of the PLL output.

[0012] Embodiments of the present application also relate to a clock generation circuit for generating frequency-divided signals. The clock generation circuit includes a phase-locked loop (PLL) and a frequency divider circuit. The PLL is configured to generate a PLL output; a frequency of the PLL output is a desired multiple of a frequency of a reference clock. The frequency divider circuit is configured to divide the PLL output by a divisor to generate a respective frequency-divided signal of a plurality of frequency-divided signals, wherein the respective frequency-divided signal is offset from a common reference by at least a desired time offset. A timing of the common reference is set with respect to the reference clock when the reference clock is available; the timing of the common reference is set with respect to a time reference signal when the reference clock is not available. The time reference signal is generated externally to the reference clock.

[0013] In some embodiments, a first edge of each frequency-divided signal has the desired time offset from a first edge of the PLL output and is located after the first edge of the PLL output; the first edge of the PLL output follows a first edge of the reference clock when the reference clock is available. A second edge of each frequency-divided signal has the desired time offset from a second edge of the PLL output and is located after the second edge of the PLL output; the second edge of the PLL output follows a second edge of the time reference signal when the reference clock is not available.

[0014] In some embodiments, the frequency divider circuit includes a counter. The counter is configured to count a number of clock cycles of the PLL output to generate the frequency-divided signal from a first time instant at which the frequency divider reset signal is received. In some embodiments, the clock generation circuit further includes a synchronization circuit. The synchronization circuit is configured to generate the frequency divider reset signal at the first time instant. The synchronization circuit includes a multiplexer, a first flip-flop, a second flip-flop, and a delay block. The multiplexer is configured to select one of the reference clock and the time reference signal as the common reference under control of a selection signal. The first flip-flop is configured to synchronize the first reset signal with the common reference to generate a first synchronized signal. The second flip-flop is configured to synchronize the first synchronized signal with the PLL output to generate a second synchronized signal. The delay block is configured to delay the second synchronized signal by the desired time offset to set the first time instant.

[0015] In some embodiments, when the reference clock is not available, the PLL is operated in a holdover mode, wherein the holdover mode requires the PLL to continue generating the PLL output without using the reference clock, the first reset signal is generated upon receiving an external reset signal after the PLL is operated in the holdover mode for at least a duration.

[0016] In some embodiments, the clock generation circuit further includes an internal clock generator configured to generate an internal clock signal as the time reference signal.

[0017] In some embodiments, each divided signal is offset relative to the common reference by the associated desired time offset plus a number of cycles of the PLL output.

[0018] Embodiments of the invention also relate to a clock generation circuit for generating a plurality of divided signals having predetermined relative phase delays. The clock generation circuit comprises a plurality of phase-locked loops, PLLs. Each PLL generates a respective PLL output and a respective subset of divided signals of the plurality of divided signals. Each divided signal of the plurality of divided signals is offset relative to a reference clock by at least an associated predetermined phase delay. An external reset signal is used to reset the plurality of PLLs, wherein the reset causes each PLL to be initialized and then reach a steady state; wherein all of the plurality of PLLs reach the steady state within a time duration after the external reset signal. The reference clock is blocked for the time duration.

[0019] In some embodiments, the clock generation circuit further comprises a synchronization block. The synchronization block is used to synchronize the first reset signal with the reference clock to generate a first synchronized signal. The first reset signal is asserted at the end of the time duration.

[0020] In some embodiments, the clock generation circuit further comprises a plurality of flip-flops and a plurality of output generator blocks. The plurality of flip-flops corresponds to each of the plurality of PLLs. The plurality of output generator blocks corresponds to each of the plurality of PLLs. Each flip-flop of the plurality of flip-flops is used to synchronize the first synchronized signal with the respective PLL output to generate a respective second synchronized signal. Each output generator block of the plurality of output generator blocks delays the second synchronized signal by the associated predetermined phase delay and divides the respective PLL output by a respective divisor to generate a respective divided signal of the plurality of divided signals.

[0021] In some embodiments, the time reference signal is used for synchronization even when the reference clock is available by continuing to block the reference clock after the time duration.

[0022] In some embodiments, the synchronization block comprises an internal clock generator to generate an internal clock signal as the time reference signal.

[0023] In some embodiments, each divided signal is offset relative to the reference clock or the time reference signal by the associated predetermined phase delay plus a number of cycles of the respective PLL output. BRIEF DESCRIPTION OF DRAWINGS

[0024] Example embodiments of the invention will be described with reference to the following figures, shortly described.

[0025] Figure 1 A block diagram of an example device in which aspects of the invention can be implemented is shown.

[0026] Figure 2A timing diagram illustrating the technique of generating divided signals in an embodiment of the invention.

[0027] Figure 3 A flowchart illustrating the technique of generating divided signals in an embodiment of the invention.

[0028] Figure 4 A block diagram illustrating a clock generation circuit implemented in an embodiment of the invention.

[0029] Figure 5 A timing diagram illustrating the technique of generating divided signals in an embodiment of the invention.

[0030] Figure 6 A block diagram illustrating a clock generation circuit generating divided signals for a plurality of PLLs in an embodiment of the invention.

[0031] Figure 7 A block diagram illustrating a system that can be combined with an apparatus implemented in accordance with aspects of the invention in an embodiment of the invention.

[0032] In the drawings, like reference numerals are generally used to refer to like elements throughout. The first occurrence of a reference numeral in a figure is shown by the left-most digit(s) of that reference numeral in the figure. DETAILED DESCRIPTION

[0033] 1. OVERVIEW

[0034] A clock generation circuit generates a plurality of divided signals, each divided signal satisfying a respective desired offset, which can be specified by a specification from an external source, in accordance with an aspect of the invention. In one embodiment, a phase locked loop (PLL) is used to generate a PLL output having a frequency that is a desired multiple of a frequency of a reference clock. The clock generation circuit receives a respective desired time offset for each divided signal.

[0035] The clock generation circuit divides the PLL output by a respective integer or fraction (dividing ratio / divisor) to generate a respective divided signal, where each divided signal is offset from a common reference by at least the respective desired time offset. The timing of the common reference is set with respect to the reference clock when the reference clock is available, and the timing of the common reference is set with respect to a time reference signal when the reference clock is not available. The time reference signal is generated externally to the reference clock (i.e., the time reference signal is independent of the reference clock, e.g., the time reference signal is not derived from the reference clock).

[0036] According to another aspect, when the reference clock is available, the edges of each divided signal have a relative time offset from and follow closely the edges of the PLL output, and the edges of each divided signal are after the edges of the PLL output. When the reference clock is not available, the edges of each divided signal have a relative time offset from and follow the edges of the PLL output, wherein the edges of the PLL output follow the edges of a time reference signal. The time reference signal is similarly used to generate all divided signals when the reference clock is not available.

[0037] Thus, when the reference clock is available and not available, the relative phase difference between the divided signals is maintained as required by the external specification. However, when the reference clock is available, the timing of all generated divided signals is set relative to the edges of the reference clock, but further synchronized with the (high frequency) PLL output. In particular, (in addition to meeting the relative offset requirements) each divided clock is synchronized with the edges of the PLL output that follow the edges of the reference clock (e.g., the edges of the PLL output occur one or two PLL output clock periods after the edges of the reference clock). When the reference clock is not available, the time reference signal is used in place of the reference clock to provide the corresponding functionality.

[0038] According to another aspect, the dividing operation can require counting the number of clock periods of the PLL output from a specified first instant in time that meets the timing described above.

[0039] According to another aspect, a multiplexer is used to select one of the reference clock and the time reference signal as a common reference under the control of a selection signal (the selection signal is used to indicate whether the reference clock is available). A first flip-flop synchronizes the first reset signal with the common reference to generate a first synchronized signal. A second flip-flop synchronizes the first synchronized signal with the PLL output to generate a second synchronized signal, and a delay block delays the second synchronized signal by the relative time offset to set the first instant in time at which counting begins.

[0040] According to another aspect, when the reference clock is not available, the PLL operates in a hold-over mode, wherein the hold-over mode requires the PLL to continue to generate the PLL output without using the reference clock. Thus, prior to entering the hold-over mode, the divided signals are generated based on the common timing reference provided by the reference clock. However, upon receiving an external reset signal (when the PLL is operating in the hold-over mode), a first reset signal is generated to cause the time reference signal to thereafter control the timing of the divided signals. In one embodiment, the time reference signal is implemented in the form of an internal clock signal generated within the clock generation circuit.

[0041] Several aspects of the application are described below with reference to example illustrations. It should be stressed, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the application. Further, the described features / aspects can be implemented in a wide variety of combinations, merely a few of which are described herein for simplicity. For clarity, certain aspects / features will be described for selective dissemination in this initial patent application. Subsequent continuation-in-part applications will disclose additional aspects / features.

[0042] 2. Example assembly

[0043] Figure 1 A block diagram showing details of an example assembly that is scalable in accordance with several aspects of the application is shown. The shown block diagram includes a PLL 100 and dividers 110-1 through divider 110-m, for ease of understanding, Figure 1 The block diagram will be described with reference to Figure 2 a timing diagram. It will be clear from the context that the dividers will be individually or collectively denoted by reference numeral 110. Similar convention is employed for the corresponding related signals.

[0044] The shown PLL 100 receives an input clock fref and generates a PLL output fout. The PLL 100 can be implemented in a known manner. Each divider 110 divides the PLL output fout on path 131 by a respective ratio received from an external source to generate a respective divided signal 195.

[0045] Each ratio can be an integer or a sum of an integer and a fractional component, and in addition, any pair of ratios needs to be related to each other by a fixed ratio. Thus, the shown PLL output fout is locked to the input clock fref at a frequency that is 10 times the input clock fref for illustration. The divided signal 195-1 and the divided signal 195-2 have a division factor of 4 and a division factor of 2, respectively, satisfying the fixed ratio requirement as an example.

[0046] The phase of each divided signal 195 is controlled by an offset on path 106 received from an external source. Thus, the shown divided signal 195-1 and the divided signal 195-2 have respective offsets and offset from the rising edge of the input clock fref. It is assumed that these offset values are received on path 106-1 and path 106-2, respectively.

[0047] However, there are often situations where the input clock fref is not available, but there are also requirements to continue to produce frequency divided signals with similar requirements as described above, at least in some environments, such as PLLs in telecommunication systems. For example, a receive array of time-interleaved Analog to Digital Converters (ADCs) still requires a SYSREF (input reference clock) and device clocks (frequency divided signals) with correct frequency ratios, and more importantly, a relative delay between the frequency divided signals from the PLL. As described in further detail below, aspects of the present invention are used to provide frequency divided signals even in such scenarios.

[0048] 3. Generating frequency divided signals

[0049] Figure 3 A flowchart of generating frequency divided signals according to aspects of the present invention is shown. For illustration only, the flowchart is described with reference to the components of Figure 1 However, many features can also be implemented in other components / systems and / or other environments without departing from the scope and spirit of aspects of the present invention, as will be apparent to those skilled in the art upon reading the disclosure provided herein. Also, some steps can be performed in a different order than described below, as will be apparent to those skilled in the relevant art, to suit a particular environment. Aspects of the present invention are intended to cover many such implementations. The flowchart starts at step 301, where control immediately goes to step 310.

[0050] At step 310, the PLL 100 generates a PLL output fout, where the frequency of the PLL output fout is a desired multiple of the frequency of the reference clock. At step 320, a respective desired offset for each frequency divided signal is received. At step 330, the controller checks whether the reference clock becomes unavailable, i.e. a previously available clock signal is now unavailable. If it is found that the clock continues to be available, control goes to step 340; otherwise, to step 350.

[0051] At step 340, the frequency divided signals are generated with respective desired offsets relative to the reference clock. Thus, when the reference clock is available, the reference clock provides a common (timing) reference for all frequency divided signals. Control then goes to step 330.

[0052] At step 350, an internal clock is generated, and at step 360, the frequency divided signals are generated with respective desired offsets relative to the internal clock. It will be appreciated that the edges of the internal clock provide a common reference for controlling the relative timing of the frequency divided signals. However, other time reference signals (e.g. a set of pulses) can also be employed, as appropriate for the respective environment. Control then goes to step 330.

[0053] Thus,Figure 3 The method of the application is used to ensure that a divided signal (corresponding to a desired division factor) is provided at least in a situation where the relative phase difference is maintained, wherein another time reference signal is used as a common reference when the reference clock is not available.

[0054] It can be noted that, Figure 3 The flowchart of the application is made under the assumption that a previously available reference clock signal becomes unavailable (e.g. after an external reset). However, such a situation can also occur when the reference clock fref is initially not available, i.e. at the first wake-up of a system comprising a PLL. This can occur for example due to a physical disruption in the telecommunication line providing the reference clock, etc. As described in the examples below, aspects of the application provide a divided signal with a predetermined relative phase delay in such a situation.

[0055] 4. Clock generation circuit

[0056] Figure 4 A block diagram of a clock generation circuit implemented in accordance with aspects of the application is shown. The shown clock generation circuit 400 comprises a multiplexer (MUX) 405, flip-flops 415 and 420, an internal clock generator 460, a controller 450, a PLL 100, and output generators 480-1 and 480-2. Each output generator 480 comprises a flip-flop 430, a delay block 435, and a counter 410.

[0057] For the sake of simplicity, only some exemplary components (e.g. multiple output generators) are shown. Figure 4 The specific blocks or components of the clock generation circuit 400 of the application are shown for illustration only. Other embodiments of the clock generation circuit 400 can be implemented with other blocks / components (analog blocks or components, digital blocks or components, and / or a combination of analog blocks or components and digital blocks or components), as will be apparent to the skilled person upon reading the disclosure provided herein. For example, although blocks 460, 405, 450, 415, and 420 are shown as being implemented outside the PLL 100, in alternative embodiments these blocks can be implemented as part of the PLL 100.

[0058] The internal clock generator 460 generates an (accurate and stable) internal clock fint, which functions as follows. The internal clock fint is used to re-set the timing of the divided signal upon receiving a logic high on path 409, as described below. The internal clock fint can be a set of pulses used to synchronize the divided clock, or the internal clock fint can be a continuous clock. The present invention has no requirement on the frequency of the internal clock, since the main requirement is to be able to use the internal clock as an event marker to align the proper relative delays on all the outputs from the PLL 100.

[0059] The illustrated MUX 405 is used to receive the input (reference) clock fref on path 101 and the internal clock fint on path 411. The MUX 405 forwards one of the input clock fref and the internal clock fint on path 406 as the common (time) reference based on the logic value of a selection signal received on path 451. In one embodiment, the MUX 405 forwards the internal clock fint as the selected common reference when the value of the selection signal received on path 451 is a logic high, and otherwise forwards the input clock fref as the selected common reference.

[0060] The controller 450 determines whether the reference clock on path 101 is available, and controls the selection signal to cause the reference clock fref to be selected when the reference clock is available, and otherwise causes the internal clock fint to be selected when the reference clock is not available. Thus, the controller 450 controls the selection of the common reference on path 406. In one embodiment, an external component uses the signal 443 to indicate the presence of another clock signal (not shown, but would be provided as an input to the MUX 405), and the controller can control the selection signal on path 451 to select that other clock signal as the common reference on path 406. Alternatively, the controller 450 can be controlled entirely by on-chip internal indicators. In one embodiment, such indicators can be various clock loss and frequency drift monitors of the reference clock.

[0061] In operation, the controller 450 can be pre-programmed to consider the reference clock fref on the path 101 as the primary clock, and the internal clock fint on the path 411 as the secondary / redundant / back-up clock. Thus, by default (e.g., upon power-up of the PLL 100), the controller 450 can program the binary value of the select signal on the path 451 to cause the MUX 405 to forward the reference clock fref on the path 406. The controller 450 continues to verify whether the reference clock fref is functional (and thus available). Upon determining that the reference clock fref has failed (not functional), the controller 450 can program the binary value of the select signal on the path 451 to cause the MUX 405 to forward the internal clock fint on the path 406.

[0062] The clocking of the flip-flop 415 is set by the common reference produced by the MUX 405 on the path 406. The flip-flop 415 receives the reset signal on the path 409 at its input (D) and produces an output (Q) on the path 416, i.e., the synchronization signal sync-1. In one embodiment, the flip-flop 415 is implemented as a positive edge triggered flip-flop. Thus, the flip-flop 415 is used to synchronize the reset signal with the first rising edge of the reference clock fref on the path 101 immediately after the reset signal is received on the path 409. In this embodiment, the reset signal is shown as being received from the PLL 100. Alternatively, in an alternate embodiment, the reset signal can also be an external signal obtained from a different reference, e.g., another subsystem on the chip, or an external signal received by the chip.

[0063] Similarly, the flip-flop 420 is used to synchronize the synchronization signal sync-1 on the path 416 with the first edge of the PLL output fout that is immediately following the first rising edge of the reference clock fref on the path 101 described above. As can be readily appreciated, the reset signal is forwarded in synchronization with the first positive edge after the reset signal arrives. The term "immediately following" is used to express this timing relationship.

[0064] On the other hand, when a few clock cycles can elapse before the output is provided (e.g., 2 clock cycles in the following embodiment), the term "closely following" can be used to express this relationship. Typically, given that the frequency of the PLL output fout is much higher than the reference clock signal and the divided signals, the resynchronized signals follow the corresponding edges of the common reference. Each output generator 480 receives the PLL output fout on path 131, receives the synchronization signal sync-2 on path 421, and generates the divided signal on the corresponding path 495. The clock of the flip-flop 430 is set by the PLL output, and the flip-flop 430 is further used to synchronize the synchronization signal sync-2 and the PLL output fout, the generated signal is provided on path 432. The flip-flop 430 is used to synchronize the synchronization signal sync-2 received on path 421 with respect to the PLL output fout. This is done to reduce the uncertainty that can be introduced due to the path delays between the different output generators 480. In other words, the synchronization signal sync-1 can be affected by path delays, i.e., the synchronization signal sync-1 can be received at different output generators 480 at different times. Therefore, a second set of synchronization is needed using flip-flop 420 and flip-flop 430, which receive the PLL output signal fout on path 131, which is typically the highest frequency clock available in the system. Even after the synchronization signal sync-1 on path 416 is synchronized with the PLL output signal fout using flip-flop 420, each output generator 480 can receive the synchronization signal sync-2 on path 421 at different times due to path delays, and thus each output generator 480 can start to generate the divided signal asynchronously (after applying the relevant offset) resulting in not being able to maintain the specified relative phase difference (between the divided signals). Using two flip-flops can solve any such issues. It is worth noting that the cascade of two flip-flops ensures that there are no metastability issues in the synchronization with the PLL output fout clock on path 131. For example, the synchronization signal sync-1 on path 416 can have metastability with respect to the PLL output fout on path 131; therefore, the synchronization signal sync-1 on path 416 cannot be sent directly to flip-flop 430, a single unique flip-flop 420 is needed to be added.

[0065] The delay block 435 delays the signal received on path 432 by an amount that is received from path 106. When the clock of the delay block 435 is set by the PLL output fout on path 131, the amount can also be converted to a number of clock periods of the PLL output fout. Thus, the output of the delay block represents the timing corresponding to the amount received on path 106 offset by a particular edge of the PLL output fout, which follows an edge of the common reference (in the example, the particular edge occurs 2 clock periods after the edge of the common reference). The delay block 435 can also be implemented in known ways (e.g., using a counter, a delay line, an RC delay, an inverter delay, etc.). In this case, the delay is not in units of periods of the PLL output fout, and a more general implementation can be employed. The counter 410 divides the frequency of the PLL output fout by a desired divisor (which can be an integer or a fraction). The counter 410 is used to count the number of clock periods of the PLL output fout from a time specified on path 436. When the number of clock periods equals an integer value received on path 105 (i.e., when the divisor is an integer), or when the average number of clock periods of the PLL output fout equals a fractional divisor received on path 105 (i.e., when the divisor is a fraction), a divide-by-one signal period is deemed to have elapsed. Thus, the counter 410 is used to divide the PLL output fout by a desired ratio (e.g., which can be determined based on a divide-code set by a user through a corresponding, not shown, device) from a time specified on path 436. The resulting divide-by-one signal f-div is provided on path 495.

[0066] From the above description, it can be appreciated that the reset signal triggers the resetting of the timing of the divide-by-one clock signal. Although not mentioned above, the timing of the reset signal can be reset when the reference signal becomes available (after being unavailable). The reset signal can be used to support operation during a holdover mode, which is first briefly described below.

[0067] 5. Support for Holdover Mode

[0068] The holdover mode refers to a mode of operation in which the PLL 100 continues to produce the PLL output fout having characteristics similar to those prior to entering the holdover mode for a period of time. Thus, the PLL 100 enters the holdover mode when the input clock fref is unavailable.

[0069] Generally, in hold mode, the PLL 100 operates in open loop mode, in which an oscillator (not shown) within the PLL 100 does not respond to (i.e., is not responsive to changes in) the input clock fref. The last known valid state of the oscillator (not shown) in the PLL 100 is stored and used to continue to generate the PLL output fout. The operation of the PLL in hold mode is described in detail in U.S. Patent No. 10,514,720, entitled "Glitchless Switching When Generating an Output Clock from Multiple Redundant Input Clocks."

[0070] According to an aspect of the present invention, the re-setting of the timing is not initiated immediately upon entering hold mode. Rather, the PLL 100 generates the reset signal only after receiving an external reset on path 471, e.g., after the PLL 100 is powered up and reaches steady state. The external reset can be generated based on a corresponding convention and converted to the appropriate logic level, as is well known. Thus, after receiving the external reset on path 471, the timing of the divided signal is re-set according to the internal clock fint on path 411. The corresponding timing relationships in an embodiment are shown below.

[0071] 6. Timing Relationships When Reference Clock is Unavailable

[0072] Figure 5 A non-to-scale timing diagram of the divided signal generated from the PLL output when the input clock is unavailable is shown. Figure 5 Example waveforms of the input clock fref on path 101, the internal clock fint on path 411, the PLL output fout on path 131, the select signal on path 451, the common reference on path 406, the first reset signal on path 409, the sync signal sync-1 on path 416, the sync signal sync-2 on path 421, the divided signal fdiv-1 on path 495-1, and the divided signal fdiv-2 on path 495-2 are shown.

[0073] The PLL 100 is in steady state prior to time t501, whether or not the input clock fref is available (as described below). Thus, prior to time t501, the select signal on path 451 is at a logic low level. Thus, the input clock fref shown has been selected as the output of MUX 405 on path 406. The divided signal fdiv-1 on path 495-1 and the divided signal fdiv-2 on path 495-2 are generated at their respective desired (programmed) rates. The divided signal fdiv-1 on path 495-1 and the divided signal fdiv-2 on path 495-2 are shown as being in phase with each other. Figure 4The internal clock generated by the internal clock generator 460, fint, is shown to be always on and available, and has the same frequency as the input clock fref. However, the internal clock fint on path 411 has a frequency relative to the input clock fref. Phase shift.

[0074] Between time t501 and time t503, the input (reference) clock fref on path 101 becomes unavailable. Once the clock failure is detected (at time t503), a component (not shown) inside PLL 100 forces PLL 100 to operate in hold mode. Alternatively, the input clock fref may not exist at all, so PLL 100 operates in hold mode at the start of operation (e.g., before time t501). In this case, since there is no last known valid state of the oscillator, the PLL uses an (internal) oscillator (not shown) to generate the PLL output fout. PLL 100 is shown operating in hold mode starting at time t503. From time t503, the input clock fref is indicated by the dashed section, used only to illustrate the phase of the input clock fref assuming it is available.

[0075] At time t503 (a finite time interval after the input clock fref fails), controller 450 detects a clock failure. Therefore, controller 450 generates a logic high level (selection signal) on path 451 starting at time t503. That is, starting at time t503, the internal clock fint is selected as the output of MUX405 on path 406.

[0076] At time t507, assume that PLL100 is reset by the signal received on path 471. "Reset" can include one or more of the following: a full-power cycle (power-down and power-up sequence) of the component containing PLL100, and a hard reset of the chip containing PLL100. From time t507, output generator 480 remains in the reset state. This time can be extended to a situation where this is the first wake-up of PLL100, and therefore, once the absence of the input clock fref is detected, the select signal on path 451 switches to logic high after this time.

[0077] Upon power-up, the PLL100 operates in hold mode as described above because the input clock fref on path 101 is unavailable. Furthermore, the internal clock fint on path 411 is selected as the output of the MUX405 on path 406.

[0078] At time t511, the PLL 100 generates a reset signal on path 409 (asynchronously) to release the output generator 480 from reset. The reset signal on path 409 is provided to the input (D) of flip-flop 415. The output (Q) of flip-flop 415 is a synchronization signal sync-1 on path 416 (synchronized with the rising edge El of the internal clock fintoccurring at time t513), as shown in FIG. 5B at time t513. The synchronization signal sync-1 on path 416 is forwarded to the input (D) of flip-flop 420. Thus, the output (Q) of flip-flop 420 is a synchronization signal sync-2 on path 421, as shown in FIG. 5B at time t515 (time t515 is the time of the rising edge Ol of the PLL output fouton path 131 immediately after the rising edge El of the internal clock finton path 411). Figure 5 Figure 5 The synchronization signal sync-2 on path 421 is forwarded to the input (D) of each flip-flop 430. Thus, the output (Q) of each flip-flop 430 is a synchronization signal on path 432, as shown in FIG. 5B at time t517 (time t517 is the time of the rising edge Ol of the PLL output fouton path 131 immediately after the rising edge El of the internal clock finton path 411).

[0079] Each flip-flop 430 receives the synchronization signal sync-2 on path 421 as input to the input (D) and generates a corresponding output (Q) on path 432 at time t517, which is synchronized with the rising edge 02 of the PLL output foutand follows the rising edge El of the internal clock finton path 411. In other words, the edge of each divided signal has a corresponding offset from the edge 02 of the PLL output foutand the edge of each divided signal is after the edge 02 of the PLL output fout, where the edge 02 follows (i.e., is a few clock cycles of the PLL output foutafter, for example, 1-2 clock cycles of the PLL output foutas described in the exemplary embodiment) the edge El of the internal clock finton path 411.

[0080] At time t517, when the output of flip-flop 430 is received on path 432, each delay block 435 delays the reset of the corresponding output generator 480 by a corresponding predetermined offset. For example, delay block 435-1 delays the release of the reset of output generator 480-1 by an offset (i.e., until time t523), while delay block 435-2 delays the release of the reset of output generator 480-2 by an offset (i.e., until time t525).

[0081] At time t523, delay block 435-1 generates a divider-reset signal on path 436-1 (not shown) to release counter 410-1 from reset. Thus, starting at time t523, counter 410-1 begins dividing the PLL output foutby the desired ratio (the ratio received on path 105-1). ​

[0082] At time t525, delay block 435-2 generates a divider reset signal on path 436-2 (not shown) to release counter 410-2 from reset. Therefore, starting at time t525, counter 410-2 begins dividing the PLL output fout by the desired ratio (the ratio received on path 105-2). As mentioned above, there may be a situation where the reference clock fref is initially unavailable. In this case, the PLL starts operating in hold mode. However, since there is no known valid state for the oscillator (generating the PLL output), the PLL operates using another (internal) oscillator to generate the PLL output fout. Therefore, even without a reference clock, the divider signal can be synchronized to the PLL output fout (generated based on another internal oscillator).

[0083] Once the reference clock fref becomes available, all divider signals are synchronized with the reference clock fref. This design is typically implemented in the form of nested or cascaded PLL architectures. It will be understood that aspects of the invention also provide divider signals with a fixed and known relative phase delay at each wake-up point in such scenarios.

[0084] According to another aspect of the invention, the output generators of multiple PLLs operating based on a common input (e.g., a reference clock fref) can also be synchronously released from reset, as will be referred to below. Figure 6 As described.

[0085] 7. Generate frequency division signals for multiple PLLs.

[0086] Figure 6 A block diagram illustrating the implementation details of generating a frequency-divided signal for a multi-PLL clock generation circuit 600 in an embodiment of the present invention is shown. Figure 6 This includes a synchronization block 610, PLLs 600-1 to 600-x, and flip-flops 620-1 to 620-x. Each PLL 600 is associated with a corresponding set of output generators 680. For example, PLL 600-1 is associated with output generators 680-1-1 to 680-1-A, PLL 600-2 is associated with output generators 680-2-1 to 680-2-B, and PLL 600-X is associated with output generators 680-X-1 to 680-XY.

[0087] Synchronization block 610 contains corresponding Figure 4 The components of blocks 405, 450, 460, and 415 are common to PLL600-1 through PLL 600-X. In other words, in Figure 6In the exemplary embodiment shown, there is only one instance of synchronization block 610 for PLL 600-1 to PLL 600-X. Synchronization block 610 is used to receive signals on path 609 and signal fref on path 601, and to generate a signal on path 616. The signal fref on path 601 corresponds to... Figure 4 The signal on path 101. Synchronization block 610 also generates an internal clock or pulse group fint (not shown). The signal on path 609 represents the common release-from-reset signal, which is asserted as being issued only when all PLLs are ready and generating the corresponding output clock.

[0088] Synchronization block 610 is used to synchronize the signal on path 609 with the signal fref on path 601 (if signal fref exists), or to synchronize the signal on path 609 with the internal clock fint (if signal fref does not exist). The selection of the signal fref or signal fint used for synchronization is determined by the equivalent of Figure 4 The MUX405 multiplexer (within synchronization block 610, but not in...) Figure 6 (As shown in the image) Execution.

[0089] Each PLL600 can be Figure 4 The PLL100, and has Figure 4 All components / blocks of the clock generation circuit 400, except for blocks 405, 450, 460, and 415. Each output generator 680 can be... Figure 4 The output generator 480. The trigger 620-1 is similar to... Figure 4 The operation is based on the 420 trigger, and for the sake of brevity, it will not be described again here.

[0090] Each PLL 600 shown receives the signal fref on path 601 and generates a corresponding PLL output fout on path 631. The signal on path 631 can be... Figure 4 The signal on path 131 is shown. As described above, as... Figure 6As shown, the signal on path 616 is common to all PLLs. Each PLL 600 synchronizes the signal on path 616 with the corresponding PLL output fout on each path 631 to generate a timing-re-timed signal on the corresponding path 621, and the uncertainty between PLLs is reduced to a few cycles of PLL output fout on each path 631. In one embodiment, the few cycles of PLL output fout are two PLL output fout cycles. As mentioned above, since the PLL output fout on path 631 is a very high-frequency signal, the relative uncertainty is very small. The signal on path 621 is used to release the corresponding counter (not shown) in the output generator 680 from reset. In this way, the output generators of multiple PLLs operating based on a common reference (signal fref or signal fint) can be synchronously released from reset.

[0091] In one embodiment, a controller outside circuit 600 reads the lock state of each PLL (indicating that the PLL has reached the aforementioned steady state) and sets the signal on path 609 to logic high only after all PLLs have reached steady state. In an alternative embodiment, such operation may be implemented by firmware stored in non-volatile memory within circuit 600.

[0092] In an alternative embodiment, Figure 6 The multi-PLL clock generation circuit 600 replicates... Figure 4 The clock generation circuit 400 is used to implement this, where the number of replications is the same as the number of PLLs in circuit 600. A common synchronization block 610 is not implemented. In this embodiment, each such replication circuit 400 can be ready and generate a corresponding output clock asynchronously relative to each other. Therefore, at each external reset (including first wake-up) indicator (e.g. Figure 4 Following an external reset on path 471, the signal fref on path 601, even if available, is temporarily blocked within each replication circuit 400 until all PLLs are ready and generating the corresponding output clock. Similarly, the internal clock fint of each replication circuit 400 is also blocked for such a duration. The blocking of signals fref and fint in each replication circuit 400 can be implemented in a known manner (e.g., by using switches in the input paths of the multiplexer).

[0093] In an alternative, the signal frefmay continue to be blocked (although available), and the divided down signals of all PLLs can be synchronized to the internal clock (or pulse group) fint, as described above. This is useful in at least some circumstances, for example, when it is desirable to synchronize the divided down signals between multiple PLLs to a common reference other than the signal fref. This can be accomplished by controlling the select signal of the equivalent MUX 405 in a known manner.

[0094] It can be appreciated that, since the individual PLLs wake up (initialize and reach steady state) in sequence (rather than all at once), blocking the signal frefand the signal finton the path 601 in each replica circuit 400 until all PLLs reach steady state, ensures that the relative alignment between the divided down signals on the different PLLs remains constant through the reset. Without this blocking, each PLL, once woken up, starts to produce the corresponding divided down signal, then the divided down signals from multiple PLLs would not start in synchronization with each other, but at different times.

[0095] The above technique ensures that for a multiple PLL system, the input reference clock (if present) can be blocked in-chip to simulate clock failure, and such a design can be used to ensure that the output generators are released together or with a known phase difference, even if the output generators are from different PLLs. This provides a unique use case, namely, even in the presence of an input reference clock, the divided down signals on the PLLs can be aligned or provided with a known relative delay. This is useful in situations where the PLLs are enabled in sequence (reach steady state), so that if the input reference clock is always present, then the output generators start producing the divided down signals as soon as the PLLs are enabled. In that scenario, the output generators would wait for the internally generated common reference to start the output dividers (counters).

[0096] The clock generation circuit 400, or the clock generation circuit 600, implemented as described above, can be incorporated into a larger device or system, described briefly below.

[0097] 8. System

[0098] Figure 7 A block diagram of an example system including PLLs implemented in accordance with aspects of the present application as described in detail above is shown. The illustrated system 700 includes a Synchronous Ethernet (SyncE) timing card 710 and SyncE timing cards 720 and line cards 1 through N, only a single line card 730 of which is shown for simplicity. The illustrated line card 730 includes a jitter attenuator PLL 740 and SyncE physical layer (PHY) transmitters 745-1 and 745-2.Figure 7 The components in the network 700 can operate in a manner consistent with the SyncE network standard. As is well known in the relevant art, SyncE is a PHY-based technique for achieving synchronization in packet-based Ethernet. The SyncE clock signal transmitted over the physical layer should be traceable to an external master clock (e.g., the SyncE clock signal comes from a timing card such as timing card 710 or timing card 720). Thus, the timing of Ethernet packets is re-set with respect to the master clock and the Ethernet packets are then transmitted in the physical layer. Thus, the timing of data (e.g., packets on path 731 and path 741) is re-set and sent without any timestamp information recorded in the packets. The packets can be generated by respective applications, such as Internet Protocol Television (IPTV), Voice over Internet Protocol (VoIP), etc.

[0099] Thus, line card 730 receives the packets on path 731 and path 741 and forwards the respective packets on output 746 and output 747 after the timing of the packets is re-set (synchronized) by the master clock.

[0100] The master clock clock-1 711 is generated by timing card 710. Timing card 720 generates a redundant clock clock-2 721 that will be used by line card 730 and line card 750 when the master clock clock-1 711 fails. The master clock 711 and the redundant clock 721 are provided to each of line card 730 and line card 750 via a backplane (represented by reference numeral 770).

[0101] In the line card 730, the jitter attenuator PLL 740 can be implemented as the clock generation circuit 400 described in detail above and receives the clock 711 and the clock 721, with the outputs of the pair of output generators connected to the Sync EPHY transmitter 745-1 and the Sync EPHY transmitter 745-2, respectively. The PLL 740 generates an output clock 771 and an output clock 781 that are used to synchronize (re-set timing) the data packets received on the paths 731 and 741, respectively, and forward the re-timed data packets on the paths 746 and 747. Any specified relative phase difference between the outputs on the paths 746 and 747 can be repeatedly maintained in the reset of the line card 730, even when the clocks 711, 721 become unavailable. Another example is the case of a data converter array, such that the Sync EPHY transmitter 745-1 and the Sync EPHY transmitter 745-2 are two data converters that require the clocks to have a similar relative phase difference.

[0102] 9. Conclusion

[0103] Throughout this specification, reference has been made to "one embodiment" or "an embodiment" or similar language. This should not be construed as a negative statement as used herein, but merely an acknowledgement of an aspect of no more than one implementation. Further, throughout the specification, periods after initials or surnames have been deleted as they should only appear in direct quotations if that was the original format. Throughout the specification, the terms "comprising," "including," containing," "having" or "encompassing" and the like shall be understood to be taken in their broadest possible context to mean that the named step or steps, feature or features, component or components, integer or integers, etc. are included.

[0104] While the application has been described above with reference to various embodiments, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the application should not be limited by any of the above described embodiments, but should be defined in accordance with the following claims and their equivalents. Figure 1 、 Figure 4 、 Figure 6 and Figure 7 In the illustrations of FIGS. 1-6, the illustrated ends / nodes have direct connections to (i.e., are "connected to") various other ends, but it should be understood that additional components (appropriate to the particular environment) can also be present in the paths, and thus the connections can be considered to be "electrically coupled" to the same connection ends.

[0105] While various embodiments of the application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the application should not be limited by any of the above described embodiments, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A method for generating a frequency-divided signal, comprising: Use a phase-locked loop (PLL) to generate a PLL output; The frequency output by the PLL is a desired multiple of the frequency of the reference clock; Receive the corresponding desired time offset for each of the multiple frequency-divided signals; as well as The PLL output is divided by a divisor to generate the corresponding frequency-divided signals of the plurality of frequency-divided signals, wherein each frequency-divided signal is offset relative to a common reference by at least the desired time offset. Wherein, when the reference clock is available, the timing of the common reference is set relative to the reference clock; when the reference clock is unavailable, the timing of the common reference is set relative to the time reference signal; The time reference signal is generated outside the reference clock. The frequency division includes counting the number of clock cycles output by the PLL starting from the first moment after receiving the frequency divider reset signal. The generation of the frequency divider reset signal includes: Under the control of the selection signal, one of the reference clock and the time reference signal is selected as the common reference; Synchronize the first reset signal with the common reference to generate a first synchronization signal; Synchronize the first synchronization signal with the PLL output to generate a second synchronization signal; and The second synchronization signal is delayed by the associated desired time offset to set the first moment.

2. The method according to claim 1, characterized in that, The first edge of each frequency-divided signal has the associated desired time offset from the first edge of the PLL output, and the first edge of each frequency-divided signal is located after the first edge of the PLL output; when the reference clock is available, the first edge of the PLL output follows the first edge of the reference clock; as well as Wherein, the second edge of each frequency division signal has the associated desired time offset from the second edge of the PLL output and the second edge of each frequency division signal is located after the second edge of the PLL output; when the reference clock is unavailable, the second edge of the PLL output follows the second edge of the time reference signal.

3. The method according to claim 2, characterized in that, When the reference clock is unavailable, the PLL operates in hold mode, wherein the hold mode requires the PLL to continue generating PLL outputs without using the reference clock. The first reset signal is generated when the PLL receives an external reset signal after the PLL has been operating in the holding mode for at least a certain period of time.

4. The method according to claim 3, characterized in that, Each frequency division signal is offset relative to the common reference by the associated desired time offset plus a number of cycles of the PLL output.

5. A clock generating circuit for generating a frequency division signal; The clock generation circuit includes: A phase-locked loop (PLL) is used to generate a PLL output; the frequency of the PLL output is a desired multiple of the frequency of the reference clock. A frequency divider circuit is used to divide the PLL output by a divisor to generate a corresponding frequency-divided signal among a plurality of frequency-divided signals, wherein the corresponding frequency-divided signal is at least related to a desired time offset relative to a common reference offset. The frequency divider circuit includes a counter for counting the number of clock cycles of the PLL output from a first moment after receiving a frequency divider reset signal to generate the frequency-divided signal; and A synchronization circuit is used to generate the frequency divider reset signal at the first moment, the synchronization circuit comprising: A multiplexer, used to select one of the reference clock and the time reference signal as the common reference under the control of a selection signal; A first trigger is configured to synchronize a first reset signal with the common reference to generate a first synchronization signal; A second trigger is configured to synchronize the first synchronization signal with the PLL output to generate a second synchronization signal; and A delay block is used to delay the second synchronization signal by the associated desired time offset to set the first moment. Wherein, when the reference clock is available, the timing of the common reference is set relative to the reference clock; when the reference clock is unavailable, the timing of the common reference is set relative to the time reference signal; The time reference signal is generated outside the reference clock.

6. The clock generating circuit according to claim 5, characterized in that, The first edge of each frequency-divided signal has the associated desired time offset from the first edge of the PLL output, and the first edge of each frequency-divided signal is located after the first edge of the PLL output; when the reference clock is available, the first edge of the PLL output follows the first edge of the reference clock; as well as Wherein, the second edge of each frequency division signal has the associated desired time offset from the second edge of the PLL output and the second edge of each frequency division signal is located after the second edge of the PLL output; when the reference clock is unavailable, the second edge of the PLL output follows the second edge of the time reference signal.

7. The clock generating circuit according to claim 6, characterized in that, When the reference clock is unavailable, the PLL operates in hold mode, wherein the hold mode requires the PLL to continue generating PLL outputs without using the reference clock. The first reset signal is generated when the PLL receives an external reset signal after the PLL has been operating in the holding mode for at least a certain period of time.

8. The clock generating circuit according to claim 7, characterized in that, The clock generation circuit also includes an internal clock generator for generating an internal clock signal that serves as the time reference signal.

9. The clock generating circuit according to claim 6, characterized in that, Each frequency division signal is offset relative to the common reference by the associated desired time offset plus a number of cycles of the PLL output.

10. A clock generation circuit for generating a plurality of frequency-divided signals having a predetermined relative phase delay, the clock generation circuit comprising: Multiple phase-locked loops (PLLs), each PLL generating a corresponding PLL output and a corresponding subset of the frequency-divided signals from the multiple frequency-divided signals; Wherein, each of the plurality of frequency-divided signals is at least associated with a predetermined phase delay relative to the reference clock offset; The external reset signal is used to reset the plurality of PLLs, wherein the reset initializes each PLL and then reaches a steady state; wherein all the plurality of PLLs reach the steady state within a certain period of time after the external reset signal. The reference clock is blocked for a specified period of time.

11. The clock generating circuit according to claim 10, characterized in that, The clock generation circuit also includes: A synchronization block is used to synchronize the first reset signal with the reference clock to generate a first synchronization signal. The first reset signal is asserted at the end of the specified time period.

12. The clock generating circuit according to claim 11, characterized in that, The clock generation circuit also includes: Multiple triggers, corresponding to each of the multiple PLLs; and Multiple output generator blocks, corresponding to each of the multiple PLLs. Each of the plurality of triggers is used to synchronize the first synchronization signal with the corresponding PLL output to generate a corresponding second synchronization signal. Each of the plurality of output generator blocks delays the second synchronization signal by the relevant predetermined phase delay and divides the corresponding PLL output by the corresponding divisor to generate the corresponding frequency division signal among the plurality of frequency division signals.

13. The clock generating circuit according to claim 11, characterized in that, Even when the reference clock is available, the time reference signal can be used for synchronization by continuing to block the reference clock after the specified period of time.

14. The clock generating circuit according to claim 13, characterized in that, The synchronization block includes an internal clock generator to generate an internal clock signal that serves as the time reference signal.

15. The clock generating circuit according to claim 14, characterized in that, Each frequency division signal is offset relative to the reference clock or the time reference signal by the associated predetermined phase delay plus a number of cycles of the corresponding PLL output.

Images