Low voltage feedback comparator

Abstract

The application provides a low potential feedback comparator, comprising a preamplification stage circuit for amplifying first and second input signals; a comparator circuit for receiving the first and second input signals for voltage comparison, thereby outputting first and second output signals; a feedback module for receiving disturbance signals of the first and second output signals, generating first and second feedback signals to feedback to the first and second output signals, so that the potential of the first and second output signals originally in L or X state is pulled down. The comparator of the application inputs the differential output of the low potential feedback comparator into the feedback module and outputs low potential feedback to the differential output end of the low potential feedback comparator. When there is a large enough positive or negative voltage disturbance, the feedback module will generate an output response and pull down the potential of the differential output end originally in X or L state, thereby stabilizing the state of the comparator.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a low potential feedback comparator. BACKGROUND

[0002] The comparator is an important component in modern electronic systems, and is a basic conversion unit of analog signals and digital signals, which can be used as a 1-bit analog-to-digital converter. It is mostly operated in an open-loop state, and internal positive feedback is often used to obtain greater gain or hysteresis effect.

[0003] The comparator is widely used in the conversion process of analog signals to digital signals, and POR, VDT, ADC and other circuits often cannot do without the comparator. In the power management module, the power supply voltage is generally sampled, and the sampled signal is input to the differential input end of the comparator for comparison to determine the current state of the circuit, and then the power management of the entire circuit is performed. However, when the comparator is disturbed by environmental noise, it is extremely likely to produce an incorrect output, which is particularly evident in high-precision applications, which can reset the entire circuit system.

[0004] Figure 1 and Figure 2 is a high-gain open-loop comparator structure of P-type and N-type differential pairs. High-precision comparators are often composed of 2-4 stages of high-gain open-loop comparators. Due to the differential input and differential output structure, external noise input to the comparator will be suppressed and will not cause incorrect output. However, the interference of the external environment on the internal nodes of the comparator cannot be ignored, and in Figure 1 and Figure 2 , any node of A and B is disturbed, which can cause incorrect response of the comparator. In the entire high-precision comparator, the first stage of high-gain open-loop comparators is most susceptible to external noise and is most likely to produce incorrect response.

[0005] Figure 3 is a structure diagram of a high-precision comparator composed of three stages of high-gain open-loop comparators. Figure 4 is Figure 3 a response diagram of the input INP, INN and the output VOUTP, VOUTN of stage1 (the first stage comparator) and the final output VOUT of the high-precision comparator in normal operation.

[0006] When the comparator is operating normally, the smaller of VOUTN and VOUTP at the stable time is defined as the L state, and the larger one is defined as the H state, and the non-stable state is defined as the X state. When the comparator is operating normally, the following states may occur: ① VOUTN is in the H state, and VOUTP is in the X or L state; ② VOUTN is in the L state, and VOUTP is in the X or H state; ③ VOUTN and VOUTP are both in the X state;

[0007] Figure 3 In the prior art, only a small OD=INP-INN is needed to obtain the response of VOUT, but the differential output of the high-gain open-loop comparator of stage 1 is small, and is particularly susceptible to external interference to generate false responses.

[0008] Figure 5 In the prior art, VOUTN is subjected to a large positive voltage interference at t1, resulting in a false response of VOUT for a time Terror.

[0009] Figure 6 In the prior art, VOUTP is subjected to a large negative voltage interference at t1, resulting in a false response of VOUT for a time Terror.

[0010] To solve the above problems, a new low-potential feedback comparator needs to be proposed. SUMMARY

[0011] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a low-potential feedback comparator for solving the problem that in the prior art, when the comparator is normally working, the smaller of VOUTN and VOUTP at the stable time is defined as the L state, and the larger one is defined as the H state, and under non-stable conditions, it is defined as the X state. When the comparator is normally working, the differential output of the high-gain open-loop comparator of stage 1 is small, and is particularly susceptible to external interference to generate false responses.

[0012] To achieve the above-mentioned purposes and other related purposes, the present application provides a low-potential feedback comparator, comprising:

[0013] A preamplification stage circuit, which is used to amplify the first and second input signals;

[0014] Preferably, the preamplification stage circuit is a differential amplification circuit.

[0015] A comparator circuit, which is used to receive the first and second input signals for voltage comparison, thereby outputting the first and second output signals;

[0016] A feedback module, which is used to receive the disturbance signals of the first and second output signals, and the disturbance signals usually include positive voltage disturbances and negative voltage disturbances, and the feedback module generates the first and second feedback signals to feedback to the first and second output signals, so that the potential of the first and second output signals originally in the L or X state is pulled down.

[0017] Preferably, the comparator is a P-type differential pair, which is used for the positive voltage disturbances and the negative voltage disturbances.

[0018] Preferably, the comparator is a P-type differential pair for the positive voltage perturbation or the negative voltage perturbation.

[0019] Preferably, the pre-amplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS;

[0020] The comparator circuit comprises a sixth NMOS and a seventh NMOS; wherein the source of the first PMOS is connected to a power voltage, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS;

[0021] The drain of the fourth NMOS is shorted to the gate of the fourth NMOS, the gate of the fourth NMOS is connected to the gate of the sixth NMOS, the drain of the fifth NMOS is shorted to the gate of the fifth NMOS, the gate of the fifth NMOS is connected to the gate of the seventh NMOS, and the sources of the fourth NMOS, the fifth NMOS, the sixth NMOS and the seventh NMOS are connected in sequence and connected to a power ground;

[0022] The drain of the sixth NMOS is connected to the drain of the fifth NMOS, the drain of the third PMOS and a second input end of a feedback module respectively, the second output end of the feedback module is connected to the drain of the fifth NMOS and the drain of the third PMOS respectively; the drain of the seventh NMOS is connected to the drain of the fourth NMOS, the drain of the second PMOS and a first input end of the feedback module respectively, and the first output end of the feedback module is connected to the drain of the fourth NMOS and the drain of the second PMOS respectively.

[0023] Preferably, the feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein,

[0024] The sources of the eighth PMOS, the ninth PMOS and the tenth PMOS are connected to a power voltage;

[0025] The gate of the eighth PMOS is shorted to the drain of the eighth PMOS, the drain of the eighth PMOS is connected to a bias current, the gate of the eighth PMOS is connected to the gate of the first PMOS, the gates of the ninth PMOS and the tenth PMOS are connected to a bias voltage;

[0026] The drain of the ninth PMOS is connected with the drain of the eleventh NMOS, the drain of the tenth PMOS is connected with the drain of the twelfth NMOS, the drain of the thirteenth NMOS is connected with the drain of the sixth NMOS and the drain of the fifth NMOS and the drain of the third PMOS respectively, the drain of the fourteenth NMOS is connected with the drain of the seventh NMOS and the drain of the fourth NMOS and the drain of the second PMOS respectively;

[0027] The source of the eleventh NMOS, the twelfth NMOS, the thirteenth NMOS and the fourteenth NMOS are connected with the power supply ground respectively;

[0028] The gate of the eleventh NMOS is connected with the drain of the second PMOS and the drain of the fourth NMOS, the gate of the twelfth NMOS is connected with the drain of the third PMOS and the drain of the fifth NMOS;

[0029] The first input end of the logic module is connected with the drain of the ninth PMOS and the drain of the eleventh NMOS, the first output end of the logic module is connected with the gate of the thirteenth NMOS, the second input end of the logic module is connected with the drain of the tenth PMOS and the drain of the twelfth NMOS, the second output end of the logic module is connected with the gate of the fourteenth NMOS.

[0030] Preferably, the preamplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS;

[0031] The comparator circuit comprises a sixth NMOS and a seventh NMOS; wherein,

[0032] The source of the first PMOS is connected with the power supply voltage, the gate of the first PMOS is connected with the bias voltage, the gate of the second PMOS is connected with the first input signal, the gate of the third PMOS is connected with the second input signal, the drain of the first PMOS is connected with the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected with the drain of the fourth NMOS, the drain of the third PMOS is connected with the drain of the fifth NMOS;

[0033] The drain of the fourth NMOS is connected with the gate of the fourth NMOS, the gate of the fourth NMOS is connected with the gate of the sixth NMOS, the drain of the fifth NMOS is connected with the gate of the fifth NMOS, the gate of the fifth NMOS is connected with the gate of the seventh NMOS, the source of the fourth NMOS, the fifth NMOS, the sixth NMOS and the seventh NMOS are connected in sequence and connected with the power supply ground;

[0034] The drain of the sixth NMOS is connected with the drain of the fifth NMOS, the drain of the third PMOS and the second input end of the feedback module respectively, and the second output end of the feedback module is connected with the drain of the fifth NMOS and the drain of the third PMOS respectively; the drain of the seventh NMOS is connected with the drain of the fourth NMOS, the drain of the second PMOS and the first input end of the feedback module respectively, and the first output end of the feedback module is connected with the drain of the fourth NMOS and the drain of the second PMOS respectively.

[0035] Preferably, the feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, a fifteenth NMOS, a sixteenth NMOS and a first and a second logic module; wherein,

[0036] The first and the second logic modules are used for different types of voltage disturbance.

[0037] The source of the eighth PMOS, the ninth PMOS and the tenth PMOS is connected with the power supply voltage.

[0038] The gate of the eighth PMOS is short-circuited with the drain, the drain of the eighth PMOS is connected with the bias current, the gate of the eighth PMOS is connected with the gate of the first PMOS, the gate of the ninth PMOS and the gate of the tenth PMOS are connected with the bias voltage.

[0039] The drain of the ninth PMOS is connected with the drain of the eleventh NMOS, the drain of the tenth PMOS is connected with the drain of the twelfth NMOS, the drain of the thirteenth NMOS is connected with the drain of the sixth NMOS and the drain of the fifth NMOS and the drain of the third PMOS respectively, the drain of the fourteenth NMOS is connected with the drain of the seventh NMOS and the drain of the fourth NMOS and the drain of the second PMOS respectively.

[0040] The source of the eleventh NMOS, the twelfth NMOS, the thirteenth NMOS and the fourteenth NMOS is connected with the power supply ground.

[0041] The gate of the eleventh NMOS is connected with the drain of the second PMOS and the drain of the fourth NMOS, and the gate of the twelfth NMOS is connected with the drain of the third PMOS and the drain of the fifth NMOS.

[0042] The drain of the fifteenth NMOS is connected between the drain of the second PMOS and the drain of the fourth NMOS, and the source of the fifteenth NMOS is connected with the ground.

[0043] The drain of the sixteenth NMOS is connected between the drain of the third PMOS and the drain of the fifth NMOS, and the source of the sixteenth NMOS is connected with the ground.

[0044] The drain of the ninth PMOS and the drain of the eleventh NMOS are connected with a first input terminal of the first and second logic modules; the drain of the tenth PMOS and the drain of the twelfth NMOS are connected with a second input terminal of the first and second logic modules; the gate of the thirteenth NMOS is connected with a first output terminal of the first logic module, the gate of the fourteenth NMOS is connected with a second output terminal of the first logic module, the gate of the fifteenth NMOS is connected with a second output terminal of the second logic module, and the gate of the sixteenth NMOS is connected with a first output terminal of the second logic module.

[0045] Preferably, the feedback module is an N-type differential pair, which is used for positive voltage perturbation or negative voltage perturbation.

[0046] Preferably, the pre-amplification stage circuit comprises a seventh NMOS, a fifth NMOS, a sixth NMOS, a first PMOS and a second PMOS; the comparator circuit comprises a third PMOS and a fourth PMOS; wherein,

[0047] The source of the seventh NMOS is connected with a power supply ground, the gate of the seventh NMOS is connected with a bias voltage, the gate of the fifth NMOS is connected with a first input signal, the gate of the sixth NMOS is connected with a second input signal, the drain of the seventh NMOS is connected with the source of the fifth NMOS and the source of the sixth NMOS respectively, the drain of the fifth NMOS is connected with the drain of the first PMOS, and the drain of the sixth NMOS is connected with the drain of the second PMOS;

[0048] The drain of the first PMOS is short-circuited with the gate of the first PMOS, the gate of the first PMOS is connected with the gate of the third PMOS, the drain of the second PMOS is short-circuited with the gate of the second PMOS, the gate of the second PMOS is connected with the gate of the fourth PMOS; the sources of the first PMOS, the second PMOS, the third PMOS and the fourth PMOS are connected in sequence and connected with a power supply voltage;

[0049] The drain of the third PMOS is connected with the drain of the second PMOS, the drain of the sixth NMOS and a second input terminal of the feedback module respectively, the second output terminal of the feedback module is connected with the drain of the second PMOS and the drain of the sixth NMOS respectively; the drain of the fourth PMOS is connected with the drain of the first PMOS, the drain of the fifth NMOS and a first input terminal of the feedback module respectively, and the first output terminal of the feedback module is connected with the drain of the first PMOS and the drain of the fifth NMOS respectively.

[0050] Preferably, the feedback module comprises an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein,

[0051] The sources of the eighth NMOS, the ninth NMOS and the tenth NMOS are connected with a power supply ground;

[0052] the gate of the eighth NMOS is shorted with the drain of the eighth NMOS, the drain of the eighth NMOS is connected with a bias current, the gate of the eighth NMOS is connected with the gate of the seventh NMOS, the gates of the ninth NMOS and the tenth NMOS are connected with a bias voltage;

[0053] the drain of the ninth NMOS is connected with the drain of the eleventh PMOS, the drain of the tenth NMOS is connected with the drain of the twelfth PMOS, the drain of the thirteenth NMOS is connected with the drain of the third PMOS and the drain of the second PMOS and the drain of the sixth NMOS respectively, the drain of the fourteenth NMOS is connected with the drain of the fourth PMOS and the drain of the first PMOS and the drain of the fifth NMOS respectively;

[0054] the sources of the eleventh PMOS and the twelfth PMOS are connected with a power supply voltage, the sources of the thirteenth NMOS and the fourteenth NMOS are connected with a power supply ground;

[0055] the gate of the eleventh PMOS is connected with the drain of the fifth NMOS and the drain of the first PMOS, the gate of the twelfth PMOS is connected with the drain of the sixth NMOS and the drain of the second PMOS;

[0056] the second input end of the logic module is connected with the drains of the tenth NMOS and the twelfth PMOS, the second output end of the logic module is connected with the gate of the fourteenth NMOS, the first input end of the logic module is connected with the drains of the ninth NMOS and the eleventh PMOS, and the first output end of the logic module is connected with the gate of the thirteenth NMOS.

[0057] Preferably, the comparator is an N-type differential pair, which is used for the positive voltage perturbation and the negative voltage perturbation.

[0058] Preferably, the logic module is used for the positive voltage perturbation, which comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NOR gate, a fifth inverter, a sixth inverter, a seventh inverter, a first NAND gate, a second NAND gate, a second NOR gate, a third NOR gate; wherein,

[0059] the input end of the first inverter serves as the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the first NAND gate, and the output end of the first NAND gate is connected with the second input end of the second NOR gate;

[0060] The input end of the second inverter is the first input end of the logic module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the second input end of the second NAND gate, and the output end of the second NAND gate is connected with the first input end of the third NOR gate;

[0061] The first input end of the first NOR gate is connected with the output end of the third inverter, the second input end of the first NOR gate is connected with the output end of the fourth inverter, the output end of the first NOR gate is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the first input end of the second NOR gate and the second input end of the third NOR gate respectively, the second input end of the first NAND gate is connected between the output end of the second NAND gate and the first input end of the third NOR gate, and the first input end of the second NAND gate is connected between the output end of the first NAND gate and the second input end of the second NOR gate.

[0062] The output end of the third NOR gate is the first output end of the logic module, and the output end of the second NOR gate is the second output end of the logic module.

[0063] Preferably, the logic module is used for the negative voltage disturbance, and comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a first NOR gate and a second NOR gate.

[0064] The input end of the first inverter is the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the second NAND gate, and the output end of the second NAND gate is connected with the second input end of the first NOR gate.

[0065] The input end of the second inverter is the first input end of the logic module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the third NAND gate, and the output end of the third NAND gate is connected with the first input end of the second NOR gate.

[0066] The first input end of the first NAND gate is connected between the output end of the third inverter and the first input end of the second NAND gate, the second input end of the first NAND gate is connected between the output end of the fourth inverter and the second input end of the third NAND gate, and the output end of the first NAND gate is connected with the first input end of the first NOR gate and the second input end of the second NOR gate respectively.

[0067] The second input end of the second NAND gate is connected between the output end of the third NAND gate and the first input end of the second NOR gate, and the first input end of the third NAND gate is connected between the output end of the second NAND gate and the second input end of the first NOR gate.

[0068] The output of the first NOR gate serves as the first output of the logic module, and the output of the second NOR gate serves as the second output of the logic module.

[0069] As described above, the low-potential feedback comparator of the present invention has the following beneficial effects:

[0070] The comparator of this invention inputs the differential output of a low-potential feedback comparator to a feedback module and outputs a low-potential feedback back to the differential output of the low-potential feedback comparator. When a sufficiently large positive or negative voltage disturbance exists, the feedback module generates an output response and pulls down the potential of the differential output terminal, which was originally in the X or L state, thus stabilizing the comparator's state. This highly reliable design method incurs a small cost but effectively avoids erroneous responses caused by external positive and negative voltage interference to the high-precision comparator. This allows the high-precision comparator to be used in more complex operating environments, improving the reliability of the entire circuit system. Attached Figure Description

[0071] Figure 1 The diagram shows a high-gain open-loop comparator for a P-type differential pair in the prior art.

[0072] Figure 2 The diagram shows a high-gain open-loop comparator for an N-type differential pair in the prior art.

[0073] Figure 3 The diagram shows a high-precision comparator structure using a three-stage high-gain open-loop comparator, which is an application of existing technology.

[0074] Figure 4 The diagram shows the response of a high-precision comparator in the prior art operating normally.

[0075] Figure 5 Displayed as existing technology Figure 3 A schematic diagram of the first-stage high-gain open-loop comparator subjected to a forward voltage disturbance;

[0076] Figure 6 Displayed as existing technology Figure 3 A schematic diagram of the first-stage high-gain open-loop comparator subjected to a negative voltage disturbance;

[0077] Figure 7 The diagram shows a comparator structure for low-potential feedback of a P-type differential pair for positive or negative voltage disturbances according to the present invention.

[0078] Figure 8 The diagram shows a comparator structure for low-potential feedback of an N-type differential pair for positive or negative voltage disturbances according to the present invention.

[0079] Figure 9The diagram shows a detailed structural schematic of the comparator with low-potential feedback for the P-type differential pair of the present invention.

[0080] Figure 10 The diagram shows a detailed structural schematic of the comparator with low-potential feedback for the N-type differential pair of the present invention.

[0081] Figure 11 The diagram shown is a schematic diagram of a logic module of the present invention;

[0082] Figure 12 This is a schematic diagram of another logic module of the present invention;

[0083] Figure 13 The diagram shows a comparator structure for low-potential feedback of a P-type differential pair used for both positive and negative voltage disturbances, as presented in this invention.

[0084] Figure 14 Displayed as Figure 9 The diagram shows the first-stage high-gain comparator subjected to a forward voltage disturbance.

[0085] Figure 15 Displayed as Figure 9 The diagram shows the first-stage high-gain comparator subjected to a negative voltage disturbance. Detailed Implementation

[0086] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] Example 1

[0088] Please see Figure 7 This invention provides a low-potential feedback comparator, which is a P-type differential pair used for positive or negative voltage disturbances, comprising:

[0089] The preamplifier stage circuit is used to amplify the first and second input signals.

[0090] In an embodiment of the present invention, the preamplifier stage circuit is a differential amplifier circuit.

[0091] A comparator circuit is used to receive the first and second input signals, compare their voltages, and then output the first and second output signals.

[0092] In the embodiment of the present application, the pre-amplification stage circuit comprises a first PMOS PM1, a second PMOS PM2, a third PMOS PM3, a fourth NMOS PM4 and a fifth NMOS PM5;

[0093] The comparator circuit comprises a sixth NMOS NM6 and a seventh NMOS NM7; wherein,

[0094] The source of the first PMOS PM1 is connected to a power voltage VDD, the gate of the first PMOS PM1 is connected to a bias voltage, the gate of the second PMOS PM2 is connected to a first input signal, the gate of the third PMOS PM3 is connected to a second input signal, the drain of the first PMOS PM1 is connected to the source of the second PMOS PM2 and the source of the third PMOS PM3 respectively, the drain of the second PMOS PM2 is connected to the drain of the fourth NMOS PM4, and the drain of the third PMOS PM3 is connected to the drain of the fifth NMOS PM5;

[0095] The drain of the fourth NMOS PM4 is shorted to the gate, the gate of the fourth NMOS PM4 is connected to the gate of the sixth NMOS NM6, the drain of the fifth NMOS PM5 is shorted to the gate, the gate of the fifth NMOS PM5 is connected to the gate of the seventh NMOS NM7, and the sources of the fourth NMOS PM4, the fifth NMOS PM5, the sixth NMOS NM6 and the seventh NMOS NM7 are connected in sequence and connected to a power ground GND;

[0096] The drain of the sixth NMOS NM6 is connected to the drain of the fifth NMOS PM5, the drain of the third PMOS PM3 and a second input terminal of a feedback module Reliable respectively, the second output terminal of the feedback module Reliable is connected to the drain of the fifth NMOS PM5 and the drain of the third PMOS PM3 respectively; the drain of the seventh NMOS NM7 is connected to the drain of the fourth NMOS PM4, the drain of the second PMOS PM2 and a first input terminal of the feedback module Reliable respectively, and the first output terminal of the feedback module Reliable is connected to the drain of the fourth NMOS PM4 and the drain of the second PMOS PM2 respectively.

[0097] The feedback module Reliable is used for receiving a disturbance signal of the first and second output signals, the disturbance signal usually comprises a positive voltage disturbance and a negative voltage disturbance, and the feedback module Reliable generates first and second feedback signals to feed back to the first and second output signals, so that the potential of the first and second output signals originally in L or X state is pulled down.

[0098] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is interfered by a positive voltage, and changes from the L or X state to the X or H state, the disturbance is input from the first and second input terminals of the feedback module Reliable and a low potential is output from the first or second output terminal to the first or second output signal, so as to pull down the potential of the first or second output signal originally in the L or X state, thereby stabilizing the working state of the comparator.

[0099] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is interfered by a positive voltage, and changes from the L or X state to the X or H state, the disturbance is input from the first and second input terminals of the feedback module Reliable and a low potential is output from the first or second output terminal to the first or second output signal, so as to pull down the potential of the first or second output signal originally in the L or X state, thereby stabilizing the working state of the comparator.

[0100] In the embodiment of the present application, referring to Figure 9 , the feedback module Reliable comprises an eighth PMOS PM8, a ninth PMOS PM9, a tenth PMOS PM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14, and a logic module Logic; wherein,

[0101] The sources of the eighth PMOS PM8, the ninth PMOS PM9, and the tenth PMOS PM10 are connected to the power supply voltage VDD;

[0102] The gate of the eighth PMOS PM8 is short-circuited with the drain of the eighth PMOS PM8, the drain of the eighth PMOS PM8 is connected to the bias voltage, the gate of the eighth PMOS PM8 is connected to the gate of the first PMOS, the gates of the ninth PMOS PM9 and the tenth PMOS PM10 are connected to the bias voltage;

[0103] The drain of the ninth PMOS PM9 is connected to the drain of the eleventh NMOS NM11, the drain of the tenth PMOS PM10 is connected to the drain of the twelfth NMOS NM12, the drain of the thirteenth NMOS NM13 is connected to the drain of the sixth NMOS NM6 and the drain of the fifth NMOS NM5 and the drain of the third PMOS PM3, respectively, and the drain of the fourteenth NMOS NM14 is connected to the drain of the seventh NMOS NM7 and the drain of the fourth NMOS NM4 and the drain of the second PMOS PM2, respectively;

[0104] The sources of the eleventh NMOS NM11, the twelfth NMOS NM12, the thirteenth NMOS NM13, and the fourteenth NMOS NM14 are connected to the ground GND;

[0105] The gate of the eleventh NMOS NM11 is connected with the drain of the second PMOS PM2 and the fourth NMOS NM4, and the gate of the twelfth NMOS NM12 is connected with the drain of the third PMOS PM3 and the fifth NMOS NM5;

[0106] The first input end of the logic module Logic is connected with the drain of the ninth PMOS PM9 and the eleventh NMOS NM11, and the first output end of the logic module Logic is connected with the gate of the thirteenth NMOS NM13; the second input end of the logic module Logic is connected with the drain of the tenth PMOS PM10 and the twelfth NMOS NM12, and the second output end of the logic module Logic is connected with the gate of the fourteenth NMOS NM14.

[0107] In the embodiment of the present application, please refer to Figure 11 The logic module Logic is used for forward voltage disturbance, which comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a fifth inverter I6, a sixth inverter I7, a seventh inverter I8, a first NOR gate I9, a second NOR gate I10, a second NAND gate I11, and a third NAND gate I12; wherein the input end of the first inverter I1 is used as the second input end of the logic module Logic, and is used for acquiring the amplified second output signal VOUTP', the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the sixth inverter I7, the output end of the sixth inverter I7 is connected with the first input end of the first NOR gate I9, and the output end of the first NOR gate I9 is connected with the second input end of the second NAND gate I11;

[0108] The input end of the second inverter I2 is used as the first input end of the logic module Logic, and is used for acquiring the amplified first output signal VOUTN', the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the seventh inverter I8, the output end of the seventh inverter I8 is connected with the second input end of the second NOR gate I10, and the output end of the second NOR gate I10 is connected with the first input end of the third NAND gate I12;

[0109] The first input end of the first NOR gate I5 is connected with the output end of the third inverter I3, the second input end of the first NOR gate I5 is connected with the output end of the fourth inverter I4, the output end of the first NOR gate I5 is connected with the input end of the fifth inverter I6, the output end of the fifth inverter I6 is respectively connected with the first input end of the second NOR gate I11 and the second input end of the third NOR gate I12, the second input end of the first NAND gate I9 is connected between the output end of the second NAND gate I10 and the first input end of the third NOR gate I12, the first input end of the second NAND gate I10 is connected between the output end of the first NAND gate I9 and the second input end of the second NOR gate I11;

[0110] The output end of the third NOR gate I12 is the first output end of the logic module Logic, and the output end of the second NOR gate I11 is the second output end of the logic module Logic.

[0111] In the embodiment of the present application, referring to Figure 12 The logic module Logic is used for negative voltage disturbance, and comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a second NAND gate I6, a third NAND gate I7, a first NOR gate I8 and a second NOR gate I9; wherein,

[0112] The input end of the first inverter I1 is the second input end of the logic module Logic, the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the second NAND gate I6, and the output end of the second NAND gate I6 is connected with the second input end of the first NOR gate I8;

[0113] The input end of the second inverter I2 is the first input end of the logic module Logic, the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the third NAND gate I7, and the output end of the third NAND gate I7 is connected with the first input end of the second NOR gate I9;

[0114] The first input end of the first NAND gate I5 is connected between the output end of the third inverter I3 and the first input end of the second NAND gate I6, the second input end of the first NAND gate I5 is connected between the output end of the fourth inverter I4 and the second input end of the third NAND gate I7, and the output end of the first NAND gate I5 is respectively connected with the first input end of the first NOR gate I8 and the second input end of the second NOR gate I9;

[0115] The second input end of the second NAND gate I6 is connected between the output end of the third NAND gate I7 and the first input end of the second NOR gate I9, and the first input end of the third NAND gate I7 is connected between the output end of the second NAND gate I6 and the second input end of the first NOR gate I8.

[0116] The output end of the first NOR gate I8 is the first output end of the logic module Logic, and the output end of the second NOR gate I9 is the second output end of the logic module Logic.

[0117] Specifically, the differential output of the comparator passes through the common-source amplification stages of the eleventh NMOS NM11 and the twelfth NMOS NM12 to obtain large signals VOUTN' and VOUTP', and then passes through the push-pull amplifier of the first inverter and the second inverter in the logic module Logic to be converted into a digital signal of 0 to VDD, and finally passes through subsequent logic processing to obtain the required control signal to control the turn-on and turn-off of the thirteenth NMOS NM13 and the fourteenth NMOS NM14, thereby pulling down the voltage of VOUTN or VOUTP to stabilize the state of the comparator.

[0118] In the embodiment of the application, Figure 14 and Figure 15 are respectively Figure 9 The response schematic diagram of VOUTN under the positive voltage interference at t1 and VOUTP under the negative voltage interference at t1 in the example;

[0119] Figure 14 and Figure 15 t2-t1 in the above is the response time of the feedback module Reliable. It starts to respond at t2 and stops responding at t3;

[0120] Figure 14 and Figure 15 The low potential feedback output of the feedback module Reliable between t2 and t3 is shown, that is, the potential of VOUTN in the original L state is pulled down, the state of the original comparator is quickly recovered, and an error response is avoided when the comparator of the first stage with high gain in the high-reliability design is suddenly disturbed by a positive or negative voltage pulse.

[0121] Embodiment two

[0122] Compared with embodiment one, the comparator is a P-type differential pair, which is used for positive voltage disturbance and negative voltage disturbance (for example Figure 13 The comparator circuit shown in the figure).

[0123] In the embodiment of the application, the preamplification stage circuit includes a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS.

[0124] The comparator circuit includes a sixth NMOS NM6 and a seventh NMOS NM7; wherein,

[0125] The source of the first PMOS is connected to a power voltage VDD, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS;

[0126] The drain of the fourth NMOS NM4 is short-circuited with the gate, the gate of the fourth NMOS NM4 is connected to the gate of the sixth NMOS NM6, the drain of the fifth NMOS NM5 is short-circuited with the gate, and the gate of the fifth NMOS NM5 is connected to the gate of the seventh NMOS NM7; the sources of the fourth NMOS NM4, the fifth NMOS NM5, the sixth NMOS NM6 and the seventh NMOS NM7 are connected in sequence and connected to a power ground GND;

[0127] The drain of the sixth NMOS NM6 is connected to the drain of the fifth NMOS NM5, the drain of the third PMOS PM3 and a second input end of a feedback module Reliable respectively, the second output end of the feedback module Reliable is connected to the drain of the fifth NMOS NM5 and the drain of the third PMOS PM3 respectively; the drain of the seventh NMOS NM7 is connected to the drain of the fourth NMOS NM4, the drain of the second PMOS PM2 and a first input end of the feedback module Reliable respectively, and the first output end of the feedback module Reliable is connected to the drain of the fourth NMOS NM4 and the drain of the second PMOS PM2 respectively.

[0128] In the embodiment of the application, the feedback module Reliable comprises an eighth PMOS PM8, a ninth PMOS PM9, a tenth PMOS PM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14, a fifteenth NMOS NM15, a sixteenth NMOS NM16 and first and second logic modules (Logic1, Logic2) Logic1; wherein,

[0129] The first and second logic modules Logic are used for different types of voltage disturbances;

[0130] The sources of the eighth PMOS PM8, the ninth PMOS PM9 and the tenth PMOS PM10 are connected to a power voltage VDD;

[0131] The gate of the eighth PMOS PM8 is shorted with the drain of the eighth PMOS PM8, the drain of the eighth PMOS PM8 is connected with a bias current, the gate of the eighth PMOS PM8 is connected with the gate of the first PMOS, the gate of the ninth PMOS PM9 and the gate of the tenth PMOS PM10 are connected with a bias voltage;

[0132] The drain of the ninth PMOS PM9 is connected with the drain of the eleventh NMOS NM11, the drain of the tenth PMOS PM10 is connected with the drain of the twelfth NMOS NM12, the drain of the thirteenth NMOS NM13 is connected with the drain of the sixth NMOS NM6 and the drain of the fifth NMOS NM5 and the drain of the third PMOS PM3 respectively, the drain of the fourteenth NMOS NM14 is connected with the drain of the seventh NMOS NM7 and the drain of the fourth NMOS NM4 and the drain of the second PMOS PM2 respectively;

[0133] The source of the eleventh NMOS NM11, the source of the twelfth NMOS NM12, the source of the thirteenth NMOS NM13 and the source of the fourteenth NMOS NM14 are connected with a power ground GND;

[0134] The gate of the eleventh NMOS NM11 is connected with the drain of the second PMOS PM2 and the drain of the fourth NMOS NM4, the gate of the twelfth NMOS NM12 is connected with the drain of the third PMOS PM3 and the drain of the fifth NMOS NM5;

[0135] The drain of the fifteenth NMOS NM15 is connected between the drain of the second PMOS PM2 and the drain of the fourth NMOS NM4, the source of the fifteenth NMOS NM15 is connected with the ground;

[0136] The drain of the sixteenth NMOS NM16 is connected between the drain of the third PMOS PM3 and the drain of the fifth NMOS NM5, the source of the sixteenth NMOS NM16 is connected with the ground;

[0137] The drain of the ninth PMOS PM9 and the drain of the eleventh NMOS NM11 are connected with the first input end of the first and second logic modules Logic, the drain of the tenth PMOS PM10 and the drain of the twelfth NMOS NM12 are connected with the second input end of the first and second logic modules Logic, the gate of the thirteenth NMOS NM13 is connected with the first output end of the first logic module Logic, the gate of the fourteenth NMOS NM14 is connected with the second output end of the first logic module Logic, the gate of the fifteenth NMOS NM15 is connected with the second output end of the second logic module Logic, and the gate of the sixteenth NMOS NM16 is connected with the first output end of the second logic module Logic.

[0138] In the embodiments of the present application, please refer to Figure 11 , the logic module Logic for the positive voltage disturbance includes a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a fifth inverter I6, a sixth inverter I7, a seventh inverter I8, a first NOR gate I9, a second NOR gate I10, a second NAND gate I11, a third NAND gate I12; wherein the input end of the first inverter I1 is the second input end of the logic module Logic, which is used to obtain the amplified second output signal VOUTP', the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the sixth inverter I7, the output end of the sixth inverter I7 is connected with the first input end of the first NOR gate I9, and the output end of the first NOR gate I9 is connected with the second input end of the second NAND gate I11;

[0139] The input end of the second inverter I2 is the first input end of the logic module Logic, which is used to obtain the amplified first output signal VOUTN', the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the seventh inverter I8, the output end of the seventh inverter I8 is connected with the second input end of the second NOR gate I10, and the output end of the second NOR gate I10 is connected with the first input end of the third NAND gate I12;

[0140] The first input end of the first NAND gate I5 is connected with the output end of the third inverter I3, the second input end of the first NAND gate I5 is connected with the output end of the fourth inverter I4, the output end of the first NAND gate I5 is connected with the input end of the fifth inverter I6, the output end of the fifth inverter I6 is connected with the first input end of the second NAND gate I11 and the second input end of the third NAND gate I12 respectively, the second input end of the first NOR gate I9 is connected between the output end of the second NOR gate I10 and the first input end of the third NAND gate I12, and the first input end of the second NOR gate I10 is connected between the output end of the first NOR gate I9 and the second input end of the second NAND gate I11;

[0141] The output end of the third NAND gate I12 is the first output end of the logic module Logic, and the output end of the second NAND gate I11 is the second output end of the logic module Logic.

[0142] In the embodiments of the present application, please refer to Figure 12 , the logic module Logic for the negative voltage disturbance includes a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a second NAND gate I6, a third NAND gate I7, a first NOR gate I8, a second NOR gate I9; wherein,

[0143] The input end of the first inverter I1 is the second input end of the logic module Logic, the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the second NAND gate I6, and the output end of the second NAND gate I6 is connected with the second input end of the first NOR gate I8;

[0144] The input end of the second inverter I2 is the first input end of the logic module Logic, the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the third NAND gate I7, and the output end of the third NAND gate I7 is connected with the first input end of the second NOR gate I9;

[0145] The first input end of the first NAND gate I5 is connected between the output end of the third inverter I3 and the first input end of the second NAND gate I6, the second input end of the first NAND gate I5 is connected between the output end of the fourth inverter I4 and the second input end of the third NAND gate I7, and the output end of the first NAND gate I5 is connected with the first input end of the first NOR gate I8 and the second input end of the second NOR gate I9 respectively;

[0146] The second input end of the second NAND gate I6 is connected between the output end of the third NAND gate I7 and the first input end of the second NOR gate I9, and the first input end of the third NAND gate I7 is connected between the output end of the second NAND gate I6 and the second input end of the first NOR gate I8;

[0147] The output end of the first NOR gate I8 is the first output end of the logic module Logic, and the output end of the second NOR gate I9 is the second output end of the logic module Logic.

[0148] Embodiment three

[0149] Please refer to Figure 8 The feedback module Reliable is an N-type differential pair, and the feedback module Reliable is used for positive voltage disturbance or negative voltage disturbance.

[0150] The feedback module Reliable is used for receiving a disturbance signal of the first and second output signals, the disturbance signal usually includes positive voltage disturbance and negative voltage disturbance, and the feedback module Reliable generates first and second feedback signals to feed back to the first and second output signals, so that the potential of the first and second output signals originally in L or X state is pulled down.

[0151] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is interfered by a positive voltage, and changes from the L or X state to the X or H state, the disturbance is input from the first and second input terminals of the feedback module Reliable and output from the first or second output terminal to the first or second output signal, so as to pull down the potential of the first or second output signal originally in the L or X state, thereby stabilizing the working state of the comparator.

[0152] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is interfered by a positive voltage, and changes from the L or X state to the X or H state, the disturbance is input from the first and second input terminals of the feedback module Reliable and output from the first or second output terminal to the first or second output signal, so as to pull down the potential of the first or second output signal originally in the L or X state, thereby stabilizing the working state of the comparator.

[0153] In the embodiment of the application, the preamplification stage circuit comprises a seventh NMOS NM7, a fifth NMOS NM5, a sixth NMOS NM6, a first PMOS PM1 and a second PMOS PM2.

[0154] The comparator circuit comprises a third PMOS PM3 and a fourth PMOS PM4; wherein,

[0155] The source of the seventh NMOS NM7 is connected to the power ground GND, the gate of the seventh NMOS NM7 is connected to a bias voltage, the gate of the fifth NMOS NM5 is connected to the first input signal, the gate of the sixth NMOS NM6 is connected to the second input signal, the drain of the seventh NMOS NM7 is connected to the source of the fifth NMOS NM5 and the source of the sixth NMOS NM6, the drain of the fifth NMOS NM5 is connected to the drain of the first PMOS PM1, and the drain of the sixth NMOS NM6 is connected to the drain of the second PMOS PM2.

[0156] The source and the gate of the first PMOS PM1 are shorted, the gate of the first PMOS PM1 is connected to the gate of the third PMOS PM3, the source and the gate of the second PMOS PM2 are shorted, the gate of the second PMOS PM2 is connected to the gate of the fourth PMOS PM4, and the sources of the first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 are connected in sequence and connected to the power voltage VDD.

[0157] The drain of the third PMOS PM3 is connected with the drain of the second PMOS PM2, the drain of the sixth NMOS NM6 and the second input end of the feedback module Reliable respectively, and the second output end of the feedback module Reliable is connected with the drain of the second PMOS PM2 and the drain of the sixth NMOS NM6 respectively; the drain of the fourth PMOS PM4 is connected with the drain of the first PMOS PM1, the drain of the fifth NMOS NM5 and the first input end of the feedback module Reliable respectively, and the first output end of the feedback module Reliable is connected with the drain of the first PMOS PM1 and the drain of the fifth NMOS NM5 respectively.

[0158] In the embodiment of the application, the feedback module Reliable comprises an eighth NMOS NM8, a ninth NMOS NM9, a tenth NMOS NM10, an eleventh PMOS PM11, a twelfth PMOS PM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14 and a logic module Logic; wherein,

[0159] The source of the eighth NMOS NM8, the ninth NMOS NM9 and the tenth NMOS NM10 is connected with the power supply ground GND;

[0160] The gate of the eighth NMOS NM8 is short-circuited with the drain, the drain of the eighth NMOS NM8 is connected with the bias current, the gate of the eighth NMOS NM8 is connected with the gate of the seventh NMOS NM7, and the gate of the ninth NMOS NM9 and the gate of the tenth NMOS NM10 are connected with the bias voltage;

[0161] The drain of the ninth NMOS NM9 is connected with the drain of the eleventh PMOS PM11, the drain of the tenth NMOS NM10 is connected with the drain of the twelfth PMOS PM12, the drain of the thirteenth NMOS NM13 is connected with the drain of the third PMOS PM3, the drain of the second PMOS PM2 and the drain of the sixth NMOS NM6 respectively, and the drain of the fourteenth NMOS NM14 is connected with the drain of the fourth PMOS PM4, the drain of the first PMOS PM1 and the drain of the fifth NMOS NM5 respectively;

[0162] The source of the eleventh PMOS PM11 and the twelfth PMOS PM12 is connected with the power supply voltage VDD, and the source of the thirteenth NMOS NM13 and the fourteenth NMOS NM14 is connected with the power supply ground GND;

[0163] The gate of the eleventh PMOS PM11 is connected with the drain of the fifth NMOS NM5 and the first PMOS PM1, and the gate of the twelfth PMOS PM12 is connected with the drain of the sixth NMOS NM6 and the second PMOS PM2;

[0164] The first input end of the logic module Logic is connected with the drain of the ninth NMOS NM9 and the eleventh PMOS PM11, and the first output end of the logic module Logic is connected with the gate of the thirteenth NMOS NM13; the second input end of the logic module Logic is connected with the drain of the tenth NMOS NM10 and the twelfth PMOS PM12, and the second output end of the logic module Logic is connected with the gate of the fourteenth NMOS NM14.

[0165] In the embodiment of the application, please refer to Figure 11 The logic module Logic is used for forward voltage disturbance, which comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a fifth inverter I6, a sixth inverter I7, a seventh inverter I8, a first NOR gate I9, a second NOR gate I10, a second NAND gate I11 and a third NAND gate I12; wherein the input end of the first inverter I1 is used as the second input end of the logic module Logic, and is used for acquiring the amplified second output signal VOUTP', the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the sixth inverter I7, the output end of the sixth inverter I7 is connected with the first input end of the first NOR gate I9, and the output end of the first NOR gate I9 is connected with the second input end of the second NAND gate I11;

[0166] The input end of the second inverter I2 is used as the first input end of the logic module, and is used for acquiring the amplified first output signal VOUTN', the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the seventh inverter I8, the output end of the seventh inverter I8 is connected with the second input end of the second NOR gate I10, and the output end of the second NOR gate I10 is connected with the first input end of the third NAND gate I12;

[0167] The first input end of the first NOR gate I5 is connected with the output end of the third inverter I3, the second input end of the first NOR gate I5 is connected with the output end of the fourth inverter I4, the output end of the first NOR gate I5 is connected with the input end of the fifth inverter I6, the output end of the fifth inverter I6 is respectively connected with the first input end of the second NOR gate I11 and the second input end of the third NOR gate I12, the second input end of the first NAND gate I9 is connected between the output end of the second NAND gate I10 and the first input end of the third NOR gate I12, the first input end of the second NAND gate I10 is connected between the output end of the first NAND gate I9 and the second input end of the second NOR gate I11;

[0168] The output end of the third NOR gate I12 is the first output end of the logic module Logic, and the output end of the second NOR gate I11 is the second output end of the logic module Logic.

[0169] In the embodiment of the present application, referring to Figure 12 The logic module Logic is used for negative voltage disturbance, and comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a second NAND gate I6, a third NAND gate I7, a first NOR gate I8 and a second NOR gate I9; wherein,

[0170] The input end of the first inverter I1 is the second input end of the logic module Logic, the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the second NAND gate I6, and the output end of the second NAND gate I6 is connected with the second input end of the first NOR gate I8;

[0171] The input end of the second inverter I2 is the first input end of the logic module Logic, the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the third NAND gate I7, and the output end of the third NAND gate I7 is connected with the first input end of the second NOR gate I9;

[0172] The first input end of the first NAND gate I5 is connected between the output end of the third inverter I3 and the first input end of the second NAND gate I6, the second input end of the first NAND gate I5 is connected between the output end of the fourth inverter I4 and the second input end of the third NAND gate I7, and the output end of the first NAND gate I5 is respectively connected with the first input end of the first NOR gate I8 and the second input end of the second NOR gate I9;

[0173] The second input end of the second NAND gate I6 is connected between the output end of the third NAND gate I7 and the first input end of the second NOR gate I9, and the first input end of the third NAND gate I7 is connected between the output end of the second NAND gate I6 and the second input end of the first NOR gate I8.

[0174] The output end of the first NOR gate I8 is the first output end of the logic module Logic, and the output end of the second NOR gate I9 is the second output end of the logic module Logic. Specifically, the differential output of the comparator passes through the common-source amplification stages of the eleventh NMOS NM11 and the twelfth NMOS NM12, to obtain large signals VOUTN' and VOUTP', and then passes through the push-pull amplifier of the first inverter and the second inverter in the logic module Logic to be converted into a digital signal of 0-VDD, and finally passes through subsequent logic processing to obtain the required control signal to control the turn-on and turn-off of the thirteenth NMOS NM13 and the fourteenth NMOS NM14, so as to pull down the voltage of VOUTN or VOUTP, and stabilize the state of the comparator.

[0175] Embodiment four

[0176] In the embodiments of the present application, the comparator is an N-type differential pair, which is used for positive voltage disturbance and negative voltage disturbance. Its structure is similar to that of a P-type differential pair used for positive voltage disturbance and negative voltage disturbance, which is not described here.

[0177] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The actual implementation of each component can be arbitrarily changed in shape, number and proportion, and the layout pattern of the components can also be more complex.

[0178] In summary, the comparator of the present application inputs the differential output of the comparator with low potential feedback into the feedback module and outputs the differential output of the comparator with low potential feedback back to the low potential feedback. When there is a large enough positive or negative voltage disturbance, the feedback module will generate an output response and pull down the potential of the differential output end in the original state X or L, to stabilize the state of the comparator. This highly reliable design method increases a small amount of cost, but can effectively avoid the false response of the high-precision comparator caused by the external positive and negative voltage interference, so that the high-precision comparator can be applied in a more complex working environment, and the reliability of the entire circuit system is improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0179] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A low voltage feedback comparator, characterized by, Comprising: a pre-amplification stage circuit for amplifying the first and second input signals; a comparator circuit for receiving the first and second input signals for voltage comparison, thereby outputting the first and second output signals; a feedback module for receiving a perturbation signal of the first and second output signals, generating the first and second feedback signals to feedback to the first and second output signals, so that the potential of the first and second output signals originally in L or X state is pulled down; wherein, when the comparator is a P-type differential pair, the feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, and a logic module; the drain of the ninth PMOS is connected with the drain of the eleventh NMOS, and the drain of the tenth PMOS is connected with the drain of the twelfth NMOS; the gate of the eleventh NMOS is connected with the first output end of the comparator circuit, and the gate of the twelfth NMOS is connected with the second output end of the comparator circuit; the first and second input ends of the logic module are respectively connected with the drains of the ninth PMOS and the eleventh NMOS, and the drains of the tenth PMOS and the twelfth NMOS, and the first and second output ends of the logic module are respectively connected with the gates of the thirteenth NMOS and the fourteenth NMOS; the drain of the thirteenth NMOS is connected with the second output end of the comparator circuit, and the drain of the fourteenth NMOS is connected with the first output end of the comparator circuit; or, when the comparator is an N-type differential pair, the feedback module comprises an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, a fourteenth NMOS, and a logic module; the drain of the ninth NMOS is connected with the drain of the eleventh PMOS, and the drain of the tenth NMOS is connected with the drain of the twelfth PMOS; the gate of the eleventh PMOS is connected with the first output end of the comparator circuit, and the gate of the twelfth PMOS is connected with the second output end of the comparator circuit; the first and second input ends of the logic module are respectively connected with the drains of the ninth NMOS and the eleventh PMOS, and the drains of the tenth NMOS and the twelfth PMOS, and the first and second output ends of the logic module are respectively connected with the gates of the thirteenth NMOS and the fourteenth NMOS; the drain of the thirteenth NMOS is connected with the second output end of the comparator circuit, and the drain of the fourteenth NMOS is connected with the first output end of the comparator circuit.

2. The low potential feedback comparator of claim 1, wherein: The pre-amplification stage circuit is a differential amplification circuit.

3. The low potential feedback comparator of claim 1, wherein: The perturbation signal comprises a positive voltage perturbation and a negative voltage perturbation.

4. The low potential feedback comparator of claim 3, wherein: The comparator is a P-type differential pair, and the feedback module is used for the positive voltage perturbation or the negative voltage perturbation.

5. The low potential feedback comparator of claim 4, wherein: The pre-amplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS; The comparator circuit comprises a sixth NMOS and a seventh NMOS; wherein, The source of the first PMOS is connected to a power supply voltage, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS; The drain of the fourth NMOS is short-circuited to the gate of the fourth NMOS, the gate of the fourth NMOS is connected to the gate of the sixth NMOS, the drain of the fifth NMOS is short-circuited to the gate of the fifth NMOS, the gate of the fifth NMOS is connected to the gate of the seventh NMOS, and the source of the fourth NMOS, the source of the fifth NMOS, the source of the sixth NMOS and the source of the seventh NMOS are sequentially connected and connected to a power supply ground; The drain of the sixth NMOS is connected to the drain of the fifth NMOS, the drain of the third PMOS and a second input end of a feedback module respectively, the second output end of the feedback module is connected to the drain of the fifth NMOS and the drain of the third PMOS respectively, the drain of the seventh NMOS is connected to the drain of the fourth NMOS, the drain of the second PMOS and a first input end of the feedback module respectively, and the first output end of the feedback module is connected to the drain of the fourth NMOS and the drain of the second PMOS respectively.

6. The low potential feedback comparator of claim 5, wherein: The feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein, The source of the eighth PMOS, the source of the ninth PMOS and the source of the tenth PMOS are all connected to a power supply voltage; The gate of the eighth PMOS is short-circuited to the drain of the eighth PMOS, the drain of the eighth PMOS is connected to a bias current, the gate of the eighth PMOS is connected to the gate of the first PMOS, the gate of the ninth PMOS and the gate of the tenth PMOS are all connected to a bias voltage; The drain of the ninth PMOS is connected to the drain of the eleventh NMOS, the drain of the tenth PMOS is connected to the drain of the twelfth NMOS, the drain of the thirteenth NMOS is connected to the drain of the sixth NMOS, the drain of the fifth NMOS and the drain of the third PMOS respectively, and the drain of the fourteenth NMOS is connected to the drain of the seventh NMOS, the drain of the fourth NMOS and the drain of the second PMOS respectively; The source of the eleventh NMOS, the source of the twelfth NMOS, the source of the thirteenth NMOS and the source of the fourteenth NMOS are all connected to a power supply ground; The gate of the eleventh NMOS is connected to the drain of the second PMOS and the drain of the fourth NMOS, and the gate of the twelfth NMOS is connected to the drain of the third PMOS and the drain of the fifth NMOS. The first input end of the logic module is connected with the drain of the ninth PMOS and the eleventh NMOS, and the first output end of the logic module is connected with the gate of the thirteenth NMOS; the second input end of the logic module is connected with the drain of the tenth PMOS and the twelfth NMOS, and the second output end of the logic module is connected with the gate of the fourteenth NMOS.

7. The low potential feedback comparator of claim 3, wherein: The comparator is a P-type differential pair, and the feedback module is used for the positive voltage disturbance and the negative voltage disturbance.

8. The low potential feedback comparator of claim 7, wherein: The pre-amplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS; The source of the first PMOS is connected with a power supply voltage, the gate of the first PMOS is connected with a bias voltage, the gate of the second PMOS is connected with a first input signal, the gate of the third PMOS is connected with a second input signal, the drain of the first PMOS is connected with the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected with the drain of the fourth NMOS, and the drain of the third PMOS is connected with the drain of the fifth NMOS.

9. The low potential feedback comparator of claim 1, wherein: The feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, a fifteenth NMOS and a sixteenth NMOS, and the logic module comprises a first logic module and a second logic module; wherein, The first logic module and the second logic module are used for different types of voltage disturbances; The drain of the fifteenth NMOS is connected between the drain of the second PMOS and the drain of the fourth NMOS, and the source of the fifteenth NMOS is connected with the ground; The drain of the sixteenth NMOS is connected between the drain of the third PMOS and the drain of the fifth NMOS, and the source of the sixteenth NMOS is connected with the ground; The drain of the ninth PMOS and the drain of the eleventh NMOS are connected with the first input end of the first logic module and the second logic module; the drain of the tenth PMOS and the drain of the twelfth NMOS are connected with the second input end of the first logic module and the second logic module; the gate of the thirteenth NMOS is connected with the first output end of the first logic module, the gate of the fourteenth NMOS is connected with the second output end of the first logic module, the gate of the fifteenth NMOS is connected with the second output end of the second logic module, and the gate of the sixteenth NMOS is connected with the first output end of the second logic module.

10. The low potential feedback comparator of claim 3, wherein: The comparator is an N-type differential pair, and the feedback module is used for the positive voltage disturbance or the negative voltage disturbance.

11. The low potential feedback comparator of claim 10, wherein: The pre-amplification stage circuit comprises a seventh NMOS, a fifth NMOS, a sixth NMOS, a first PMOS and a second PMOS; The comparator circuit comprises a third PMOS and a fourth PMOS; wherein, The source of the seventh NMOS is connected with a power supply ground, the gate of the seventh NMOS is connected with a bias voltage, the gate of the fifth NMOS is connected with a first input signal, the gate of the sixth NMOS is connected with a second input signal, the drain of the seventh NMOS is connected with the source of the fifth NMOS and the source of the sixth NMOS respectively, the drain of the fifth NMOS is connected with the drain of the first PMOS, and the drain of the sixth NMOS is connected with the drain of the second PMOS; The drain and the gate of the first PMOS are short-circuited, the gate of the first PMOS is connected with the gate of the third PMOS, the drain and the gate of the second PMOS are short-circuited, and the gate of the second PMOS is connected with the gate of the fourth PMOS; the sources of the first PMOS, the second PMOS, the third PMOS and the fourth PMOS are connected in sequence and connected with a power supply voltage; The drain of the third PMOS is connected with the drain of the second PMOS, the drain of the sixth NMOS and a second input end of a feedback module respectively, the second output end of the feedback module is connected with the drain of the second PMOS and the drain of the sixth NMOS respectively; the drain of the fourth PMOS is connected with the drain of the first PMOS, the drain of the fifth NMOS and a first input end of the feedback module respectively, and the first output end of the feedback module is connected with the drain of the first PMOS and the drain of the fifth NMOS respectively.

12. The low potential feedback comparator of claim 11, wherein: The feedback module comprises an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein, The sources of the eighth NMOS, the ninth NMOS and the tenth NMOS are connected with a power supply ground; The gate and the drain of the eighth NMOS are short-circuited, the drain of the eighth NMOS is connected with a bias current, the gate of the eighth NMOS is connected with the gate of the seventh NMOS, and the gates of the ninth NMOS and the tenth NMOS are connected with a bias voltage; The drain of the ninth NMOS is connected with the drain of the eleventh PMOS, the drain of the tenth NMOS is connected with the drain of the twelfth PMOS, the drain of the thirteenth NMOS is connected with the drain of the third PMOS, the drain of the second PMOS and the drain of the sixth NMOS respectively, and the drain of the fourteenth NMOS is connected with the drain of the fourth PMOS, the drain of the first PMOS and the drain of the fifth NMOS respectively; The sources of the eleventh PMOS and the twelfth PMOS are connected with a power supply voltage, and the sources of the thirteenth NMOS and the fourteenth NMOS are connected with a power supply ground; The gate of the eleventh PMOS is connected with the drain of the fifth NMOS and the drain of the first PMOS, and the gate of the twelfth PMOS is connected with the drain of the sixth NMOS and the drain of the second PMOS; The second input end of the logic module is connected with the drain of the tenth NMOS and the drain of the twelfth PMOS, the second output end of the logic module is connected with the gate of the fourteenth NMOS, the first input end of the logic module is connected with the drain of the ninth NMOS and the drain of the eleventh PMOS, and the first output end of the logic module is connected with the gate of the thirteenth NMOS.

13. The low- voltage feedback comparator of claim 3, wherein: The comparator is an N-type differential pair, and the feedback module is used for the positive voltage disturbance and the negative voltage disturbance.

14. The low voltage feedback comparator of claim 6 or 9 or 12 or 13, wherein: When the feedback module is used for responding to the positive voltage disturbance, the logic module used for the positive voltage disturbance comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NOR gate, a fifth inverter, a sixth inverter, a seventh inverter, a first NAND gate, a second NAND gate, a second NOR gate, a third NOR gate; wherein, The input end of the first inverter is the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the first NAND gate, and the output end of the first NAND gate is connected with the second input end of the second NOR gate; The input end of the second inverter is the first input end of the logic module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the second input end of the second NAND gate, and the output end of the second NAND gate is connected with the first input end of the third NOR gate; The first input end of the first NOR gate is connected with the output end of the third inverter, the second input end of the first NOR gate is connected with the output end of the fourth inverter, the output end of the first NOR gate is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the first input end of the second NOR gate and the second input end of the third NOR gate, the second input end of the first NAND gate is connected between the output end of the second NAND gate and the first input end of the third NOR gate, and the first input end of the second NAND gate is connected between the output end of the first NAND gate and the second input end of the second NOR gate; The output end of the third NOR gate is the first output end of the logic module, and the output end of the second NOR gate is the second output end of the logic module.

15. The low voltage feedback comparator of claim 6 or 9 or 12 or 13, wherein: When the feedback module is used for responding to a negative voltage disturbance, the logic module for the negative voltage disturbance comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a first NOR gate and a second NOR gate; wherein, The input end of the first inverter is the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the second NAND gate, and the output end of the second NAND gate is connected with the second input end of the first NOR gate; The input end of the second inverter is the first input end of the logic module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the third NAND gate, and the output end of the third NAND gate is connected with the first input end of the second NOR gate; The first input end of the first NAND gate is connected between the output end of the third inverter and the first input end of the second NAND gate, the second input end of the first NAND gate is connected between the output end of the fourth inverter and the second input end of the third NAND gate, and the output end of the first NAND gate is connected with the first input end of the first NOR gate and the second input end of the second NOR gate; The second input end of the second NAND gate is connected between the output end of the third NAND gate and the first input end of the second NOR gate, and the first input end of the third NAND gate is connected between the output end of the second NAND gate and the second input end of the first NOR gate; The output end of the first NOR gate is the first output end of the logic module, and the output end of the second NOR gate is the second output end of the logic module.

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