A Time-Sensitive Network Switch and Method Based on SMS Architecture

Abstract

The present invention discloses a time-sensitive network switch and method based on the SMS architecture. The switch forms a pre-switching stage and a post-switching stage based on the SMS architecture; data frames enter the shared cache module through the pre-switching stage and are output through the post-switching stage; the SMS architecture includes a first-level crossbar module and a second-level crossbar module; the switch includes an input processing module, a descriptor control module, a unicast / multicast arbitration module, a shared cache module, an AS time synchronization module, and an output processing module. The present invention adopts the SMS architecture as the switching architecture of the TSN switch and supports the cut-through forwarding transmission mode, reducing the transmission delay; at the same time, the storage method of the shared cache enhances the ability of each port to cope with burst traffic. The SMS architecture of the present invention enables each TSN protocol to be reasonably arranged in the front and rear stages of the switch, having a certain degree of reusability.

Description

Technical Field

[0001] The present invention relates to the technical field of data link layer networks including Time Sensitive Network (TSN), and particularly to a TSN switch and method based on the SMS architecture. Background Art

[0002] Time Sensitive Network (TSN) is an extended protocol based on Ethernet, with the full name of Time Sensitive Network, including IEEE802.1AS, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB. The purpose is to improve its determinism, reliability and low latency on the basis of the widespread application of Ethernet. Emerging services such as artificial intelligence, autonomous driving, and industrial control require extremely low latency, precise arrival times and zero packet loss rates, which are requirements that traditional Ethernet switches cannot meet.

[0003] Chinese Patent CN113821516A discloses a time-sensitive network switching architecture based on virtual queues, which relates to the field of industrial automation, including a scheduling information module, a scheduling module and a parallel cache module. Although this architecture is very flexible, it only mentions the integration of the Qbv protocol, and does not mention how IEEE802.1AS, IEEECB, IEEE802.1Qci are integrated with this architecture. In addition, the adaptability to other TSN protocols is not clear.

[0004] Chinese Patent CN105634995A discloses a low-latency airborne gigabit Ethernet switching architecture. However, it only supports the 1588 time synchronization protocol and does not provide deterministic guarantees for time-critical services. Summary of the Invention

[0005] The object of the present invention is to provide a TSN switch and method based on the SMS architecture. The present invention constructs a loosely coupled switch architecture that integrates TSN protocols (IEEE802.1AS, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB); specifically, it adopts the SMS (Switch-Memory-Switch) architecture as the switching architecture of the TSN switch, and supports the cut-through transmission mode, reducing the transmission delay; at the same time, the storage method of shared cache is adopted to enhance the ability of each port to handle burst traffic. The SMS architecture of the present invention enables each TSN protocol to be reasonably arranged in the front and rear stages of the switch, with a certain degree of reusability.

[0006] Among them, the SMS architecture is a switching architecture including a front - end crossbar matrix, an intermediate cache, and a back - end crossbar matrix.

[0007] The present invention is realized through the following technical solutions:

[0008] In a first aspect, the present invention provides a time - sensitive network switch based on the SMS architecture. The switch forms a switching front - end and a switching back - end based on the SMS architecture; data frames enter the shared cache module through the switching front - end and are output through the switching back - end; the SMS architecture includes a first - level crossbar module and a second - level crossbar module; the switch includes:

[0009] An input processing module, configured to store the input data frames into the input cache queue; extract keyword field information from the data frames and perform a look - up table operation to obtain the forwarding destination port and the flow identifier; according to the flow identifier, perform Qci token bucket filtering and CB redundancy removal operations to obtain a valid signal and generate a descriptor;

[0010] A descriptor control module, configured to control reading the descriptors of ordinary frames from the input processing module and reading the descriptors of AS output frames from the AS time synchronization module, and sending them to the unicast - multicast arbitration module for descriptor scheduling; and sending the data frames in the input cache queue to the shared cache module through the first - level crossbar module;

[0011] A unicast - multicast arbitration module, configured to perform comprehensive unicast and multicast scheduling by combining Qbv gating shaping according to the descriptors of ordinary frames and AS output frames, generate an arbitration result and an output frame descriptor; send the arbitration result to the shared cache, and send the output frames in the shared cache to the output processing module for processing;

[0012] A shared cache module, configured to take out the AS output frames according to the data frames in the input cache queue, AS output frames, and the arbitration result, and send them to the corresponding output ports through the second - level crossbar module; a first - level crossbar module is provided in front of the shared cache module, and a second - level crossbar module is provided behind the shared cache module;

[0013] An AS time synchronization module, configured to provide AS time synchronization for each module and be arranged in parallel with the data frame flow direction.

[0014] Further, the switch further includes an output processing module, which is used to extract the AS output frame according to the output frame descriptor, mark the AS timestamp for the output frame and send it to the AS time synchronization module; and correct and output the output frame; the correction includes: adding a VLAN TAG and removing the VLAN TAG according to the port information, changing the DMAC field of the frame with the requirement of separating the redundant flow (CB flow) by looking up the table, and adding an R-TAG field.

[0015] Further, the switch further includes a Qci token bucket unit, a CB redundancy removal unit and a Qbv unit;

[0016] The Qci token bucket unit is used to find the corresponding token bucket according to the flow identifier (i.e., flow id) generated by the look-up table operation, and reduce the impact of burst traffic on the switch; specifically, it records the timestamp, and increases the tokens by combining the fixed-point decimal multiplication method, and uniformly manages the token buckets of different traffic through RAM loading; and the token bucket of a certain traffic only performs a one-time token increase or decrease operation when it is used.

[0017] The CB redundancy removal unit is used to proxy terminals without CB function and perform redundancy removal function on the member flows identified as the same combined flow; specifically, it removes redundant frames in the transmission link to reduce redundant bandwidth occupancy; and provides flow separation and R-TAG removal functions for nodes without CB redundancy removal function. As a further implementation, the CB redundancy removal unit is respectively integrated in the input processing module and the output processing module. The input processing module generates a request for the CB redundancy removal unit, first performs redundancy removal of the repeated transmission member flows, and then performs redundancy removal of different member flows; the output processing module mainly provides R-TAG addition and R-TAG removal functions for terminals without CB function.

[0018] The Qbv unit is used to act on the priority queue of the unicast / multicast arbitration module, and generate corresponding gating information to inhibit or allow the corresponding priority descriptor to be arbitrated by the unicast / multicast arbitration.

[0019] Further, the first-level crossbar module is a cross-switch matrix that fully connects the descriptors;

[0020] The second-level crossbar module is a cross-switch matrix that fully connects the output frames.

[0021] Further, the AS time synchronization adopts the AS time synchronization proxy mechanism, specifically, if the upstream node times out in sending the synchronization frame, the timeout status is added to the sending unit, so as to proxy the upstream node to send the synchronization frame to the downstream node.

[0022] Further, the AS time synchronization module includes a preprocessing unit, a timing unit, a sending unit, a receiving unit, a synchronization transfer unit and a link measurement unit;

[0023] A preprocessing unit, which is used to classify the clock domain of a data frame, timestamp it, and eliminate frames that do not conform to the AS format; extract corresponding information according to different synchronization frames, and send the information to the subsequent receiving unit and link measurement unit; where: if it is a link measurement frame, it enters the link request and link response modules of the corresponding port, and these two modules are responsible for calculating the frequency offset and link delay. If it is a synchronization frame, it enters the receiving module to obtain the update of the upstream receiving time and the frequency offset between the master node and this node, and enters the synchronization transfer module after receiving the complete synchronization frame sync and synchronization follow-up frame followup.

[0024] Receiving unit: According to the synchronization frame information extracted by the preprocessing unit, obtain the update of the upstream receiving time and frequency offset, and transfer the received signal to the synchronization transfer unit;

[0025] Synchronization transfer unit: Transfer the synchronization information to the timing unit and sending unit according to the configuration;

[0026] A timing unit, which is used to compensate for the loss of intermediate variable calculation delay, and obtain the upstream synchronization moment based on the master node clock by adding the starting moment of the master node, the synchronization correction value, and the link delay; add the calculation delay to the master node clock to obtain the final synchronization point;

[0027] Sending unit, which is used to propagate the synchronization frame according to the frequency of the received synchronization frame or send it at its own fixed frequency; if the synchronization frame has not been received for three consecutive upstream sending frequencies, resend the frame information received last time downstream; and is used to send data frames downstream, put them into the fixed buffer queue in the shared buffer, and generate corresponding descriptors and send them to the descriptor queue of the corresponding port of the unicast / multicast arbitration;

[0028] Link measurement unit, which is used to calculate the frequency offset and link delay.

[0029] Furthermore, a unicast / multicast arbitration module, which is used to perform comprehensive unicast and multicast scheduling according to the descriptors of ordinary frames and AS output frames, combined with Qbv gating shaping, to generate arbitration results and output frame descriptors; and send the arbitration results into the shared buffer, and send the output frames in the shared buffer to the output processing module for processing, specifically including:

[0030] Generate unicast / multicast requests according to the descriptors of ordinary frames and AS output frames;

[0031] Poll the descriptors sent by each port according to the unicast / multicast request and identify the priorities of the descriptors, and put the descriptors into the corresponding priority queues according to the priorities;

[0032] Arbitrate the descriptors in the priority queue in combination with the Qbv gate status, generate unicast / multicast arbitration results, and send the unicast / multicast arbitration results to the shared cache; and read the output frames in the shared cache into the output processing module through the secondary crossbar module for processing;

[0033] Among them, the Qbv gate status is that the queue is allowed to cross-transmit when the descriptors are opened in two consecutive time slots according to the Qbv gate control list; specifically: adopt the method of pre-reading one item, and the actual closing time of each state is calculated by the actual scheduling module according to the current gate control state, the next state and their respective end times, so as to maximize the use of bandwidth.

[0034] Furthermore, the running steps of the Qbv gate control list are as follows:

[0035] Step A, send a round start signal and calculate the start time of the next round;

[0036] Step B, read and execute the entries in the RAM of the input processing module one by one. This process will pre-read the next entry and generate the current state, the next state and their respective end times at the same time;

[0037] Step C, when the start time of the next round is reached, jump to Step A.

[0038] Furthermore, the descriptor is used to describe the input data frame, and the structure of the descriptor includes frame length, descriptor valid field, frame priority, frame timestamp, destination port of the frame, FIFO number where the frame is located, and flow number.

[0039] In a second aspect, the present invention further provides a transmission method for a time-sensitive network switch based on the SMS architecture, and the method includes:

[0040] Store the input data frame into the input cache queue;

[0041] Extract the key field information of the data frame and perform a table lookup operation to obtain the forwarding destination port and the flow identifier;

[0042] According to the flow identifier, through Qci token bucket filtering and CB redundancy removal operations, obtain a valid signal and generate a descriptor;

[0043] Control the reading out of the descriptor, send the descriptor to unicast / multicast arbitration, and send the data frame in the input cache queue to the shared cache through the primary crossbar;

[0044] Perform unicast and multicast comprehensive scheduling on descriptors based on Qbv gating shaping to generate arbitration results, including: the Qbv gating list obtains the AS synchronization time and opens and closes the gate, and determines whether the data frame can pass within the preset time; if it can pass, generate arbitration results; if it cannot pass, return to the Qbv gating list to obtain the AS synchronization time and open and close the gate;

[0045] Take out the AS output frame from the shared cache and send it to the corresponding output port through the secondary crossbar.

[0046] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0047] The present invention relates to a time-sensitive network switch and method based on the SMS architecture, which constructs a loosely coupled switch architecture that integrates TSN protocols (IEEE802.1AS, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB); specifically, it adopts the SMS (Switch-Memory-Switch) architecture as the switching architecture of the TSN switch, and supports the cut-through transmission mode, reducing the transmission delay; at the same time, it adopts the storage method of shared cache and supports cut-through, greatly enhancing the ability of each port to handle burst traffic. The SMS architecture of the present invention enables each TSN protocol to be reasonably arranged in the front and rear levels of the switch, with a certain degree of reusability. Description of the Drawings

[0048] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, form a part of this application, and do not limit the embodiments of the present invention. In the drawings:

[0049] Figure 1 It is an architecture diagram of a time-sensitive network switch based on the SMS architecture in Embodiment 1 of the present invention;

[0050] Figure 2 It is a data flow diagram of the transmission method of a time-sensitive network switch based on the SMS architecture in Embodiment 2 of the present invention; 2-1 is Figure 2 the upper half of, and 2-2 is Figure 2 the lower half of;

[0051] Figure 3 It is a diagram of the method for merging redundant synchronization times of the present invention;

[0052] Figure 4 It is an explanatory diagram of the Qbv gating list function of the present invention;

[0053] Figure 5 It is a diagram of the descriptor content of the present invention;

[0054] Figure 6 It is a diagram of the shared cache processing method of the present invention;

[0055] Figure 7 It is a diagram introducing the basic control principle of the Qbv gating list of the present invention. Specific embodiments

[0056] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the embodiments and the accompanying drawings. The illustrative embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0057] Based on the prior art, only the integration of the Qbv protocol is mentioned, and the integration of IEEE802.1AS, IEEECB, and IEEE802.1Qci with this architecture is not mentioned, and the adaptability to other TSN protocols is not clear. Some only support the 1588 time synchronization protocol, and there is no deterministic guarantee for time-critical services. It can be seen that there is no clear and comprehensive switch architecture for the current time-sensitive network to achieve low transmission delay.

[0058] Based on the above problems, the present invention constructs a loosely coupled switch architecture that integrates TSN protocols (IEEE802.1AS, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB); specifically, it adopts the SMS (Switch-Memory-Switch) architecture as the switching architecture of the TSN switch, and supports the cut-through transmission mode, reducing the transmission delay; at the same time, the shared cache storage method is adopted to enhance the ability of each port to handle burst traffic. The SMS architecture of the present invention enables each TSN protocol to be reasonably arranged in the front and rear stages of the switch, with certain reusability.

[0059] Among them, the SMS architecture is a switching architecture including a front-stage crossbar, an intermediate cache, and a rear-stage crossbar.

[0060] Specifically, the switch of the present invention includes an input processing module, a descriptor control module, a shared buffer management module, a first-level crossbar module, a unicast / multicast arbitration module, a second-level crossbar module, a shared buffer module, an AS (IEEE802.1AS) time synchronization module, an output processing module, etc.; the input processing module includes a Qci (IEEE802.1Qci) token bucket unit, a CB (IEEE802.1CB) redundancy removal unit, etc.; the unicast / multicast arbitration module includes a Qbv (IEEE802.1Qbv) gating list module. Among them, the first-level crossbar module is a fully connected cross-switch matrix for descriptors; the second-level crossbar module is a fully connected cross-switch matrix for output frames.

[0061] The AS time synchronization module provides accurate switch gate times for the Qbv gating list module, thereby affecting the result of unicast / multicast arbitration and indirectly ensuring the determinism and real-time performance of critical services.

[0062] The AS time synchronization module adopts an AS time synchronization proxy mechanism. If the upstream node times out in sending a synchronization frame, a timeout status is added to the sending module, and thus the upstream node is proxied to send a synchronization frame to the downstream.

[0063] As Figure 3 shown, Figure 3 is a diagram of a method for merging redundant synchronization times of the present invention. If neither of the two time domains times out, the synchronization time of domain 0 is selected as the synchronization time; if one of the synchronization domains times out, the synchronization time of the domain that does not time out is selected as the synchronization time; if both time out, the synchronization time of domain 0 is selected as the synchronization time.

[0064] The Qbv gating list module generates corresponding switch gate signals, thereby shielding or allowing the arbitration requests of the corresponding descriptor queues, affecting the unicast / multicast arbitration result, and its action on the unicast / multicast arbitration module is as Figure 4 shown.

[0065] The Qbv gating list allows the queue to perform cross-slot transmission when the door is opened for two consecutive time slots at this priority. A method of pre-reading one item is adopted, and in the actual scheduling module, the actual closing time of each state is calculated based on the current gating state, the next state, and their respective end times, so as to maximize the utilization of bandwidth. As Figure 7As shown (where O represents door opening and C represents door closing), when time slot 2 arrives, first, according to all door opening priorities, the frame with a priority of 5 is output first. After that, since the fourth queue opens in both time slots 2 and 3, the frame with a priority of 4 will be able to be transmitted across two time slots. Since the remaining time in time slot 3 is not enough to transmit another frame with a priority of 4, the shorter frame with a priority of 1 will be transmitted. In time slot 4, even if a higher-priority frame is to be transmitted, it has to wait for the previous frame to complete transmission.

[0066] The Qci token bucket unit discards frames that do not meet the traffic requirements, thereby improving the robustness of the network. It acts in the input processing module and is one of the criteria for determining whether a frame is discarded.

[0067] The Qci token bucket unit adds tokens by combining timestamp recording with fixed-point decimal multiplication and uniformly manages the token buckets of different traffic through random access memory RAM loading. The token bucket of a certain traffic will only perform a one-time token increase or decrease operation when it is used.

[0068] The CB redundancy removal unit has redundancy removal and proxy functions, and provides flow separation and R-TAG (Redundancy tag) removal functions for end nodes without CB functions. Redundancy removal is aimed at removing artificially generated redundant frames in the link and reducing the redundant bandwidth occupancy. The CB redundancy removal function acts in the input processing module of the switch and is one of the criteria for determining whether a frame is discarded.

[0069] Embodiment 1

[0070] As Figure 1 shown, a time-sensitive network switch based on the SMS architecture according to the present invention forms a pre-switching stage and a post-switching stage based on the SMS architecture; data frames enter the shared cache module through the pre-switching stage and are output through the post-switching stage; the SMS architecture includes a first-level crossbar module and a second-level crossbar module; a first-level crossbar module is arranged in front of the shared cache module, and a second-level crossbar module is arranged behind the shared cache module;

[0071] The first-level crossbar module and the modules before it are used as the pre-switching stage, and the second-level crossbar module and the modules after it are used as the post-switching stage. This arrangement makes the insertion of the TSN protocol more flexible. The TSN protocol cluster adopted in the design of the present invention includes the IEEE802.1AS protocol, IEEE802.1Qbv, IEEE802.1Qci, and IEEECB protocol.

[0072] The switch includes:

[0073] An input processing module, which is used to store the input data frame into the input buffer queue; and perform keyword field information extraction and look-up table operations on the data frame to obtain the forwarding destination port and the flow identifier; according to the flow identifier, through Qci token bucket filtering and CB redundancy removal operations, obtain a valid signal and generate a descriptor;

[0074] A descriptor control module, which is used to control the reading of the descriptor of the ordinary frame from the input processing module and the reading of the descriptor of the AS output frame from the AS time synchronization module, and send them to the unicast multicast arbitration module for descriptor scheduling; and send the data frame in the input buffer queue to the shared buffer module through a first-level crossbar module;

[0075] A unicast multicast arbitration module, which is used to perform comprehensive unicast and multicast scheduling according to the descriptor of the ordinary frame and the descriptor of the AS output frame, combined with Qbv gating shaping, to generate an arbitration result and an output frame descriptor; and send the arbitration result to the shared buffer, and send the output frame in the shared buffer to the output processing module for processing;

[0076] A shared buffer module, which is used to take out the AS output frame according to the data frame, AS output frame and arbitration result in the input buffer queue, and send it to the corresponding output port through a second-level crossbar module;

[0077] An AS time synchronization module, which is used to provide AS time synchronization for each module and is arranged in parallel with the data frame flow direction.

[0078] An output processing module, which is used to mark the AS timestamp for the output frame according to the output frame descriptor and take out the AS output frame, and send it to the AS time synchronization module; and correct and output the output frame; the correction includes: adding a VLAN TAG (VLAN label) and removing the VLAN TAG operation according to the port information, changing the DMAC field of the frame with the requirement of separating the redundancy removal flow (CB flow) by looking up the table, and adding an R-TAG field.

[0079] As a further implementation, the switch further includes a Qci token bucket unit, a CB redundancy removal unit and a Qbv unit;

[0080] A Qci token bucket unit, which is used to find the corresponding token bucket according to the flow identifier (i.e., flow id) generated by the look-up table operation to reduce the impact of burst traffic on the switch; specifically, by recording the timestamp and increasing the token in combination with the fixed-point decimal multiplication method, and uniformly managing the token buckets of different traffic through RAM loading; and the token bucket of a certain traffic only performs a one-time token increase and decrease operation when it is used;

[0081] The CB de-redundancy unit is used to act as an agent for terminals without CB functions and to perform de-redundancy functions on member flows identified as the same combined flow; specifically, it removes redundant frames in the transmission link to reduce redundant bandwidth occupancy; and provides flow separation and R-TAG removal functions for nodes without CB de-redundancy functions. As a further implementation, the CB de-redundancy unit is respectively integrated in the input processing module and the output processing module. The input processing module generates a request to the CB de-redundancy unit, first de-redundancy of repeatedly sent member flows, and then de-redundancy of different member flows; the output processing module mainly provides R-TAG addition and R-TAG removal functions for terminals without CB functions.

[0082] The Qbv unit is used to act on the priority queue of the unicast multicast arbitration module to generate corresponding gating information to suppress or allow the corresponding priority descriptor to be arbitrated by the unicast multicast arbitration module.

[0083] As a further implementation, AS time synchronization adopts an AS time synchronization proxy mechanism. Specifically, if the upstream node times out to send the synchronization frame, a timeout state is added to the sending unit, so that the upstream node sends the synchronization frame to the downstream node on behalf of the upstream node.

[0084] As a further implementation, the AS time synchronization module includes a preprocessing unit, a timing unit, a sending unit, a receiving unit, a synchronization transfer unit and a link measurement unit;

[0085] The preprocessing unit is used to classify the clock domain of the data frame, timestamp it and remove the frames that do not conform to the AS format; extract the corresponding information according to different synchronization frames, and send the information to the subsequent receiving unit and link measurement unit; wherein: if it is a link measurement frame, it enters the link request and link response modules of the corresponding port, and these two modules are responsible for calculating the frequency deviation and link delay. If it is a synchronization frame, it enters the receiving module to obtain the update of the upstream receiving time and the frequency deviation of the master node and the node, and enters the synchronization transfer module after receiving the complete synchronization frame sync and the synchronization follow-up frame followup.

[0086] Receiving unit: obtains the update of upstream receiving time and frequency deviation according to the synchronization frame information extracted by the pre-processing unit, and transmits the receiving signal to the synchronization transfer unit;

[0087] Synchronous transfer unit: transmits synchronization information to the timing unit and the sending unit according to the configuration;

[0088] The timing unit is used to compensate for the loss of the intermediate variable calculation delay, by adding the master node start time, the synchronization correction value and the link delay to obtain the upstream synchronization time based on the master node clock; the master node clock is added with the calculation delay to obtain the final synchronization point;

[0089] A sending unit, configured to propagate a synchronization frame according to the frequency of the received synchronization frame or send at its own fixed frequency; if a synchronization frame has not been received for three consecutive upstream sending frequencies, re-send to the downstream using the frame information received last time; and configured to send a data frame to the downstream, place it in a fixed buffer queue in the shared buffer, and generate a corresponding descriptor and send it to the descriptor queue of the corresponding port of the unicast / multicast arbitration;

[0090] A link measurement unit, configured to calculate the frequency offset and link delay.

[0091] As a further implementation, a unicast / multicast arbitration module, configured to perform unicast and multicast comprehensive scheduling according to the descriptors of ordinary frames and the descriptors of AS output frames, in combination with Qbv gating shaping, generate an arbitration result and an output frame descriptor; and send the arbitration result to the shared buffer, and send the output frame in the shared buffer to the output processing module for processing, specifically including:

[0092] Generate a unicast / multicast request according to the descriptors of ordinary frames and the descriptors of AS output frames;

[0093] Poll the descriptors sent from each port according to the unicast / multicast request and identify the priority of the descriptors, and place the descriptors in the corresponding priority queue according to the priority;

[0094] Arbitrate the descriptors in the priority queue in combination with the Qbv gate state, generate a unicast / multicast arbitration result, and send the unicast / multicast arbitration result to the shared buffer; and read the output frame in the shared buffer to the output processing module through a secondary crossbar module for processing;

[0095] Among them, the Qbv gate state is that the queue is allowed to cross-transmit when the descriptors' priority allows the queue to open the door for two consecutive time slots according to the Qbv gating list; specifically: adopt a way of pre-reading one item, and the actual scheduling module calculates the actual closing time of each state according to the current gate state, next state and their respective end times, so as to maximize the utilization of bandwidth.

[0096] As a further implementation, the running steps of the Qbv gating list are as follows:

[0097] Step A, send a round start signal and calculate the start time of the next round;

[0098] Step B, read the entries in the RAM of the input processing module one by one and execute them. This process will pre-read the next entry and generate the current state, next state and their respective end times at the same time;

[0099] Step C, when the start time of the next round is reached, jump to Step A.

[0100] As a further implementation, the descriptor is used to describe the input data frame. The structure of the descriptor includes frame length (Length), descriptor valid field (Valid), frame priority (Pri), frame timestamp (Timestamp), destination port of the frame (Dport), FIFO number where the frame is located (Fifonumber), and stream number (Sid), as Figure 5 shown.

[0101] Embodiment 2

[0102] As Figure 2 shown, the difference between this embodiment and Embodiment 1 is that this embodiment provides a transmission method for a time-sensitive network switch based on the SMS architecture. The method includes:

[0103] Step 1, input processing: Store the input data frame into the input buffer queue; extract keyword field information from the data frame and perform a table lookup operation to obtain the forwarding destination port and the flow identifier; according to the flow identifier, perform Qci token bucket filtering and CB redundancy removal operations to obtain a valid signal and generate a descriptor;

[0104] Step 1 specifically includes:

[0105] One copy of the data frame entering the switch port enters the input processing module, and at the same time, a copy enters the AS time synchronization module. Apply for a cache for the shared cache management to obtain the number of the shared cache FIFO.

[0106] Judge whether the frame needs to add a VlanTag (VLAN tag) according to the port characteristics, and at the same time send the frame into the frame buffer FIFO. Query the FDB (Filtering Database) table according to the VID (vlanid) of the frame to obtain the destination address of the in-domain broadcast and update the symbol bit indicating whether this frame is received by this port. Query the forwarding table and the flow id table to obtain the corresponding destination port number and flow id number, and generate learning flag information.

[0107] Obtain the flag indicating whether the frame can pass through through the Qci token bucket module and the CB module.

[0108] Obtain the descriptor according to the above steps and write it into the descriptor FIFO, and generate relevant requests for mac address learning.

[0109] The detailed steps are as follows:

[0110] Step 1.1: Information extraction and table lookup operation

[0111] Step 1.1.1: The data frame enters the input processing module for extracting keyword field information. To associate the query of the data frame with the field information of the data frame, the keyword fields are accumulated to obtain a hash value, and the information stored at the corresponding address in the RAM is matched.

[0112] Step 1.1.2: Send a request signal of fifonumber (data is stored in the shared cache in the cache queue fifo, and each fifo has its unique number) to the shared cache management module to obtain the corresponding fifonumber.

[0113] Step 1.1.3: As shown in Table 1, the task of Table 1 is to perform the filtering function of the FDB (Filtering Database) table in the protocol. Use the hash algorithm to find the corresponding table entry, that is, the table entry corresponding to this VID (vlanid). The highest bit represents whether the port receives this vid. If it is 1, it can be received. If it is 0, it will be discarded later. The remaining bits represent the multicast destination port.

[0114] Table 1

[0115]

[0116] Step 1.1.4: Obtain the hash value according to the dmac and vid or the ip field and vid, and look up the flow id (flow identifier) through this hash value in the table.

[0117] Step 1.2: Qci token bucket and CB operations

[0118] Step 1.2.1: After obtaining the data frame length field, read the RAM storing the Qci token number and timestamp. Calculate the updated token number according to the read Qci token and timestamp and compare it with the current frame length. If the token number is less than the data frame length, set the valid (descriptor valid flag) field of the descriptor to invalid, and at the same time write the updated token number and the current timestamp into the RAM. If the updated token number is greater than the data frame length, set the relevant valid fields to valid, and write the token number minus the frame length token and the current timestamp into the RAM.

[0119] Step 1.2.2: Use a RAM with a depth of N to store each token bucket parameter, and cooperate with the timestamp and multiplier to achieve token growth. Each time the data is taken out from the RAM, record the time of taking it out according to the local time. Calculate the time difference between this time of taking it out and the time of taking it out when it was last stored, and then multiply it by the token bucket injection rate to obtain the token increase number during this period.

[0120] Step 1.2.3: After obtaining the stream ID (stream identifier), first remove frames with consecutive identical sequence numbers through the independent recovery function, and then use the sequence recovery module to determine whether the frame is a redundant frame. If so, set the descriptor valid to invalid. The state machine in the CB redundancy removal unit will combine the results of the two redundancy removals to output the final judgment result and enable signal. At the same time, the fault detection module will periodically read the statistical data of each stream in the sequence recovery module and determine whether a fault has occurred during this period.

[0121] Step 1.3: Generate descriptors

[0122] Step 1.3.1: After redundancy removal by the CB redundancy removal unit, descriptors are generated and written into the descriptor FIFO (cache queue). The structure of the descriptor is as Figure 5 shown. The structure of the descriptor includes frame length (Length), descriptor valid field (Valid), frame priority (Pri), frame timestamp (Timestamp), destination port of the frame (Dport), FIFO number where the frame is located (Fifonumber), and stream number (Sid).

[0123] Step 2: Descriptor control and learning aging configuration

[0124] Step 2.1: The descriptor control module reads the descriptors from the input processing module, sends them to the unicast / multicast arbitration module for descriptor scheduling. After reading the data frame ends, it clears the occupancy information and feeds it back to the shared cache management module, clearing the preoccupied FIFO. According to the descriptor information, the frame is sent to the shared cache module through a first-level crossbar module. Specifically, it includes:

[0125] Step 2.1.1 Observe whether the descriptor of this port is non-empty. If non-empty, read out this descriptor; otherwise, remain in the IDLE (idle state).

[0126] Step 2.1.2 Determine the validity of the data frame according to the valid field of the descriptor. If valid, read the frame from the cache FIFO of the input processing to the corresponding FIFO of the shared cache according to the cache ID (number) of the descriptor.

[0127] Step 2.1.3 When the data frame tail flag is found, stop reading and generate a return FIFO signal and a return cache ID.

[0128] Step 2.1.4 Enter Step 2.1.1.

[0129] Step 2.2: For the learning aging configuration module, it receives the learning content sent from each port and performs corresponding feedback learning, update, and aging operations on the RAM or register bank according to the learning content.

[0130] Step 3: Shared Cache Management

[0131] As Figure 6 shown. Busy_intern reflects the occupancy of the corresponding shared cache fifo. If it is occupied, the corresponding bit is 1. When the occupancy is eliminated, that bit is set to 0. There are as many bits as there are fifos.

[0132] Step 3 specifically includes:

[0133] Step 3.1: Poll the FIFO pre-requests of the four ports. If there is a request, respond. In the same situation, give priority to responding to the borrowed FIFO, and give secondary priority to responding to the returned FIFO signal.

[0134] After the response, continue polling and repeat Step 3.1.

[0135] Step 4: AS Time Synchronization

[0136] For the data frame entering the AS time synchronization module, first classify the clock domain of the data frame, timestamp it, and eliminate the frames that do not conform to the AS format; make corresponding configurations according to different synchronization frames, and send the configuration information to the subsequent sending unit and timing unit; among them: if it is a link measurement frame, it enters the link request and link response modules of the corresponding port, and these two modules are responsible for calculating the frequency offset and link delay. If it is a synchronization frame, it enters the receiving module to obtain the upstream reception time and the update of the frequency offset between the master node and this node. After receiving the complete synchronization frame sync and synchronization follow-up frame followup, it enters the synchronization transfer module.

[0137] Step 4.2: The timing unit needs to compensate for the loss of the intermediate variable calculation delay. By adding the start time of the master node, the synchronization correction value, and the link delay, the upstream synchronization time based on the master node clock is obtained; adding the calculation delay to the master node clock to obtain the final synchronization point;

[0138] Step 4.3: The sending unit propagates the synchronization frame according to the frequency of the received synchronization frame or sends it at its own fixed frequency; if the upstream transmission frequency of the synchronization frame has not been received for three consecutive times, the frame information received last time is re-sent downstream; and it is used to send data frames downstream, which are put into the fixed cache queue in the shared cache, and the corresponding descriptors are generated and sent to the descriptor queue of the corresponding port of the unicast / multicast arbitration.

[0139] Step 5: Unicast / Multicast Arbitration and Qbv Gating List

[0140] The basic control principle of the Qbv gating list is as Figure 6As shown, a period of time is divided into multiple time slots, where only specific priority queues can pass through specific time slots while blocking other priority queues, so the purpose of protecting critical services can be achieved.

[0141] Step 5.1: Unicast-multicast arbitration first polls the descriptors sent from each port and identifies their priorities, and places them in the corresponding priority queues according to their priorities.

[0142] Step 5.2: Thereafter, the unicast-multicast arbitration module combines the Qbv gate state, arbitrates the descriptors in the descriptor queue, generates a unicast-multicast arbitration result, and reads the frames in the shared cache to the output processing module through the secondary crossbar.

[0143] The Qbv gate state is obtained through Qbv operation. The operation steps of Qbv are as follows:

[0144] Step A: Send a round start signal and calculate the start time of the next round;

[0145] Step B: Read the entries in the RAM of the input processing module one by one and execute them. This process will pre-read the next entry and generate the current state, next state, and their respective end times at the same time;

[0146] Step C: When the start time of the next round is reached, jump to Step A.

[0147] Step 6: Output processing

[0148] The function of the output processing module is to timestamp and implement the function of modifying the dmac address of the CB redundancy removal unit, adding and removing R-TAG, and adding and removing VLANTAG.

[0149] Step 6.1: Timestamp and send the timestamp to the AS time synchronization module; since all data frames including the AS time synchronization frame are output from the output processing module, the timestamping function is implemented in the output processing module;

[0150] Step 6.2: If it is a frame with a flow separation requirement, look up the table and modify its DMAC.

[0151] Step 6.3: Judge whether it needs to remove VLANTAG and add R-TAG according to the descriptor, and perform corresponding operations.

[0152] Step 6.4: Send the corrected data frame out of the port.

[0153] The present invention adopts a shared cache-based switching architecture based on the SMS architecture, supports cut-through, and greatly enhances the low latency of the switch and its ability to handle burst traffic. At the same time, the main protocol clusters of TSN are reasonably arranged, reflecting the reusability of the switching architecture.

[0154] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0155] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0156] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that realizes the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0158] The specific embodiments described above further elaborate on the objective, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A time-sensitive network switch based on the SMS architecture, characterized in that, the switch forms a pre-switching stage and a post-switching stage based on the SMS architecture; data frames enter the shared buffer module through the pre-switching stage and are output through the post-switching stage; the SMS architecture includes a first-level crossbar module and a second-level crossbar module; the switch includes: an input processing module, configured to store the input data frames into an input buffer queue; and perform keyword field information extraction and look-up table operations on the data frames to obtain the forwarding destination port and the flow identifier; according to the flow identifier, perform Qci token bucket filtering and CB redundancy removal operations to obtain a valid signal and generate a descriptor; a descriptor control module, configured to control reading the descriptors of ordinary frames from the input processing module and reading the descriptors of AS output frames from the AS time synchronization module, and sending them to the unicast / multicast arbitration module for descriptor scheduling; and sending the data frames in the input buffer queue to the shared buffer module through the first-level crossbar module; a unicast / multicast arbitration module, configured to perform comprehensive unicast and multicast scheduling in combination with Qbv gating shaping according to the descriptors of ordinary frames and the descriptors of AS output frames to generate an arbitration result and an output frame descriptor; and sending the arbitration result to the shared buffer, and sending the output frames in the shared buffer to the output processing module for processing; a shared buffer module, configured to take out the AS output frames according to the data frames in the input buffer queue, the AS output frames and the arbitration result, and send them to the corresponding output ports through the second-level crossbar module; a first-level crossbar module is arranged in front of the shared buffer module, and a second-level crossbar module is arranged behind the shared buffer module; an AS time synchronization module, configured to provide AS time synchronization for each module.

2. The time-sensitive network switch based on the SMS architecture according to claim 1, characterized in that, the switch further includes an output processing module, configured to timestamp the output frames with AS time according to the output frame descriptors and take out the AS output frames, and send them to the AS time synchronization module; and correct and output the output frames; the correction includes: adding a VLAN TAG and removing a VLAN TAG operation according to the port information, changing the DMAC field of the frames with redundancy removal flow separation requirements by looking up a table, and adding an R-TAG field.

3. The time-sensitive network switch based on the SMS architecture according to claim 1, characterized in that, the switch further includes a Qci token bucket unit, a CB redundancy removal unit and a Qbv unit; the Qci token bucket unit is configured to find the corresponding token bucket according to the flow identifier generated by the look-up table operation to reduce the impact of burst traffic on the switch; specifically, by recording timestamps and adding tokens in combination with fixed-point fractional multiplication, and uniformly managing the token buckets of different traffic through RAM loading; and the token bucket of a certain traffic only performs a one-time token increase or decrease operation when it is used. CB de-redundancy unit, used to act as an agent for terminals without CB function and to perform de-redundancy function on member flows identified as the same combined flow; specifically, to remove redundant frames in the transmission link to reduce redundant bandwidth occupancy; and to provide flow separation and R-TAG removal functions for nodes without CB de-redundancy function; The Qbv unit is used to act on the priority queue of the unicast multicast arbitration module to generate corresponding gating information to suppress or allow the corresponding priority descriptor to be arbitrated by the unicast multicast arbitration module.

4. The SMS architecture-based time-sensitive network switch according to claim 1, It is characterized in that The first-level crossbar module is a crossbar switch matrix that fully connects the descriptors; The secondary crossbar module is a crossbar switch matrix that fully connects the output frames.

5. The SMS architecture-based time-sensitive network switch according to claim 1, It is characterized in that The AS time synchronization adopts the AS time synchronization agent mechanism. Specifically, if the upstream node times out when sending the synchronization frame, a timeout state is added to the sending unit, so that the upstream node sends the synchronization frame to the downstream node on behalf of the upstream node.

6. The SMS architecture-based time-sensitive network switch according to claim 5, It is characterized in that The AS time synchronization module includes a preprocessing unit, a timing unit, a sending unit, a receiving unit, a synchronization transfer unit and a link measurement unit; The preprocessing unit is used to classify the clock domain of the data frame, add time stamps and remove frames that do not conform to the AS format; extract corresponding information according to different synchronization frames, and send the information to the subsequent receiving unit and link measurement unit; Receiving unit: obtains the update of upstream receiving time and frequency deviation according to the synchronization frame information extracted by the pre-processing unit, and transmits the receiving signal to the synchronization transfer unit; Synchronous transfer unit: transmits synchronization information to the timing unit and the sending unit according to the configuration; The timing unit is used to compensate for the loss of the intermediate variable calculation delay, by adding the master node start time, the synchronization correction value and the link delay to obtain the upstream synchronization time based on the master node clock; the master node clock is added with the calculation delay to obtain the final synchronization point; The sending unit is used to propagate the synchronization frame or send it at its own fixed frequency according to the frequency of receiving the synchronization frame; if the synchronization frame is not received at the upstream sending frequency for three consecutive times, the frame information received last time is resent to the downstream; and the data frame is sent to the downstream, which is placed in the fixed cache queue in the shared cache, and the corresponding descriptor is generated and sent to the descriptor queue of the corresponding port of unicast multicast arbitration; Link measurement unit, used to calculate frequency deviation and link delay.

7. The SMS architecture-based time-sensitive network switch according to claim 1, It is characterized in that The unicast multicast arbitration module is used to perform unicast and multicast comprehensive scheduling according to the descriptor of the common frame and the descriptor of the AS output frame, combined with Qbv gating shaping, to generate an arbitration result and an output frame descriptor; Send the arbitration result to the shared cache, and send the output frame in the shared cache to the output processing module for processing, specifically including: Generate unicast / multicast requests according to the descriptors of ordinary frames and the descriptors of AS output frames; Poll the descriptors sent by each port according to the unicast / multicast requests and identify the priorities of the descriptors, and put the descriptors into the corresponding priority queues according to the priorities; Arbitrate the descriptors in the priority queues in combination with the Qbv gate status, generate unicast / multicast arbitration results, and send the unicast / multicast arbitration results to the shared cache; send the output frames in the shared cache to the output processing module for processing; Among them, the Qbv gate status is to allow the queue to cross-transmit when the descriptors have consecutive two time slots of priority to open the door according to the Qbv gate control list; specifically: adopt the way of pre-reading one item, and calculate the actual closing time of each state according to the current gate control state, the next state and their respective end times, so as to maximize the use of bandwidth.

8. A time-sensitive network switch based on the SMS architecture according to claim 7, characterized in that the running steps of the Qbv gate control list are: Step A, send a round start signal and calculate the start time of the next round; Step B, read and execute the entries in the RAM of the input processing module one by one. This process will pre-read the next entry and generate the current state, the next state and their respective end times at the same time; Step C, when reaching the start time of the next round, jump to Step A.

9. A time-sensitive network switch based on the SMS architecture according to claim 1, characterized in that the descriptor is used to describe the input data frame, and the structure of the descriptor includes frame length, descriptor valid field, frame priority, frame timestamp, destination port of the frame, FIFO number where the frame is located, and flow number.

10. A transmission method of a time-sensitive network switch based on the SMS architecture according to any one of claims 1 to 9, characterized in that the method includes: Store the input data frame in the input cache queue; Extract keyword field information from the data frame and perform a table lookup operation to obtain the forwarding destination port and flow identifier; According to the flow identifier, filter through the Qci token bucket and perform CB redundancy removal operations to obtain a valid signal and generate a descriptor; Control the readout of the descriptor, send the descriptor to unicast / multicast arbitration, and send the data frame in the input cache queue to the shared cache through a first-level crossbar; Perform unicast / multicast comprehensive scheduling on the descriptor based on Qbv gate shaping to generate an arbitration result; including: the Qbv gate control list obtains the AS synchronization time and opens and closes the door, and judges whether the data frame can pass within a preset time; if it can pass, an arbitration result is generated; if it cannot pass, return to the Qbv gate control list to obtain the AS synchronization time and open and close the door; Take out the AS output frame from the shared cache and send it to the corresponding output port through a second-level crossbar.

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