One-time programmable reset memory array and its formation method

Abstract

A one-time programmable reset memory array and its formation method are disclosed. The method includes: providing a substrate, the substrate including a base and an active region; forming a word line gate structure on the active region, the word line gate structure including a plurality of first implantation portions, second implantation portions, and no implantation portions; forming source and drain doped layers in the active region; forming a first implantation layer in the first implantation portions, the first implantation layer containing first ions; forming a second implantation layer in the second implantation portions, the second implantation layer containing second ions, the first ions and the second ions having different electrical types. Since the first ions and the second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first implantation layer and the second implantation layer can represent two types of data information. Combined with the fact that the no implantation portions can also represent one type of data information, this allows a memory cell in the one-time programmable reset memory array to have three types of data information storage options, thereby effectively increasing the storage capacity of the memory array.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a one-time programmable reset memory array and a method for forming the same. Background Technology

[0002] Embedded non-volatile memory (ENVM) technology has been adopted in applications such as post-silicon verification, memory repair, in-circuit field testing, and secure ID storage. ENVM is also a critical component for self-healing applications, where information about time-related failure mechanisms (such as circuit aging) must be retained during system power-down cycles. One-time programmable (OTP) memory has been widely used for memory repair in standard logic processes.

[0003] One-time programmable memory (IPM) is a read-only memory, named so because it can only be programmed once. When manufactured, IPM typically stores only 0s or 1s, allowing users to program it according to their needs and write user data. Due to its simple structure, ease of use, and low cost, IPM is widely used in microcontrollers (MCUs) and other chips, replacing traditional electrically erasable programmable memory (EPROM).

[0004] However, existing one-time programmable memory arrays still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a one-time programmable reset memory array and a method for forming the same, so as to increase the storage capacity of data information.

[0006] To address the aforementioned problems, the present invention provides a method for forming a one-time programmable reset memory array, comprising: providing a substrate, the substrate including a base and an active region located on the base; forming a word line gate structure on the substrate, the word line gate structure covering a portion of the top surface of the active region, the word line gate structure including a plurality of first implantation portions, a plurality of second implantation portions, and a plurality of non-implanted portions; forming a source / drain doped layer in the active region, the source / drain doped layer containing first ions; forming a first implantation layer in the first implantation portions, the first implantation layer containing the first ions; forming a second implantation layer in the second implantation portions, the second implantation layer containing second ions, wherein the electrical types of the first ions and the second ions are different.

[0007] Optionally, the active region includes a first active portion parallel to the first direction and a plurality of second active portions parallel to the second direction. The first active portion and the plurality of second active portions are arranged in an intersecting pattern, and the intersection of the first active portion and the second active portion is a common active portion. The first direction is perpendicular to the second direction.

[0008] Optionally, the word line grid structure is parallel to the first direction, and the word line grid structure covers the first active portion; the first injection portion, the second injection portion, and the non-injection portion are respectively located on the first active portion between adjacent common active portions.

[0009] Optionally, a source / drain doped layer is formed within the exposed second active portion.

[0010] Optionally, the first implantation layer and the source / drain doped layers are formed simultaneously.

[0011] Optionally, the method for forming the source / drain doped layer and the first implantation layer includes: forming a first sacrificial layer on the substrate, the first sacrificial layer exposing the top surface of the second active portion and the top surface of the first implantation portion; implanting the first ions using the first sacrificial layer as a mask to form the source / drain doped layer and the first implantation layer.

[0012] Optionally, the method for forming the second implantation layer includes: forming a second sacrificial layer on the substrate, the second sacrificial layer exposing the top surface of the second implantation portion; implanting the second ions using the second sacrificial layer as a mask to form the second implantation layer.

[0013] Optionally, the word line grid structure includes: a grid dielectric layer, a word line grid layer located on the grid dielectric layer, and sidewalls located on the sidewalls of the grid dielectric layer and the word line grid layer.

[0014] Optionally, the method for forming the word line gate structure includes: forming a gate dielectric layer on the substrate; forming a word line gate material layer on the gate dielectric layer; patterning the gate dielectric layer and the word line material layer to form the gate dielectric layer and the word line gate layer; forming a sidewall material layer on the sidewalls of the gate dielectric layer and the word line gate layer, and on the top surface of the word line gate layer; and etching back the sidewall material layer until the top surface of the word line gate layer is exposed to form the sidewall.

[0015] Optionally, the first ion includes an N-type ion or a P-type ion; the second ion includes a P-type ion or an N-type ion.

[0016] Accordingly, the present invention also provides a one-time programmable reset memory array, comprising: a substrate, the substrate including a base and an active region located on the base; a word line gate structure located on the substrate, the word line gate structure covering a portion of the top surface of the active region, the word line gate structure including a plurality of first implantation portions, a plurality of second implantation portions and a plurality of non-implanted portions; a source / drain doped layer located in the active region, the source / drain doped layer containing first ions; a first implantation layer located in the first implantation portions, the first implantation layer containing the first ions; and a second implantation layer located in the second implantation portions, the second implantation layer containing second ions, wherein the electrical types of the first ions and the second ions are different.

[0017] Optionally, the active region includes a first active portion parallel to the first direction and a plurality of second active portions parallel to the second direction. The first active portion and the plurality of second active portions are arranged in an intersecting pattern, and the intersection of the first active portion and the second active portion is a common active portion. The first direction is perpendicular to the second direction.

[0018] Optionally, the word line grid structure is parallel to the first direction, and the word line grid structure covers the first active portion; the first injection portion, the second injection portion, and the non-injection portion are respectively located on the first active portion between adjacent common active portions.

[0019] Optionally, the source / drain doped layer is located in the second active region.

[0020] Optionally, the word line grid structure includes: a grid dielectric layer, a word line grid layer located on the grid dielectric layer, and sidewalls located on the sidewalls of the grid dielectric layer and the word line grid layer.

[0021] Optionally, the first ion includes an N-type ion or a P-type ion; the second ion includes a P-type ion or an N-type ion.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the method for forming a one-time programmable reset memory array according to the technical solution of the present invention, the word line gate structure is divided into several first injection portions, several second injection portions, and several non-injection portions. A first injection layer is formed in the first injection portion, containing first ions. A second injection layer is formed in the second injection portion, containing second ions. The electrical types of the first ions and the second ions are different. Since the first ions and the second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first injection layer and the second injection layer can represent two types of data information. In addition, the non-injection portions can also represent one type of data information. This allows a memory cell in the one-time programmable reset memory array to have three data information storage options (i.e., reset, and selection of two or more data information states), namely data information "0", "1", and "2", thereby effectively increasing the storage capacity of the one-time programmable reset memory array.

[0024] Furthermore, the first implantation layer and the source / drain doped layer are formed simultaneously. By forming the first implantation layer and the source / drain doped layer simultaneously, the photomask used to form the first implantation layer can be utilized, eliminating the need for a dedicated additional implantation doping photolithography step and corresponding photomask for forming the first implantation layer. This effectively simplifies the process and reduces manufacturing costs.

[0025] The one-time programmable reset memory array of the present invention includes: a word line gate structure located on the substrate, the word line gate structure covering a portion of the top surface of the active region, the word line gate structure including a plurality of first injection portions, a plurality of second injection portions, and a plurality of non-injection portions; a first injection layer located within the first injection portions, the first injection layer containing the first ions; and a second injection layer located within the second injection portions, the second injection layer containing the second ions, the electrical types of the first ions and the second ions being different. Since the first ions and the second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first injection layer and the second injection layer can represent two types of data information. Combined with the fact that the non-injection portions can also represent one type of data information, this allows a memory cell in the one-time programmable reset memory array to have three data information storage options, namely data information "0", "1", and "2", thereby effectively increasing the storage capacity of the one-time programmable reset memory array. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a one-time programmable reset memory array;

[0027] Figures 2 to 15This is a schematic diagram of the structure of each step in the method for forming a one-time programmable reset memory array in an embodiment of the present invention. Detailed Implementation

[0028] As described in the background section, existing one-time programmable reset memory arrays still have many problems in their fabrication process. These will be explained in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of a one-time programmable reset memory array.

[0030] Please refer to Figure 1 A one-time programmable reset memory array includes: a substrate, the substrate including a base and an active region (not shown) located on the base; a word line gate structure 101 located on the substrate, the word line gate structure 101 covering a portion of the top surface of the active region, the word line gate structure 101 including a plurality of implanted portions 101a and a plurality of unimplanted portions 101b; a source / drain doped layer 102 located within the active region, the source / drain doped layer 102 having a first ion; and an implanted layer 103 located within the implanted portions 101a, the implanted layer 103 having a second ion.

[0031] In this embodiment, the injection section 101a and the non-injection section 101b are arranged alternately as an example.

[0032] In this embodiment, in the one-time programmable reset memory array, the threshold voltage Vt in the transistor structure is adjusted by injecting the second ion into the word line gate structure 101, thereby characterizing different data information.

[0033] However, since the second ions in all the implanted regions 101a of the word line gate structure 101 are the same, the adjustment of the implanted layer 103 can only represent one type of data information. Furthermore, since all the non-implanted portions 101b can also only represent one type of data information, a single memory cell in the one-time programmable reset memory array has three data information storage options: data information "1" and "0". Therefore, the storage capacity of the data information in the one-time programmable reset memory array needs to be improved.

[0034] Based on this, the present invention provides a one-time programmable reset memory array and its formation method. By dividing the word line gate structure into several first injection portions, several second injection portions, and several non-injection portions, a first injection layer is formed in the first injection portions, containing first ions. A second injection layer is formed in the second injection portions, containing second ions, and the electrical types of the first ions and second ions are different. Since the first ions and second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first and second injection layers can represent two types of data information. Combined with the fact that the non-injection portions can also represent one type of data information, the entire one-time programmable reset memory array can represent three types of data information: "0", "1", and "2", thereby effectively increasing the storage capacity of the one-time programmable reset memory array.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 15 This is a schematic diagram of the structure of each step in the method for forming a one-time programmable reset memory array in an embodiment of the present invention.

[0037] Please refer to Figures 2 to 4 , Figure 3 yes Figure 2 Schematic diagram of the cross section along line AA. Figure 4 yes Figure 2 A schematic diagram of a cross-section along the BB line in China is provided, showing a substrate including a base 200 and an active region 201 located on the base 200.

[0038] In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown); and performing patterning processing on the initial substrate to form the substrate, wherein the substrate includes a base 200 and the active region 201 located on the base 200.

[0039] In this embodiment, the active region 201 includes a first active portion 201a parallel to the first direction X and a plurality of second active portions 201b parallel to the second direction Y. The first active portion 201a and the plurality of second active portions 201b are arranged intersectingly, and the intersection of the first active portion 201a and the second active portion 201b is a common active portion 201c. The first direction X is perpendicular to the second direction Y.

[0040] In this embodiment, the substrate is made of silicon; in other embodiments, the substrate may also be made of silicon-germanium.

[0041] Please refer to Figure 5 and Figure 6 , Figure 5 and Figure 3 The view orientation is consistent. Figure 6 and Figure 4 With the view orientation consistent, an isolation layer 202 is formed on the substrate, the isolation layer 202 covers the sidewall of the active region 201 and exposes the top surface of the active region 201.

[0042] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate, the initial isolation layer covering the active region 201; and performing a back etching process on the initial isolation layer until the top surface of the active region 201 is exposed, thereby forming the isolation layer 202.

[0043] In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0044] Please refer to Figure 7 and Figure 8 , Figure 8 yes Figure 7 A schematic cross-sectional view along the CC line shows that after the isolation layer 202 is formed, a word line gate structure 203 is formed on the substrate. The word line gate structure 203 covers part of the top surface of the active region 201. The word line gate structure 203 includes a plurality of first injection portions 203a, a plurality of second injection portions 203b, and a plurality of non-injection portions 203c.

[0045] In this embodiment, the word line grid structure 203 is parallel to the first direction X, and the word line grid structure 203 covers the first active portion 201a; the first injection portion 203a, the second injection portion 203b, and the non-injection portion 203c are respectively located on the first active portion 201a between adjacent common active portions 201c.

[0046] In this embodiment, the word line grid structure 203 includes: a grid dielectric layer (not shown), a word line grid layer (not shown) located on the grid dielectric layer, and sidewalls (not shown) located on the sidewalls of the grid dielectric layer and the word line grid layer.

[0047] The method for forming the word line gate structure 203 includes: forming a gate dielectric layer material layer (not shown) on the substrate; forming a word line gate material layer (not shown) on the gate dielectric material layer; patterning the gate dielectric material layer and the word line material layer to form the gate dielectric layer and the word line gate layer; forming a sidewall material layer (not shown) on the sidewalls of the gate dielectric layer and the word line gate layer, and on the top surface of the word line gate layer; and etching back the sidewall material layer until the top surface of the word line gate layer is exposed to form the sidewall.

[0048] In this embodiment, the gate oxide layer is made of silicon oxide; the word line gate layer is made of polysilicon; and the sidewalls are made of silicon nitride.

[0049] It should be noted that, in this embodiment, the division and arrangement of the first injection portion 203a, the second injection portion 203b, and the non-injection portion 203c in the word line grid structure 203 can be flexibly defined according to actual needs.

[0050] In one specific embodiment, the first injection section 203a, the second injection section 203b, and the non-injection section 203c are arranged alternately in sequence.

[0051] Please refer to Figures 9 to 12 , Figure 10 yes Figure 9 Schematic diagram of the cross section along the DD line. Figure 11 yes Figure 9 Schematic diagram of the cross section along the EE line. Figure 12 yes Figure 9 A schematic diagram of the cross-section along the FF line shows that after the word line gate structure 203 is formed, a source / drain doped layer 204 is formed in the active region 201, and the source / drain doped layer 204 contains first ions; a first implantation layer 205 is formed in the first implantation portion 203a, and the first implantation layer 205 contains the first ions.

[0052] In this embodiment, a source / drain doped layer is formed within the exposed second active portion 201b.

[0053] In this embodiment, the first implantation layer 205 and the source / drain doped layer 204 are formed simultaneously.

[0054] In this embodiment, the method for forming the source / drain doped layer 204 and the first implantation layer 205 includes: forming a first sacrificial layer (not shown) on the substrate, wherein the first sacrificial layer exposes the top surface of the second active portion 201b and the top surface of the first implantation portion 203a; and implanting the first ions using the first sacrificial layer as a mask to form the source / drain doped layer 204 and the first implantation layer 205.

[0055] In this embodiment, by forming the first implantation layer 205 and the source / drain doped layer 204 simultaneously, the photomask used when forming the source / drain doped layer 204 can be used to form the first implantation layer 205, eliminating the need for a dedicated additional implantation doping photolithography step and corresponding photomask for forming the first implantation layer 205, thereby effectively simplifying the process and reducing manufacturing costs.

[0056] In this embodiment, the first ion is an N-type ion; in other embodiments, the N-type ion may also be a P-type ion.

[0057] Thus, in this embodiment, a plurality of NMOS transistor structures connected in series along the first direction are formed.

[0058] Please refer to Figures 13 to 15 , Figure 14 yes Figure 13 Schematic diagram of the cross section along the GG line. Figure 15 yes Figure 13 A schematic diagram of a cross-section along the HH line shows that after the source / drain doped layer 204 and the first implantation layer 205 are formed, a second implantation layer 206 is formed in the second implantation portion 203b. The second implantation layer 206 contains a second ion, and the electrical types of the first ion and the second ion are different.

[0059] In this embodiment, the method for forming the second implantation layer 206 includes: forming a second sacrificial layer (not shown) on the substrate, the second sacrificial layer exposing the top surface of the second implantation portion 203b; implanting the second ions using the second sacrificial layer as a mask to form the second implantation layer.

[0060] It should be noted that in this embodiment, the formation of the second implantation layer 206 can be carried out simultaneously with the source and drain doping layers in other regions (not shown) on the chip. However, it is necessary to ensure that the electrical type of the dopant ions in the source and drain doping layers in other regions is the same as that of the second ions. This can eliminate the need for a dedicated additional implantation doping photolithography step and a corresponding photomask when forming the second implantation layer 206, thereby simplifying the process and reducing manufacturing costs.

[0061] In this embodiment, the second ion is a P-type ion; in other embodiments, when the first ion is a P-type ion, the second ion is an N-type ion.

[0062] In this embodiment, the word line gate structure 203 is divided into several first injection portions 203a, several second injection portions 203b, and several non-injection portions 203c. A first injection layer 205 is formed in the first injection portion 203a, containing first ions. A second injection layer 206 is formed in the second injection portion 203b, containing second ions. The electrical types of the first ions and the second ions are different. Since the first ions and the second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first injection layer 205 and the second injection layer 206 can represent two types of data information. In addition, the non-injection portions 203c can also represent one type of data information. This allows a single memory cell in the one-time programmable reset memory array to have three data information storage options (i.e., reset, and selection of two or more data information states), namely data information "0", "1", and "2", thereby effectively increasing the storage capacity of the data information in the one-time programmable reset memory array.

[0063] Accordingly, this invention also provides a one-time programmable reset memory array; please refer to [further details]. Figures 13 to 15 The device includes: a substrate, the substrate including a base 200 and an active region 201 located on the base 200; a word line gate structure 203 located on the substrate, the word line gate structure 203 covering a portion of the top surface of the active region 201, the word line gate structure 203 including a plurality of first implantation portions 203a, a plurality of second implantation portions 203b and a plurality of non-implanted portions 203c; a source / drain doped layer 204 located within the active region 201, the source / drain doped layer 204 containing first ions; a first implantation layer 205 located within the first implantation portions 203a, the first implantation layer 205 containing the first ions; and a second implantation layer 206 located within the second implantation portions 203b, the second implantation layer 206 containing second ions, wherein the electrical types of the first ions and the second ions are different.

[0064] In this embodiment, since the first ion and the second ion have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first injection layer 205 and the second injection layer 206 can represent two types of data information. In addition, the non-injection part 203c can also represent one type of data information, so that a storage cell in the one-programmable reset memory array has three data information storage options, namely data information "0", "1" and "2", thereby effectively increasing the storage capacity of data information in the one-programmable reset memory array.

[0065] In this embodiment, the active region 201 includes a first active portion 201a parallel to the first direction X and a plurality of second active portions 201b parallel to the second direction Y. The first active portion 201a and the plurality of second active portions 201b are arranged intersectingly, and the intersection of the first active portion 201a and the second active portion 201b is a common active portion 201c. The first direction X is perpendicular to the second direction Y.

[0066] In this embodiment, the word line grid structure 203 is parallel to the first direction X, and the word line grid structure 203 covers the first active portion 201a; the first injection portion 203a, the second injection portion 203b, and the non-injection portion 203c are respectively located on the first active portion 201a between adjacent common active portions 201c.

[0067] In this embodiment, the source / drain doped layer 204 is located in the second active portion 201b.

[0068] In this embodiment, the word line grid structure 203 includes: a grid dielectric layer, a word line grid layer located on the grid dielectric layer, and sidewalls located on the sidewalls of the grid dielectric layer and the word line grid layer.

[0069] In this embodiment, the first ion is an N-type ion and the second ion is a P-type ion; in other embodiments, the first ion may also be a P-type ion, and the corresponding second ion may be an N-type ion.

[0070] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a one-time programmable reset memory array, characterized in that, include: A substrate is provided, the substrate including a base and an active region located on the base; A word line gate structure is formed on the substrate, the word line gate structure covering a portion of the top surface of the active region, and the word line gate structure includes a plurality of first injection portions, a plurality of second injection portions, and a plurality of non-injection portions; A source / drain doped layer is formed in the active region, and the source / drain doped layer contains a first ion; A first injection layer is formed within the first injection portion, and the first injection layer contains the first ions; A second injection layer is formed within the second injection section, and the second injection layer contains a second ion, wherein the electrical type of the first ion is different from that of the second ion.

2. The method for forming a one-time programmable reset memory array as described in claim 1, characterized in that, The active region includes a first active portion parallel to a first direction and a plurality of second active portions parallel to a second direction. The first active portion and the plurality of second active portions are arranged in an intersecting pattern, and the intersection of the first active portion and the second active portion is a common active portion. The first direction is perpendicular to the second direction.

3. The method for forming a one-time programmable reset memory array as described in claim 2, characterized in that, The word line grid structure is parallel to the first direction and covers the first active portion; the first injection portion, the second injection portion, and the non-injection portion are respectively located on the first active portion between adjacent common active portions.

4. The method for forming a one-time programmable reset memory array as described in claim 3, characterized in that, A source / drain doped layer is formed within the exposed second active portion.

5. The method for forming a one-time programmable reset memory array as described in claim 4, characterized in that, The first injection layer and the source / drain doped layer are formed simultaneously.

6. The method for forming a one-time programmable reset memory array as described in claim 5, characterized in that, The method for forming the source / drain doped layer and the first implantation layer includes: forming a first sacrificial layer on the substrate, wherein the first sacrificial layer exposes the top surface of the second active portion and the top surface of the first implantation portion; and implanting the first ions using the first sacrificial layer as a mask to form the source / drain doped layer and the first implantation layer.

7. The method for forming a one-time programmable reset memory array as described in claim 1, characterized in that, The method for forming the second implantation layer includes: forming a second sacrificial layer on the substrate, the second sacrificial layer exposing the top surface of the second implantation portion; implanting the second ions using the second sacrificial layer as a mask to form the second implantation layer.

8. The method for forming a one-time programmable reset memory array as described in claim 1, characterized in that, The word line grid structure includes: a grid dielectric layer, a word line grid layer located on the grid dielectric layer, and sidewalls located on the sidewalls of the grid dielectric layer and the word line grid layer.

9. The method for forming a one-time programmable reset memory array as described in claim 8, characterized in that, The method for forming the word line gate structure includes: forming a gate dielectric material layer on the substrate; forming a word line gate material layer on the gate dielectric material layer; patterning the gate dielectric material layer and the word line gate material layer to form the gate dielectric layer and the word line gate layer; forming a sidewall material layer on the sidewalls of the gate dielectric layer and the word line gate layer, and on the top surface of the word line gate layer; and etching back the sidewall material layer until the top surface of the word line gate layer is exposed to form the sidewall.

10. The method for forming a one-time programmable reset memory array as described in claim 1, characterized in that, The first ion includes: N-type ion or P-type ion; the second ion includes: P-type ion or N-type ion.

11. A one-time programmable reset memory array, characterized in that, include: A substrate, the substrate comprising a base and an active region located on the base; A word line gate structure located on the substrate, the word line gate structure covering a portion of the top surface of the active region, the word line gate structure including a plurality of first injection portions, a plurality of second injection portions and a plurality of no injection portions; A source / drain doped layer located within the active region, wherein the source / drain doped layer contains a first ion; A first injection layer located within the first injection section, wherein the first injection layer contains the first ion; The second injection layer is located within the second injection section, and the second injection layer contains a second ion, the electrical type of the first ion and the electrical type of the second ion are different.

12. The one-time programmable reset memory array as described in claim 11, characterized in that, The active region includes a first active portion parallel to a first direction and a plurality of second active portions parallel to a second direction. The first active portion and the plurality of second active portions are arranged in an intersecting pattern, and the intersection of the first active portion and the second active portion is a common active portion. The first direction is perpendicular to the second direction.

13. The one-time programmable reset memory array as described in claim 12, characterized in that, The word line grid structure is parallel to the first direction and covers the first active portion; the first injection portion, the second injection portion, and the non-injection portion are respectively located on the first active portion between adjacent common active portions.

14. The one-time programmable reset memory array as described in claim 13, characterized in that, The source and drain doped layers are located in the second active region.

15. The one-time programmable reset memory array as described in claim 11, characterized in that, The word line grid structure includes: a grid dielectric layer, a word line grid layer located on the grid dielectric layer, and sidewalls located on the sidewalls of the grid dielectric layer and the word line grid layer.

16. The one-time programmable reset memory array as described in claim 11, characterized in that, The first ion includes: N-type ion or P-type ion; the second ion includes: P-type ion or N-type ion.

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