Method for manufacturing a flash memory floating gate

Abstract

The present invention provides a method for manufacturing a flash memory floating gate, comprising: providing a substrate having a storage area and a peripheral area, etching a portion of the thickness of the substrate to form a groove and define an active area, wherein the active area is located in the substrate on both sides of the groove; using a HARP process to form an isolation medium, wherein the isolation medium fills the groove and includes an isolation protrusion that is higher than the substrate; forming a floating gate layer, wherein the floating gate layer covers the upper surface and side surfaces of the substrate and the isolation protrusion in the storage area, and the floating gate layer also covers the substrate located in the peripheral area; forming a protective layer, wherein the protective layer fills the recessed area of ​​the floating gate layer located in the active area; using the protective layer as a mask, etching and removing the portion of the floating gate layer covering the isolation protrusion in the storage area, and removing the portion of the floating gate layer located in the peripheral area; removing the protective layer, and the remaining floating gate layer constitutes a floating gate. The present invention realizes that the floating gate layer is formed after the active area, and the HARP process is used to form the isolation medium in the STI structure, thereby ensuring good compatibility with the logic process.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for manufacturing a flash memory floating gate. Background Art

[0002] With the development of semiconductor technology, flash memory has been widely used as a non-volatile memory. Flash memory adds a floating gate and a tunneling oxide layer to the traditional MOS transistor structure, and uses the floating gate to store charges, thereby achieving non-volatility of the stored content. The manufacturing of the floating gate in flash memory is crucial. In the current flash memory floating gate manufacturing process, it is difficult to simultaneously meet the uniformity of the floating gate thickness and the compatibility with the HARP process in the logic process. Summary of the invention

[0003] The purpose of the present invention is to provide a method for manufacturing a floating gate of a flash memory. The present invention realizes that a floating gate layer is formed after an active region, and a HARP process is used to form an isolation medium in an STI structure, thereby ensuring good compatibility with a logic process.

[0004] The present invention provides a method for manufacturing a flash memory floating gate, comprising:

[0005] Providing a substrate having a storage area and a peripheral area, etching a portion of the thickness of the substrate to form a groove and define an active area, wherein the active area is located in the substrate on both sides of the groove;

[0006] forming an isolation dielectric by adopting a HARP process, wherein the isolation dielectric fills the trench and includes an isolation protrusion higher than the substrate;

[0007] forming a floating gate layer, wherein the floating gate layer covers the substrate and the upper surface and side surfaces of the isolation protrusion in the storage area, and the floating gate layer also covers the substrate in the peripheral area;

[0008] forming a protection layer, wherein the protection layer fills a recessed area of ​​the floating gate layer located in the active area;

[0009] Using the protection layer as a mask, etching and removing the portion of the floating gate layer covering the isolation protrusion in the storage area, and removing the portion of the floating gate layer located in the peripheral area;

[0010] The protection layer is removed, and the remaining floating gate layer constitutes a floating gate.

[0011] Furthermore, the floating gate layer is formed by a furnace tube process, the floating gate layer is formed by a low pressure chemical vapor deposition process in a furnace tube, and ions are implanted into the floating gate layer.

[0012] Furthermore, the furnace tube process parameters specifically include: silane gas is introduced into the furnace tube, the temperature in the furnace tube is 600° C. to 680° C., and the pressure in the furnace tube is 180 mtorr to 230 mtorr.

[0013] Furthermore, in the HARP process, Si(CH5O)(TEOS) and ozone (O3) are used as precursors to form the isolation medium.

[0014] Furthermore, after forming the isolation medium, the method further includes: performing annealing and densification treatment on the isolation medium.

[0015] Further, forming the protective layer includes:

[0016] forming a protective layer material layer, wherein the protective layer material layer covers the floating gate layer in the storage area and the peripheral area;

[0017] The protective layer material layer is chemically and mechanically polished until the floating gate layer above the isolation protrusion of the storage area and the floating gate layer of the peripheral area are exposed; the remaining protective layer material layer serves as the protective layer.

[0018] Furthermore, the method of forming the protective layer material layer includes rapid thermal oxidation or high temperature thermal oxidation.

[0019] Furthermore, the material of the protective layer includes at least one of silicon oxide, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride.

[0020] Furthermore, using the protective layer as a mask, the floating gate layer in the corresponding area is etched by dry etching, and specific parameters include: using hydrogen bromide gas with a flow rate of 100sccm to 150sccm, oxygen with a flow rate of 2sccm to 6sccm, and chlorine with a flow rate of 30sccm to 50sccm, a power of 200W to 300W, a bias voltage of 50V to 100V, and an etching time of 10s to 15s.

[0021] Furthermore, the protective layer is removed by wet etching with an HF aqueous solution.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention provides a method for manufacturing a flash memory floating gate, comprising: providing a substrate having a storage area and a peripheral area, etching a portion of the thickness of the substrate to form a groove and define an active area, wherein the active area is located in the substrate on both sides of the groove; using a HARP process to form an isolation medium, wherein the isolation medium fills the groove and includes an isolation protrusion that is higher than the substrate; forming a floating gate layer, wherein the floating gate layer covers the upper surface and side surfaces of the substrate and the isolation protrusion in the storage area, and the floating gate layer also covers the substrate located in the peripheral area; forming a protective layer, wherein the protective layer fills the recessed area of ​​the floating gate layer located in the active area; using the protective layer as a mask, etching and removing the portion of the floating gate layer covering the isolation protrusion in the storage area, and removing the portion of the floating gate layer located in the peripheral area; removing the protective layer, and the remaining floating gate layer constitutes a floating gate. The present invention realizes that the floating gate layer is formed after the active area, and the HARP process is used to form the isolation medium in the STI structure, thereby ensuring good compatibility with the logic process.

[0024] Furthermore, the floating gate layer is formed by a furnace tube process, the floating gate layer is formed by a low pressure chemical vapor deposition process in the furnace tube, and ions are implanted into the floating gate layer. The floating gate layer formed by the furnace tube process has good uniformity, and the present invention simultaneously satisfies the thickness uniformity of the floating gate and the compatibility with the HARP process in the logic process. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 to Figure 2 The figure is a schematic diagram of the steps of a method for manufacturing a flash memory.

[0026] Figure 3 to Figure 4 A schematic diagram of the steps of another method for making a flash memory.

[0027] Figure 5 The present invention is a flowchart of a method for manufacturing a flash memory floating gate according to an embodiment of the present invention.

[0028] Figures 6 to 11 Schematic diagram of each step of a method for manufacturing a flash memory floating gate according to an embodiment of the present invention.

[0029] The reference numerals are as follows:

[0030] 010 - substrate; 011 - floating gate layer; 012 - silicon nitride layer; 013 - first trench; 014 - first isolation layer 014; 015 - active area.

[0031] 020 - substrate; 021 - pad oxide layer; 022 - floating gate material layer; 022a - floating gate; 023 - second trench; 024 - second isolation layer; 025 - active area.

[0032] 100 - substrate; I - storage area; II - peripheral area; 101 - oxide layer; 102 - trench; 103 - isolation medium; 103a - isolation protrusion; 104 - active area; 105a, 105b - silicon nitride layer; 106 - floating gate layer; 107 - protective layer material layer; 107a - protective layer. DETAILED DESCRIPTION

[0033] As described in the background art, in the manufacturing process of the floating gate of a flash memory, it is difficult to simultaneously meet the requirements of the thickness uniformity of the floating gate and compatibility with the HARP process in the logic process.

[0034] Specifically, Figure 1 and Figure 2 As shown, in a floating gate manufacturing process of a 90nm embedded flash memory, a floating gate layer 011 is formed first and then an active area 015 is formed. Specifically, the process includes: firstly forming a floating gate layer 011 and a silicon nitride layer 012 in sequence on a substrate 010, and the floating gate layer 011 can be formed by a furnace tube process; the floating gate layer 011 formed by the furnace tube process has good uniformity; and then etching the silicon nitride layer 012, the floating gate layer 011 and a part of the thickness of the substrate 010 to form a first trench 013, defining an active area 015, and the active area 015 is located in the substrate region between adjacent first trenches 013. In this process, since the floating gate layer 011 and the silicon nitride layer 012 are first formed in sequence on the substrate 010, the first trench 013 formed needs to be etched by the silicon nitride layer 012 and the floating gate layer 011 in addition to etching the substrate 010, thereby forming a deeper first trench 013. In the deeper first trench 013, HARP (High Aspect Ratio Process) in the advanced logic process is used to fill the first trench 013 to form the first isolation layer 014. It is difficult to fill the first trench 013 using the HARP process, and gaps are likely to appear. That is, the floating gate layer 011 is formed first and then the active area 015 is formed. The furnace tube process forms the floating gate layer 011 with better uniformity, but it is difficult to be compatible with the HARP process in the advanced logic process.

[0035] like Figure 3 and Figure 4As shown, in a floating gate manufacturing process of an embedded flash memory in a 55nm or lower process, a floating gate 022a is formed after an active area 025. Specifically, the process includes: providing a substrate 020, on which a pad oxide layer 021 is formed; first etching the substrate 020 to form a second trench 023, and the substrate region between adjacent second trenches 023 defines an active area 025; forming a second isolation layer 024 in the second trench 023 by a HARP process in an advanced logic process, and the second isolation layer 024 formed by the HARP process can well fill the second trench 023. Afterwards, a floating gate material layer 022 is formed to cover the second isolation layer 024 and the substrate 020, and the floating gate material layer 022 is thinned by a CMP (chemical mechanical polishing) process to form a final floating gate 022a; the thickness of the floating gate 022a is determined by the CMP process, and the thickness uniformity of the floating gate 022a formed by the CMP process is poor. That is, although the process of forming the active region 025 first and then forming the floating gate 022a can be well integrated with the HARP process in the logic process, the thickness uniformity of the floating gate 022a formed by the CMP process is poor.

[0036] Based on the above research, the present invention provides a method for manufacturing a flash memory floating gate. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0038] The embodiment of the present invention provides a method for manufacturing a flash memory floating gate, such as Figure 5 As shown, including:

[0039] Step S1, providing a substrate having a storage area and a peripheral area, etching a portion of the thickness of the substrate to form a groove and define an active area, wherein the active area is located in the substrate on both sides of the groove;

[0040] Step S2, forming an isolation dielectric by using a HARP process, wherein the isolation dielectric fills the trench and includes an isolation protrusion higher than the substrate;

[0041] Step S3, forming a floating gate layer, wherein the floating gate layer covers the substrate and the upper surface and side surfaces of the isolation protrusion in the storage area, and the floating gate layer also covers the substrate in the peripheral area;

[0042] Step S4, forming a protection layer, wherein the protection layer fills the recessed area of ​​the floating gate layer located in the active area;

[0043] Step S5, using the protection layer as a mask, etching and removing the portion of the floating gate layer covering the isolation protrusion in the storage area, and removing the portion of the floating gate layer located in the peripheral area;

[0044] Step S6: removing the protection layer, and the remaining floating gate layer constitutes a floating gate.

[0045] Combine the following Figures 6 to 11 The steps of the method for manufacturing a flash memory floating gate according to an embodiment of the present invention are described in detail.

[0046] Step S1: Figure 6 As shown, a substrate 100 having a storage area I and a peripheral area II is provided; in the storage area I and the peripheral area II, a portion of the thickness of the substrate 100 is etched to form a groove 102 and an active area 104 is defined, and the active area 104 is located in the substrate 100 on both sides of the groove 102. It can also be understood that the portion of the substrate 100 between any two grooves 102 is the active area 104. That is, in this step, the active area 104 is formed while etching to form the groove 102. The present invention is divided into a storage area I and a peripheral area II on the substrate where the groove 102 and the active area 104 are formed, as shown in FIG. Figure 6 The area on the left side of the vertical line is the storage area I of the flash memory unit, and the area on the right side of the vertical line is the peripheral area II.

[0047] Specifically, in this embodiment, the substrate 100 can be at least one of the following materials: Si, SiC, SiGe, SiGeC, GeAs, InAs, InP, and other III-V or II-VI compound semiconductors. Here are only a few examples of substrates that can be formed. Those skilled in the art can select the type of substrate according to the semiconductor device formed on the substrate, and the type of substrate does not constitute a limitation on the scope of protection of the present invention. An oxide layer 101 and a silicon nitride layer are formed on the substrate 100; the silicon nitride layer includes a silicon nitride layer 105a located in the storage area I and a silicon nitride layer 105b located in the peripheral area II. The oxide layer 101 and the silicon nitride layer are etched to form a groove 102, and an active area 104 is defined. The active area 104 is located in the substrate 100 on both sides of the groove 102. On the cross section perpendicular to the substrate 100, the cross-sectional shape of the groove 102 is an inverted trapezoid or a rectangle. Exemplarily, the number of the grooves 102 is multiple, and the multiple grooves 102 are arranged at intervals. The oxide layer 101 and the silicon nitride layer may be etched using fluorine-based reactive ion etching, wherein the reaction gas includes a fluorine-based gas.

[0048] Step S2: Figure 6 As shown, the isolation dielectric 103 is formed by the HARP (High Aspect Ratio Process) process, and the isolation dielectric 103 fills the groove 102 and includes an isolation protrusion 103a higher than the substrate 100. The material of the isolation dielectric 103 is, for example, silicon oxide. The HARP process is used to fill the groove 102, which is compatible with the HARP process in the advanced logic process. The HARP process belongs to sub-atmospheric pressure chemical vapor deposition, which is a thermal reaction process. It can achieve conformal growth, so it has a strong filling ability. The HARP process is widely used in the trench filling process of shallow trench isolation (Silicon Trench Isolation, STI). The HARP process can meet the needs of trench filling at technology nodes. The isolation dielectric 103 in the groove 102 is formed by the HARP process, thereby avoiding gaps or holes in the STI and improving the hole filling ability of the HARP process in the STI.

[0049] In the HARP process, Si(CH5O)(TEOS) and ozone (O3) are used as precursors, and the ratio of O3 / TEOS is adjusted to ensure the gap filling capability. In the HARP process, chemical vapor deposition is performed through a thermal process rather than plasma enhanced chemical vapor deposition (PECVD), so there is no damage to the semiconductor structure and / or substrate on the substrate 100 caused by plasma bombardment.

[0050] Next, the isolation medium 103 can be annealed and densified. The isolation medium 103 deposited by the HARP process uses TEOS as a reactant, and the reaction is incomplete, leaving many active bond structures. When the material is exposed to an open environment, it is very easy to cause changes in the material properties. For example, the stress will decrease a lot over time due to the absorption of water vapor. In addition, the isolation medium 103 formed by the HARP process is usually loose and soft, and it is easy to produce depression defects when it is flattened by the chemical mechanical polishing (CMP) process. Such depressions will provide an uneven interface for subsequent processes. Annealing and densification of the isolation medium 103 are used to eliminate these unstable factors to stabilize its properties.

[0051] The isolation dielectric 103 is subjected to annealing and densification treatment, which can be performed in a variety of systems. For example, in a vertical or horizontal furnace, or in a rapid thermal processing (RTP) system. The annealing is set in a temperature range of 900 to 1200°C, for a period of 10 to 300 minutes, and is performed in a pure O2 environment. A steam environment combined with nitrogen, hydrogen, oxygen or other gases can also be used. The time will vary depending on the thickness of the isolation dielectric 103, and is preferably in the range of 100 to 200 minutes. The annealing and densification treatment can be completed in one process, and the isolation dielectric 103 is densified under the annealing high temperature and O2 environment, so that the isolation dielectric 103 has a higher density and hardness to avoid the generation of concave defects when the isolation dielectric 103 is flattened. The annealing high temperature removes water vapor. After the isolation dielectric 103 is annealed and densified, a CMP process is performed to make the isolation dielectric 103 and the silicon nitride layer in the storage area I flush.

[0052] like Figure 6 and Figure 7 As shown, the silicon nitride layer 105a of the storage area I is then removed to form an isolation protrusion 103a above the trench 102 and higher than the substrate 100. The silicon nitride layer 105b of the peripheral area covers the isolation protrusion 103a and the oxide layer 101.

[0053] Step S3: Figure 7As shown, a floating gate layer 106 is formed, and the floating gate layer 106 covers the upper surface and side of the substrate 100 and the isolation protrusion 103a in the storage area I, and the floating gate layer 106 also covers the substrate located in the peripheral area II. Specifically, the floating gate layer 106 in the storage area I covers the oxide layer 101 on the substrate 100, and the floating gate layer 106 in the peripheral area II covers the silicon nitride layer 105b above the substrate 100. The floating gate layer 106 is ion-implanted with N-type ions or P-type ions, and annealed. The N-type ions may include one or more of nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), and the P-type ions may include one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In). The material of the floating gate layer 106 includes, for example, polysilicon. Polysilicon is grown on the substrate using a low-pressure chemical vapor deposition process in a furnace tube, and ion implantation is performed on the polysilicon to form the floating gate layer 106. The furnace tube process parameters specifically include: silane gas is introduced into the furnace tube, the temperature in the furnace tube is 600° C. to 680° C., the pressure in the furnace tube is 180 mtorr to 230 mtorr, and the furnace tube is a quartz tube. The furnace tube process forms the floating gate layer 106 with good uniformity.

[0054] Step S4: Figure 8 and Fig. 9 As shown, a protection layer 107a is formed, and the protection layer 107a fills the recessed area of ​​the floating gate layer 106 located in the active area 104. The material of the protection layer 107a is, for example, at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.

[0055] Forming the protective layer 107a specifically includes: forming a protective layer material layer 107, wherein the protective layer material layer 107 covers the floating gate layer 106 of the storage area I and the peripheral area II. The method for forming the protective layer material layer 107 may be rapid thermal oxidation (RTO) or high temperature thermal oxidation (HTO). Specifically, the substrate 100 containing the floating gate layer 106 may be placed in a rapid oxidation process chamber, a halogen tungsten lamp may be used as a radiation heat source, and the parameters in the process chamber may be set, such as setting the process temperature at 800°C to 940°C (e.g., 850°C, 900°C, etc.), setting the reaction time at 10s to 95s (e.g., 20s, 50s, 80s, etc.), and setting parameters such as oxygen flow rate and reaction gas pressure to form the protective layer material layer 107. The desired thickness of the protective layer material layer 107 may be obtained by adjusting the process temperature, reaction time and other parameters of the rapid thermal oxidation. The rapid thermal oxidation method has the characteristics of short reaction time and fast heating speed, and can quickly form a protective layer material layer 107 on the floating gate layer 106. The protective layer material layer 107 is chemically mechanically polished (CMP) to expose the floating gate layer 106 above the isolation protrusion 103a of the storage area I and the floating gate layer 106 of the peripheral area II. The remaining protective layer material layer is used as the protective layer 107a.

[0056] Step S5: Fig.10 As shown, the protective layer 107a is used as a mask to etch away the portion of the floating gate layer 106 covering the isolation protrusion 103a in the storage area I, and the portion of the floating gate layer 106 located in the peripheral area II is removed. The protective layer 107a protects the floating gate layer 106 located between the protective layer 107a and the oxide layer 101 in the active area from being etched. The morphology of the floating gate layer 106 is trimmed; specifically, the floating gate layer 106 can be etched by dry etching. The process gas of the dry plasma process uses hydrogen bromide gas with a flow rate of 100sccm to 150sccm, oxygen with a flow rate of 2sccm to 6sccm, and chlorine with a flow rate of 30sccm to 50sccm. The power provided by the plasma process energy source is 200W to 300W, the bias voltage is 50V to 100V, and the etching time is 10s to 15s.

[0057] Step S6: Fig.10 and Fig.11 As shown, the protective layer 107a is removed, and the remaining floating gate layer 106 constitutes a floating gate. Specifically, the protective layer 107a above the floating gate layer 106 between adjacent trenches of the storage area I is etched away, and the protective layer 107a can be wet-etched by using an HF aqueous solution.

[0058] In summary, the present invention provides a method for manufacturing a flash memory floating gate, including: providing a substrate having a storage area and a peripheral area, etching a portion of the thickness of the substrate to form a groove and define an active area, wherein the active area is located in the substrate on both sides of the groove; using the HARP process to form an isolation medium, wherein the isolation medium fills the groove and includes an isolation protrusion that is higher than the substrate; forming a floating gate layer, wherein the floating gate layer covers the upper surface and side surfaces of the substrate and the isolation protrusion in the storage area, and the floating gate layer also covers the substrate located in the peripheral area; forming a protective layer, wherein the protective layer fills the recessed area of ​​the floating gate layer located in the active area; using the protective layer as a mask, etching and removing the portion of the floating gate layer covering the isolation protrusion in the storage area, and removing the portion of the floating gate layer located in the peripheral area; removing the protective layer, and the remaining floating gate layer constitutes a floating gate. The present invention realizes that the floating gate layer is formed after the active area, and the HARP process is used to form the isolation medium in the STI structure, thereby ensuring good compatibility with the logic process.

[0059] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0060] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a flash memory floating gate, characterized in that: include: Providing a substrate having a storage area and a peripheral area, etching a portion of the thickness of the substrate to form a groove and define an active area, wherein the active area is located in the substrate on both sides of the groove; forming an isolation dielectric by adopting a HARP process, wherein the isolation dielectric fills the trench and includes an isolation protrusion higher than the substrate; forming a floating gate layer, wherein the floating gate layer covers the substrate and the upper surface and side surfaces of the isolation protrusion in the storage area, and the floating gate layer also covers the substrate in the peripheral area; forming a protection layer, wherein the protection layer fills a recessed area of ​​the floating gate layer located in the active area; Using the protection layer as a mask, etching and removing the portion of the floating gate layer covering the isolation protrusion in the storage area, and removing the portion of the floating gate layer located in the peripheral area; The protection layer is removed, and the remaining floating gate layer constitutes a floating gate.

2. The method for manufacturing a flash memory floating gate according to claim 1, wherein: The floating gate layer is formed by adopting a furnace tube process, the floating gate layer is formed by adopting a low pressure chemical vapor deposition process in the furnace tube, and ions are implanted into the floating gate layer.

3. The method for manufacturing a flash memory floating gate according to claim 2, wherein: The process parameters of the furnace tube specifically include: silane gas is introduced into the furnace tube, the temperature in the furnace tube is 600° C. to 680° C., and the pressure in the furnace tube is 180 mtorr to 230 mtorr.

4. The method for manufacturing a flash memory floating gate according to claim 1, wherein: In the HARP process, Si(CH5O)(TEOS) and ozone (O3) are used as precursors to form the isolation medium.

5. The method for manufacturing a flash memory floating gate according to claim 4, characterized in that: After forming the isolation medium, the method further includes: performing annealing and densification treatment on the isolation medium.

6. The method for manufacturing a flash memory floating gate according to claim 1, wherein: Forming the protective layer includes: forming a protective layer material layer, wherein the protective layer material layer covers the floating gate layer in the storage area and the peripheral area; The protective layer material layer is chemically and mechanically polished until the floating gate layer above the isolation protrusion of the storage area and the floating gate layer of the peripheral area are exposed; the remaining protective layer material layer serves as the protective layer.

7. The method for manufacturing a flash memory floating gate according to claim 6, wherein: The method of forming the protective layer material layer includes rapid thermal oxidation or high temperature thermal oxidation.

8. The method for manufacturing a flash memory floating gate according to any one of claims 1 to 7, characterized in that: The material of the protective layer includes at least one of silicon oxide, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride.

9. The method for manufacturing a flash memory floating gate according to any one of claims 1 to 7, characterized in that: Using the protective layer as a mask, the floating gate layer in the corresponding area is etched by dry etching, and specific parameters include: using hydrogen bromide gas with a flow rate of 100sccm to 150sccm, oxygen with a flow rate of 2sccm to 6sccm, and chlorine with a flow rate of 30sccm to 50sccm, power of 200W to 300W, bias voltage of 50V to 100V, and etching time of 10s to 15s.

10. The method for manufacturing a flash memory floating gate according to any one of claims 1 to 7, characterized in that: The protective layer is removed by wet etching with an HF aqueous solution.

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