Color display optoelectronic device comprising light emitting diodes

Abstract

The present specification relates to an optoelectronic device (10) comprising a first three-dimensional light emitting diode, a second three-dimensional light emitting diode and a third three-dimensional light emitting diode having an axial configuration. Each light emitting diode comprises a semiconductor element (20, 22, 24) and an active region located on the semiconductor element. Each semiconductor element corresponds to a micron wire, a nanowire, a conical or truncated conical element in the nanometer or micron range. The first, second and third light emitting diodes are configured to emit first, second and third radiation at a first, second and third wavelength, respectively. The semiconductor elements of the first, second and third light emitting diodes have a first, second and third diameter (D1, D2, D3), respectively. The first diameter (D1) is smaller than the second diameter (D2), and the second diameter (D2) is smaller than the third diameter (D3), the first wavelength is larger than the third wavelength, and the second wavelength is larger than the first wavelength.

Description

[0001] This patent application claims priority from French patent application FR20 / 09895, which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present invention relates generally to optoelectronic devices comprising a three-dimensional semiconductor element of nanowire or microwire type and to a method for manufacturing same, and more particularly to optoelectronic devices capable of displaying an image, in particular a display screen or an image projection device. BACKGROUND

[0003] A pixel of an image corresponds to a unit element of the image displayed or captured by the optoelectronic device. For the display of a color image, the optoelectronic device generally comprises at least three components, also called display sub-pixels, for the display of each pixel of the image, each component emitting light radiation substantially in a single color (for example, red, green and blue). The superposition of the radiations emitted by the three display sub-pixels forming a component for a pixel of the displayed image provides the observer with a color sensation corresponding to the pixel of the displayed image. In this case, the component formed by the three display sub-pixels for a pixel of the displayed image is called a display pixel of the optoelectronic device.

[0004] There exist optoelectronic devices comprising a three-dimensional semiconductor element of nanowire or microwire type based on III-V compounds, which are capable of forming so-called three-dimensional light emitting diodes. A light emitting diode comprises an active region, which is the region from which the majority of the electromagnetic radiation provided by the light emitting diode is emitted. A three-dimensional light emitting diode can be formed in a so-called radial configuration (also called core / shell configuration), in which the active region is formed at the periphery of the three-dimensional semiconductor element. It can also be formed in a so-called axial configuration, in which the active region does not cover the periphery of the three-dimensional semiconductor element, but extends substantially along the longitudinal epitaxial growth axis.

[0005] The emission surface area of a three-dimensional light emitting diode in axial configuration is smaller than that of a light emitting diode in radial configuration, but has the advantage of being made of semiconductor materials of better crystalline quality, thus providing a higher internal quantum efficiency, in particular due to better relaxation of the stresses at the interfaces between the semiconductor layers.

[0006] It is known to cover a light emitting diode with a photoluminescent material, which is capable of converting the electromagnetic radiation emitted by the active region into electromagnetic radiation of different wavelength, in particular electromagnetic waves of higher wavelength. However, such a photoluminescent material can have a high cost, have a low conversion efficiency, and have a performance that degrades over time.

[0007] It would therefore be desirable to be able to form an optoelectronic device comprising a light emitting diode configured to directly emit radiation of three different colors to obtain a color display, without using a photoluminescent material.

[0008] Furthermore, industrial development of methods for producing the active regions of axial-type three-dimensional light-emitting diodes based on III-V compounds is a challenging undertaking. It is known to simultaneously form light-emitting diodes using semiconductor elements of varying diameters, which, however, emit radiation of different colors. The wavelength of the radiation emitted by the active region depends, in particular, on the diameter of the semiconductor elements and the distance between them, with the wavelength theoretically decreasing with their diameter. However, producing light-emitting diodes emitting in the blue color can be difficult, as this would require semiconductor elements with diameters too small to be compatible with industrial-scale manufacturing methods. Summary of the Invention

[0009] Therefore, an object of an embodiment is to at least partially overcome the aforementioned disadvantages of optoelectronic devices comprising light emitting diodes.

[0010] It is another object of an embodiment that the active region of each light emitting diode comprises a stack of semiconductor material layers based on III-V compounds.

[0011] It is another object of an embodiment that an optoelectronic device includes a light emitting diode configured to emit light radiation of three different colors without using photoluminescent materials.

[0012] It is another object of an embodiment that an optoelectronic device includes a light emitting diode configured to emit light radiation of three different colors and which is manufactured simultaneously.

[0013] One embodiment provides an optoelectronic device comprising first, second, and third three-dimensional light emitting diodes having an axial configuration, each light emitting diode comprising a semiconductor element and an active region located on the semiconductor element, each semiconductor element corresponding to a microwire, a nanowire, a conical element in the nanometer or micrometer range, or a truncated conical element in the nanometer or micrometer range, the first light emitting diode being configured to emit a first radiation at a first wavelength, the semiconductor element of the first light emitting diode having a first diameter, the second light emitting diode being configured to emit a second radiation at a second wavelength, the semiconductor element of the second light emitting diode having a second diameter, and the third light emitting diode being configured to emit a third radiation at a third wavelength, the semiconductor element of the third light emitting diode having a third diameter, the first diameter being smaller than the second diameter, and the second diameter being smaller than the third diameter, the first wavelength being greater than the third wavelength, and the second wavelength being greater than the first wavelength.

[0014] According to one embodiment, the first diameter varies between 80 nm and 150 nm.

[0015] According to one embodiment, the second diameter varies between 200 nm and 350 nm.

[0016] According to one embodiment, the third diameter varies between 370 nm and 500 nm.

[0017] According to one embodiment, the first wavelength is in the range 510 nm to 570 nm.

[0018] According to one embodiment, the second wavelength is in the range 600 nm to 720 nm.

[0019] According to one embodiment, the third wavelength is in the range 430 nm to 490 nm.

[0020] According to one embodiment, the device comprises a first opto-electronic circuit bonded to a second electronic circuit, the second electronic circuit comprising a conductive pad, the first opto-electronic circuit comprising pixels, and for each pixel, comprising:

[0021] - a first electrically conductive layer;

[0022] - for each of the first, second and third light emitting diodes, the semiconductor element extends perpendicularly to the first electrically conductive layer and is in contact with the first electrically conductive layer, and the active region is located on an end of the semiconductor element opposite the first electrically conductive layer; and

[0023] - second, third, fourth and fifth electrically conductive layers electrically coupled to the conductive pad, the second electrically conductive layer being coupled to the active region of the first light emitting diode, the third electrically conductive layer being coupled to the active region of the second light emitting diode, the fourth electrically conductive layer being coupled to the active region of the third light emitting diode, and the fifth electrically conductive layer being coupled to the first electrically conductive layer.

[0024] According to one embodiment, each active region comprises a single quantum well or a plurality of quantum wells.

[0025] According to one embodiment, the semiconductor element and the active region are made of a III-V compound.

[0026] According to one embodiment, the semiconductor element of the first, second and third light emitting diodes is formed by MOCVD.

[0027] According to one embodiment, the active region of the first, second and third light emitting diodes is formed by MBE.

[0028] According to one embodiment, the semiconductor element of the first, second and third light emitting diodes is located on a substrate and is in contact with a material adapted for epitaxial growth of the semiconductor element of the first, second and third light emitting diodes.

[0029] According to one embodiment, the first, second and third light emitting diodes form a monolithic structure.

[0030] The embodiments also provide a method of manufacturing an optoelectronic device as previously defined, comprising the following successive steps:

[0031] - simultaneously forming semiconductor elements of the first, second and third light emitting diodes; and

[0032] - simultaneously forming active regions of the first, second and third light emitting diodes on the semiconductor elements of the first, second and third light emitting diodes.

[0033] According to one embodiment, the method comprises the following successive steps:

[0034] - simultaneously forming semiconductor elements of the first, second and third light emitting diodes on the support, and forming active regions of the first, second and third light emitting diodes on the semiconductor elements of the first, second and third light emitting diodes;

[0035] - forming an electrically insulating layer between the three-dimensional semiconductor elements of the first, second and third light emitting diodes; and

[0036] - removing the support. BRIEF DESCRIPTION OF DRAWINGS

[0037] The foregoing features and advantages, as well as other features and advantages, will be more fully described in the following description of specific embodiments, taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 is a partial simplified cross-sectional view of an embodiment of an optoelectronic device comprising microwires or nanowires;

[0039] Figure 2 is a detailed view of a portion of Figure 1 ;

[0040] Figure 3 is a curve showing the variation of the central wavelength of the radiation emitted by the axial light emitting diodes as a function of the diameter of the light emitting diodes, obtained by tests;

[0041] Figure 4 shows a chromaticity diagram showing the color gamut that can be obtained with the optoelectronic device of Figure 1 ;

[0042] Figure 5 shows a curve of the light intensity as a function of the wavelength of the radiation emitted by the three light emitting diodes of the optoelectronic device of Figure 1 , obtained by tests;

[0043] Figure 6 is a graph showing the color gamut that can be obtained with the optoelectronic device of Figure 1partial simplified cross-sectional view of the operation of an optoelectronic device;

[0044] Figure 7A An embodiment of a method of manufacturing an optoelectronic device is shown. Figure 1 An embodiment of a method of manufacturing an optoelectronic device is shown.

[0045] Figure 7B Another step of the method is shown.

[0046] Figure 7C Another step of the method is shown.

[0047] Figure 7D Another step of the method is shown.

[0048] Figure 7E Another step of the method is shown.

[0049] Figure 7F Another step of the method is shown.

[0050] Figure 7G Another step of the method is shown.

[0051] Figure 7H Another step of the method is shown.

[0052] Figure 7I Another step of the method is shown.

[0053] Figure 7J Another step of the method is shown.

[0054] Figure 7K Another step of the method is shown.

[0055] Figure 7L Another step of the method is shown.

[0056] Figure 7M Another step of the method is shown; and

[0057] Figure 7N Another step of the method is shown. DETAILED DESCRIPTION

[0058] In the various drawings, like features are designated by like reference numerals. In particular, structural and / or functional features that are common among the various embodiments can have the same reference numerals and can be provided with the same structural, dimensional, and material attributes. For the sake of clarity, only the steps and elements useful for an understanding of the embodiments described herein have been shown and described in detail. In particular, devices for controlling light emitting diodes of an optoelectronic device are well known and will not be described.

[0059] In the following description, when referring to terms defining an absolute position, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or a relative position, such as the terms "above", "below", "upper", "lower", etc., or a term defining a direction, such as the terms "horizontal", "vertical", etc., it refers to the orientation of the drawings or to the optoelectronic device in a normal use position.

[0060] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected, or they can be coupled via one or more other elements.

[0061] Unless otherwise specified, the expressions "approximately", "about", "substantially" and "around" mean within 10% and preferably within 5%. Furthermore, unless otherwise specified, the expression "insulated" means "electrically insulated" and the expression "conductive" means "electrically conductive". In the following description, the internal transmission of a layer corresponds to the ratio of the intensity of the radiation coming out of the layer to the intensity of the radiation entering the layer. The absorption of the layer is equal to the difference between 1 and the internal transmission. In the following description, a layer is said to be transparent to radiation when the absorption of the radiation by the layer is less than 60%. In the following description, a layer is said to be absorbing to radiation when the absorption of the radiation in the layer is higher than 60%. When the radiation exhibits a spectrum generally "bell" shaped (for example, Gaussian shape) with one maximum, the wavelength of the radiation, or the central wavelength or the main wavelength of the radiation, denotes the wavelength reaching the maximum of the spectrum. In the following description, the refractive index of a material corresponds to the refractive index of the material in the wavelength range of the radiation emitted by the optoelectronic device. Unless otherwise specified, the refractive index is considered to be substantially constant in the wavelength range of the useful radiation, for example, equal to the average of the refractive index in the wavelength range of the radiation emitted by the optoelectronic device.

[0062] The present application particularly relates to optoelectronic devices comprising light emitting diodes comprising three-dimensional elements, for example, microwires, nanowires, conical elements in the nanometric or micrometric range, or truncated conical elements in the nanometric or micrometric range. In particular, the conical or truncated conical elements can be conical or truncated conical elements or pyramidal or truncated conical elements. In the following description, embodiments are particularly described for electronic devices comprising microwires or nanowires. However, such embodiments can be implemented for three-dimensional elements other than microwires or nanowires, for example, conical or truncated conical three-dimensional elements.

[0063] The terms "microwire", "nanowire", "conical element" or "truncated conical element" mean a three-dimensional structure having a shape elongated along a preferential direction, having at least two dimensions, called secondary dimensions, ranging from 5 nm to 2.5 pm, preferably from 50 nm to 1 pm, more preferably from 30 nm to 300 nm, a third dimension, called primary dimension, greater than or equal to 1 times the largest secondary dimension, preferably greater than or equal to 5 times, for example ranging from 1 pm to 5 pm.

[0064] In the following description, the term "wire" is used to mean "microwire" or "nanowire". Preferably, in a plane perpendicular to the preferential direction of the wire, the median line of the wire passing through the barycenter of the cross section is substantially straight and is hereinafter referred to as the "axis" of the wire. The wire diameter is defined here as the quantity associated with the perimeter of the wire at a level of the cross section. This can be the diameter of a disc having the same surface as the cross section of the wire. The local diameter, also referred to hereinafter as the diameter, is the diameter of the wire at a given level of height along the axis of the wire. The average diameter is the average, for example the arithmetic average, of the local diameters along the wire or a portion thereof.

[0065] According to one embodiment, as previously mentioned, each axial type light emitting diode comprises a wire and an active region on top of the wire. The active region is the region that emits the most part of the radiation provided by the light emitting diode. The active region can comprise confinement means. The active region can comprise one quantum well, two quantum wells or a plurality of quantum wells, each quantum well being inserted between two barrier layers, the bandgap energy of the quantum well being smaller than the bandgap energy of the barrier layers. The active region can comprise one or more quantum wells made of a ternary compound comprising the group III and group V elements of the wire and an additional group III element. The length of the radiation emitted by the active region depends on the proportion of incorporation of the additional group III element. For example, the wire can be made of GaN and the one or more quantum wells can be made of InGaN. Thus, the length of the radiation emitted by the active region depends on the proportion of incorporation of In.

[0066] It is known that the proportion of additional group III element varies as a function of the wire diameter. However, the documents mentioning this variation so far describe an increase in the proportion of additional group III element as a function of the wire diameter and thus an increase in the wavelength of the radiation emitted by the axial type light emitting diode comprising such a wire.

[0067] The inventors have shown that it is possible to observe a first, a second and a third successive diameter range, the wavelength of the radiation emitted by the light emitting diode increasing when the wire diameter increases in the first diameter range, the wavelength of the radiation emitted by the light emitting diode decreasing when the wire diameter increases in the second diameter range, and the wavelength of the radiation emitted by the light emitting diode stagnating when the wire diameter increases in the third diameter range.

[0068] These results have been advantageously obtained with wires formed by metal-organic chemical vapor deposition (MOCVD) and active regions, generally formed by molecular beam epitaxy (MBE).

[0069] The aforementioned method can be implemented to manufacture optoelectronic devices capable of displaying images, in particular display screens or image projection devices. In particular, the aforementioned method can be implemented to manufacture wires of different average diameters, for example, a first wire having a small average diameter, a second wire having an intermediate diameter and a third wire having a large average diameter. The active regions formed on the first, second and third wires will emit radiation of different wavelengths. In particular, the first wire having a small average diameter will emit radiation at a first central wavelength, the second wire having an intermediate average diameter will emit radiation at a second central wavelength, and the third wire having an intermediate average diameter will emit radiation at a third central wavelength, the second wavelength being greater than the first wavelength and the third wavelength being less than the first wavelength. A color display screen can then be manufactured.

[0070] The formation of the wires by MOCVD advantageously makes it possible to obtain wires with fewer defects, in particular defect-free wires, compared to wires that can be obtained by MBE. The formation of the wires by MOCVD advantageously makes it possible to obtain rapid growth of the wires. It also makes it possible to easily obtain wires with diameters that comply with the diameter-wavelength variation curve implemented according to the application. The MBE method advantageously makes it possible to incorporate a greater proportion of additional group III elements into the quantum well compared to the MOCVD method.

[0071] In addition, the fact that the active regions are formed only on the upper part of the wires and not on the sides of the wires advantageously makes it possible to form the active regions only on the c-plane or semi-polar plane and not on the m-plane. This advantageously makes it possible to incorporate a greater proportion of additional group III elements into the quantum well compared to the case where the active regions grow on the m-plane.

[0072] Figure 1 is a partial simplified cross-sectional view of an optoelectronic device 10 formed from wires as previously described and capable of emitting electromagnetic radiation. According to one embodiment, the optoelectronic device 10 is provided comprising at least two integrated circuits 12 and 14, also referred to as chips. The first integrated circuit 12 comprises light-emitting diodes. The second integrated circuit 14 comprises electronic components, in particular transistors, for controlling the light-emitting diodes of the first integrated circuit 12. The first integrated circuit 12 is bonded to the second integrated circuit, for example by molecular bonding or by a "flip-chip" type bonding, in particular a ball or microtube "flip-chip" method. The first integrated circuit 12 is referred to as an optoelectronic circuit or optoelectronic chip in the following description and the second integrated circuit 14 is referred to as a control circuit or control chip in the following description.

[0073] Preferably, the optoelectronic chip 12 comprises only light emitting diodes and their connecting elements, and the control chip 14 comprises all the electronic components required to control the light emitting diodes of the optoelectronic chip. As a variant, the optoelectronic chip 12 may also comprise other electronic components in addition to the light emitting diodes.

[0074] Figure 1 On its left part the elements of the optoelectronic chip 12 for a display pixel are shown, this structure being repeated for each display pixel, and on its right part the elements adjacent to the display pixel and possibly common to a plurality of display pixels are shown.

[0075] Optoelectronic chip 12 Figure 1 From top to bottom, it includes:

[0076] an electrically insulating layer 16 , which is at least partially transparent to the electromagnetic radiation emitted by the light-emitting diode and which defines a surface 17 ;

[0077] - an electrically conductive layer 18 which is at least partially transparent to the electromagnetic radiation emitted by the light-emitting diode;

[0078] a first conductive wire 20 (three first conductive wires are shown) having a diameter D1, a second conductive wire 22 (three second conductive wires are shown) having a diameter D2, and a third conductive wire 24 (three third conductive wires are shown) having a diameter D3, wherein the first, second, and third conductive wires have axes that are parallel to each other and perpendicular to surface 17, extend from and contact conductive layer 18, and wherein diameter D1 is smaller than diameter D2, and diameter D2 is smaller than diameter D3;

[0079] a first head 26 at the end of each first conductive wire 20 opposite the conductive layer 18 , a second head 28 at the end of each second conductive wire 22 opposite the conductive layer 18 , and a third head 30 at the end of each third conductive wire 24 opposite the conductive layer 18 ;

[0080] an electrically insulating layer 32 made of a first electrically insulating material between the wires 20 , 22 , 24 , the thickness of which is substantially equal to the sum of the heights H of the wires 20 , 20 , 24 and of the associated heads 26 , 28 , 30 , measured along their axes;

[0081] an electrically insulating layer 34 of a second electrically insulating material, which may be different from the first insulating material or the same as the first insulating material, extending around the first insulating layer 32 and having the same thickness as the insulating layer 32;

[0082] an opening 36 extending through the insulating layer 34 across the entire thickness of the insulating layer 34 ;

[0083] a conductive layer 38 extending in the opening 36 and in contact with the conductive layer 18 ;

[0084] different conductive layers 42 , 44 , 46 , 48 , the conductive layer 42 being in contact with the first head 26 , the conductive layer 44 being in contact with the second head 28 , the conductive layer 46 being in contact with the third head 30 , and the conductive layer 48 being in contact with the conductive layer 38 ;

[0085] an electrically insulating layer 50 covering and extending between the conductive layers 42 , 44 , 46 and 48 and defining a surface 51 , preferably substantially planar; and

[0086] Conductive pads 52 , 54 , 56 , 58 can have a multi-layer structure, extending through insulating layer 50 and flush with surface 51 , conductive pad 52 contacting conductive layer 42 , conductive pad 54 contacting conductive layer 44 , conductive pad 56 contacting conductive layer 46 , and conductive pad 58 contacting conductive layer 48 .

[0087] The control chip 14 comprises, in particular, an electrically insulating layer 60 on the side of the optoelectronic chip 12, the electrically insulating layer 60 defining a surface 61, preferably substantially planar, and conductive pads 62 flush with the surface 61, the conductive pads 62 being electrically coupled to the conductive pads 52, 54, 56, 58. In the case where the control chip 14 is bonded to the optoelectronic chip 12 by molecular bonding, the conductive pads 62 can be in contact with the conductive pads 52, 54, 56, 58. In the case where the control chip 14 is bonded to the optoelectronic chip 12 by a "flip-chip" type bonding, solder balls or micropipes can be inserted between the conductive pads 62 and the conductive pads 52, 54, 56, 58.

[0088] The assembly formed by each wire 20, 22, 24 and the associated header 26, 28, 30 forms, in an axial configuration, a basic light-emitting diode in the form of a wire.

[0089] Figure 2 is a simplified partial cross-sectional view of a more detailed embodiment of a light emitting diode header 26. Headers 28 and 30 may have similar structures.

[0090] Head 26 Figure 2 From top to bottom, it includes:

[0091] a semiconductor layer 70 , also referred to as a semiconductor cap, made of the same material as the conductive line 20 and doped with a first conductivity type, for example N-type, covering an upper end 72 of the conductive line 20 and having an upper surface 74 ;

[0092] an active region 76 covering a surface 74 of the semiconductor layer 70 ; and

[0093] A semiconductor stack 78 covering the active region 76 and comprising at least one semiconductor layer 80 , having a conductivity type opposite to that of the conductive line 20 , covering the active region 74 .

[0094] Each wire 20, 22, 24 and each semiconductor layer 70, 80 is at least partially formed from at least one semiconductor material. According to one embodiment, the semiconductor material is selected from the group comprising III-V compounds, for example III-N compounds. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AIN, InN, InGaN, AlGaN or AlInGaN. Other group V elements can also be used, for example phosphorus or arsenic. Typically, the elements in the III-V compound can be combined in different molar fractions. The semiconductor material of the wires 20, 22, 24 and / or the semiconductor layers 70, 80 can comprise a dopant, for example silicon to ensure N-type doping of the III-N compound, or magnesium to ensure P-type doping of the III-N compound.

[0095] The stack 78 can further comprise an electron blocking layer 82 between the active region 76 and the semiconductor layer 80, and a junction layer 84 covering the semiconductor layer 80 on the opposite side of the active region 76, the junction layer 84 being covered by the conductive layer 42. The junction layer 84 can be made of the same semiconductor material as the semiconductor layer 80, with the same conductivity type as the semiconductor layer 80, but with a greater dopant concentration. The junction layer 84 is capable of forming an ohmic contact between the semiconductor layer 80 and the conductive pad 42.

[0096] The active region 76 is the region that emits most of the radiation provided by the light emitting diode. According to one example, the active region 76 can comprise confinement means. The active region 76 can comprise at least one quantum well comprising a layer of additional semiconductor material having a band gap energy smaller than the band gap energy of the semiconductor layers 70 and 80, preferably interposed between two barrier layers, thereby improving the confinement of charge carriers. The additional semiconductor material can comprise a III-V compound that dopes the semiconductor layers 70, 80 with at least one additional element incorporated therein. As an example, in the case of wires 20, 22, 24 made of GaN, the additional material forming the quantum well is preferably InGaN. The active region 76 can be made of a single quantum well or of multiple quantum wells.

[0097] According to a preferred embodiment, each wire 20, 22, 24 is made of GaN. The semiconductor layer 70 can be made of GaN and doped with a first type of conduction, for example N-type, in particular doped with silicon. The height of the conductive layer 70, measured along the axis C, can be in the range 10 nm to 1 pm, for example in the range 20 nm to 200 nm. The active region 76 can comprise a single or multiple quantum well, for example made of InGaN. The active region 76 can comprise a single quantum well extending between the semiconductor layers 70, 80. As a variant, it can comprise multiple quantum wells, and then formed by quantum wells 86, for example made of InGaN, and barrier layers 88, for example made of GaN, alternating along the axis C, Figure 2 Three GaN layers 88 and two InGaN layers 86 are shown as examples in FIG. 1. The GaN layers 88 can for example be N-type or P-type doped or non-doped. The thickness of the active region 76, measured along the axis C, can be in the range 2 nm to 100 nm. The conductive layer 80 can be made of GaN and doped with a second type of conduction opposite to the first type, for example P-type, in particular doped with magnesium. The thickness of the semiconductor layer 80 can be in the range 20 nm to 100 nm. When present, the electron blocking layer 82 can be made of GaN or a ternary III-N compound, for example AlGaN or AlInN, advantageously P-type doped. This enables to increase the radiative recombination rate in the active region 76. The thickness of the electron blocking layer 82 can be in the range 10 nm to 50 nm. The electron blocking layer 82 can correspond to a superlattice of InAlGaN or AlGaN and GaN layers, each layer for example having a thickness of 2 nm.

[0098] Tests have been carried out. For the tests, the wires 20 were made of GaN. The active regions 76 each consisted of seven quantum wells made of InGaN separated by GaN layers. The wires 20 have been formed by MCV D and the active regions 76 have been formed by MBE. The wavelength of the radiation emitted by the active regions 76 as well as the diameter of the wires 20 have been measured.

[0099] Figure 3 The results of these tests have been collected. The ordinate axis shows the central wavelength l of the radiation emitted by the active regions 76, expressed in nanometers, and the abscissa axis shows the diameter D of the wires 20, expressed in nanometers. The results of a first series of tests are represented by white circles in Figure 3 and the results of a second series of tests are represented by black circles in Figure 3 The curve CT is a curve of the variation of the wavelength l as a function of the diameter D, obtained by cubic spline regression from the values obtained in the first and second tests. The horizontal lines R, G and B correspond to red, green and blue respectively.

[0100] As a comparison, the black diamonds show the results disclosed in the publication by Kishino et al. entitled "Monolithic integration of four-colour InGaN-based nanocolumn LEDs" (Elec Letters, 28 May 2015, Vol. 51, pp. 852-854), and the hexagons containing a cross show the results disclosed in the publication by Mi et al. entitled "Tunable, Full-Color Nanowire Light Emitting Diode Arrays Monolithically Integrated on Si and Sapphire" (Proc. of SPIE Vol. 9748+, 2016). The comparison results were obtained with GaN wires and active regions having a single InGaN quantum well. Moreover, for the publications by Mi et al. and Kishino et al., the wires and the active regions were formed by MBE. For the comparison results, it can be observed that the wavelength of the emitted radiation increases with the increase of the wire diameter. It is known that the wavelength of the radiation emitted by an active region increases when the proportion of indium in the quantum well or quantum wells increases. Therefore, the comparison results show that the proportion of indium in the single quantum well increases when the wire diameter increases.

[0101] The wires formed by MOCVD are able to form wires of greater diameter than those typically achieved by MBE, so after forming the active region by MBE, it is observed that the curve of variation CT successively comprises a first rising portion CI for which the wavelength of the emitted radiation increases with the diameter of the wire; a second decreasing portion C2 for which the wavelength of the emitted radiation decreases with the diameter of the wire; and a third substantially constant portion C3 for which the wavelength of the emitted radiation varies little with the diameter of the wire.

[0102] According to one embodiment, the first rising portion CI is obtained for wire diameters varying in a first range PI of approximately 50 nm to approximately 300 nm. The wavelength of the emitted radiation increases on the first rising portion from approximately 510 nm to approximately 675 nm. According to one embodiment, the second decreasing portion C2 is obtained for wire diameters varying in a second range P2 from approximately 300 nm to approximately 375 nm. The wavelength of the emitted radiation decreases on the second decreasing portion from approximately 675 nm to approximately 475 nm. According to one embodiment, the third constant portion C3 is obtained for wire diameters in a third range P3 from approximately 375 nm to approximately 550 nm. The wavelength of the emitted radiation varies on the third constant portion between approximately 460 nm and 490 nm. As can be observed in the graph of figure 1, the curve of variation CT obtained with the wires formed by MOCVD comprises a first rising portion CI, a second decreasing portion C2 and a third constant portion C3, which are substantially similar to the curve of variation CT obtained with the wires formed by MBE. Figure 3The light emitting diodes emitting in blue can be formed with a diameter in the third range P3 and the light emitting diodes emitting in green and red can be formed with a diameter in the first range PI. The light emitting diodes emitting in green can be formed with a diameter in the second range P2. In practice, however, the variability of the wavelength obtained as a function of the diameter can be too high for industrial scale applications.

[0103] The display pixel is formed by forming a first light emitting diode with a wire 20 having a small diameter Dl, a second light emitting diode with a wire 22 having a medium diameter D2 and a third light emitting diode with a wire 24 having a large diameter D3.

[0104] Figure 4 An XY chromaticity diagram is shown in which the results of the first and second tests are represented with black circles. By selecting the light emitting diodes corresponding to the circles DR, DG and DB closest to the "apex" of the chromaticity diagram, it is possible to form a display sub-pixel which can display an image pixel whose color can be obtained by combining the colors corresponding to the circles DR, DG and DB. For the circle DR, the diameter is approximately equal to 200-250 nm. For the circle DG, the diameter is approximately equal to 100-150 nm. For the circle DB, the diameter is greater than or equal to approximately 370 nm. It appears possible to reach a large part of the chromaticity diagram.

[0105] Figure 5 The possible explanation of the variation of the curve CT in Figure 4 is shown. R The curves C G and C B represent the intensity of the light I emitted by the light emitting diodes corresponding to the circles DR, DG and DB respectively, in arbitrary units (a.u.). As shown in this figure, the radiation spectrum of these light emitting diodes is relatively narrow.

[0106] Figure 6 The possible explanation of the variation of the curve CT in Figure 3 is shown. Figure 6 Three wires 20, 22, 24 are shown very schematically, without showing the associated active regions 76, semiconductor stacks 78 and conductive layers 42, 44 and 46. The upper part of each wire 20, 22, 24 can comprise a c-plane (a surface 90 perpendicular to the axis c) and / or a semi-polar plane (a surface 92 inclined with respect to the axis c). The active region 76 can cover the c-plane and / or the semi-polar plane. The optical properties of the part of the active region 76 covering the c-plane are different from the optical properties of the part of the active region 76 covering the semi-polar plane. In particular, the maximum rate of incorporation of additional elements into the part of the active region 76 covering the c-plane is greater than the maximum rate of incorporation of additional elements into the part of the active region 76 covering the semi-polar plane. The optical properties of the part of the active region 76 covering the semi-polar plane are different from the optical properties of the part of the active region 76 covering the c-plane. In particular, the maximum rate of incorporation of additional elements into the part of the active region 76 covering the semi-polar plane is greater than the maximum rate of incorporation of additional elements into the part of the active region 76 covering the c-plane. The optical properties of the part of the active region 76 covering the semi-polar plane are different from the optical properties of the part of the active region 76 covering the c-plane. In particular, the maximum rate of incorporation of additional elements into the part of the active region 76 covering the semi-polar plane is greater than the maximum rate of incorporation of additional elements into the part of the active region 76 covering the c-plane. Figure 3The interpretation of the curve CT of the variation is as follows: in a first range of diameters PI, among the total radiation emitted by the active region 76, the contribution of the part of the active region 76 located on the c-plane is greater than the contribution of the part of the active region 76 located on the semi-polar plane. Thus, it can be observed that the wavelength of the total radiation increases with the increase in the wire diameter. In a second range of diameters P2, the contribution of the total radiation of the part of the active region 76 located on the c-plane and the contribution of the total radiation of the part of the active region 76 located on the semi-polar plane are of opposite significance, and since the incorporation of indium into the part of the active region 76 located on the semi-polar plane decreases, the central wavelength of the total radiation drops. In a third range of diameters P3, among the total radiation emitted by the active region 76, the contribution of the part of the active region 76 located on the semi-polar plane exceeds the contribution of the part of the active region 76 located on the c-plane, which leads to a stagnation of the central wavelength of the emitted radiation.

[0107] Again considering Figure 1 , according to one embodiment, each display pixel of the optoelectronic device 10 comprises at least three types of light-emitting diodes. According to one embodiment, a first type of light-emitting diode (for example comprising the wire 20 and the head 26) is adapted to emit a first radiation at a first central wavelength. A second type of light-emitting diode (for example comprising the wire 22 and the head 28) is adapted to emit a second radiation at a second central wavelength. A third type of light-emitting diode (for example comprising the wire 24 and the head 30) is adapted to emit a third radiation at a third central wavelength. The first, second and third central wavelengths are different.

[0108] According to one embodiment, the first wavelength corresponds to green light and is in the range 510 nm to 550 nm. According to one embodiment, the first diameter D1 varies from 80 nm to 150 nm. According to one embodiment, the second wavelength corresponds to red light and is in the range 600 nm to 720 nm. According to one embodiment, the second diameter D2 varies from 200 nm to 350 nm. According to one embodiment, the third wavelength corresponds to blue light and is in the range 430 nm to 490 nm. According to one embodiment, the third diameter D3 varies from 370 nm to 500 nm. Advantageously, as Figure 3 indicated on the graph, above a diameter equal to approximately 400 nm, the wavelength of the radiation emitted by the active region 76 is almost insensitive to the wire diameter.

[0109] According to one embodiment, each display pixel Pix includes a fourth type of light-emitting diode, which is adapted to emit fourth radiation at a fourth wavelength. The first, second, third, and fourth wavelengths may be different. According to one embodiment, the fourth wavelength corresponds to yellow light and is in the range of 570 nm to 600 nm, or corresponds to cyan and is in the range of 490 nm to 510 nm, or generally corresponds to any other color in addition to the first, second, and third radiation.

[0110] According to one embodiment, for each display pixel, elementary light emitting diodes having wires of the same diameter have a common electrode, and when a voltage is applied between conductive layer 18 and conductive layer 42, 44 or 46, light radiation is emitted from the active areas of these elementary light emitting diodes.

[0111] In this embodiment, electromagnetic radiation emitted by each light emitting diode escapes from the optoelectronic device 12 through the surface 17. Preferably, each conductive layer 42, 44, 46 is reflective and advantageously increases the proportion of radiation emitted by the light emitting diode that escapes from the optoelectronic device 10 through the surface 17.

[0112] The stacking of optoelectronic chip 12 and control chip 14 reduces the lateral size of optoelectronic device 10. According to one embodiment, the lateral dimension of a display pixel, measured perpendicular to the conductor axis, is less than 5 μm, preferably less than 4 μm, for example, approximately 3 μm. Furthermore, optoelectronic chip 12 can have the same dimensions as control chip 14. Consequently, the compactness of optoelectronic device 10 can be advantageously increased.

[0113] Conductive layer 18 can bias the active areas of headers 26, 28, and 30 and provide a path for electromagnetic radiation emitted by the light-emitting diodes. Conductive layer 18 can be formed of a transparent conductive material such as graphene or a transparent conductive oxide (TCO) (particularly indium tin oxide (ITO) or zinc oxide doped or undoped with aluminum, gallium, or boron), or silver nanowires. By way of example, the thickness of conductive layer 18 ranges from 20 nm to 500 nm, preferably from 20 nm to 100 nm.

[0114] The conductive layers 38, 42, 44, 46, 48 and the conductive pads 52, 54, 56, 58 can be made of a metal, for example of aluminum, silver, platinum, nickel, copper, gold or ruthenium, or of an alloy comprising at least two of these compounds, in particular a PdAgNiAu alloy or a PtAgNiAu alloy. The thickness of the conductive layer 38 can be in the range of 100 nm to 3 pm. The thickness of the conductive portions 42, 44, 46, 48 can be in the range of 100 nm to 2 pm. In a plane perpendicular to the surface 17, the smallest lateral dimension is in the range of 150 nm to 1 pm, for example about 0.25 pm. The thickness of the conductive pads 52, 54, 56, 58 can be in the range of 0.5 pm to 2 pm.

[0115] Each of the insulating layers 16, 32, 34 and 50 is made of a material selected from the group of silicon oxide (Si02), silicon nitride (Si3N4), silicon oxynitride (in particular of the general formula SiOxNy, for example Si2ON2), hafnium oxide (Hf02), titanium oxide (Ti02) or aluminum oxide (AI2O3). The layer 34 and / or the layer 32 can further be made of an organic insulating material, for example of parylene or benzocyclobutene (BCB). The maximum thickness of the insulating layer 16 can be in the range of 100 nm to 5 pm. The maximum thickness of the insulating layers 32 and 34 can be in the range of 0.5 pm to 2 pm. The maximum thickness of the insulating layer 50 can be in the range of 0.5 pm to 2 pm. x N y wherein x is approximately equal to 3 and y is approximately equal to 4, for example Si3N4), silicon oxynitride (in particular of the general formula SiOxNy, for example Si2ON2), hafnium oxide (Hf02), titanium oxide (Ti02) or aluminum oxide (AI2O3). The layer 34 and / or the layer 32 can further be made of an organic insulating material, for example of parylene or benzocyclobutene (BCB). The maximum thickness of the insulating layer 16 can be in the range of 100 nm to 5 pm. The maximum thickness of the insulating layers 32 and 34 can be in the range of 0.5 pm to 2 pm. The maximum thickness of the insulating layer 50 can be in the range of 0.5 pm to 2 pm. x N y wherein x is approximately equal to 3 and y is approximately equal to 4, for example Si3N4), silicon oxynitride (in particular of the general formula SiOxNy, for example Si2ON2), hafnium oxide (Hf02), titanium oxide (Ti02) or aluminum oxide (AI2O3). The layer 34 and / or the layer 32 can further be made of an organic insulating material, for example of parylene or benzocyclobutene (BCB). The maximum thickness of the insulating layer 16 can be in the range of 100 nm to 5 pm. The maximum thickness of the insulating layers 32 and 34 can be in the range of 0.5 pm to 2 pm. The maximum thickness of the insulating layer 50 can be in the range of 0.5 pm to 2 pm.

[0116] Each wire 20, 22, 24 can have a semiconductor structure elongated along an axis substantially perpendicular to the surface 17. Each wire 20, 22, 24 can have a substantially cylindrical shape, the cross-section of which can have a different shape, such as for example an elliptical shape, a circular shape or a polygonal shape, in particular a triangular shape, a rectangular shape, a square shape or a hexagonal shape. The axes of two adjacent wires 20, 22, 24 can be at a distance of 100 nm to 3 pm, preferably of 200 nm to 1.5 pm. The height of each wire 20, 22, 24 can be in the range of 150 nm to 10 pm, preferably of 200 nm to 1 pm, more preferably of 250 nm to 750 nm. The average diameter of each wire 20, 22, 24 can be in the range of 50 nm to 10 pm, preferably of 100 nm to 2 pm, more preferably of 120 nm to 1 pm.

[0117] According to one embodiment, the wires 20, 22, 24 are formed simultaneously from the seed layer by MOCVD. The growth conditions in the reactor are adapted to favour preferential growth of each wire 20, 22, 24 along its axis C. This means that the growth speed of the wire along the axis C is much greater than the growth speed of the wire in a direction perpendicular to the axis C, preferably at least one order of magnitude. In one example, the method can comprise injecting a precursor of a group III element and a precursor of a group V element into the reactor. Examples of precursors of group III elements are trimethyl gallium (TMGa), triethyl gallium (TEGa), trimethyl indium (TMIn) or trimethyl aluminium (TMAl). Examples of precursors of group V elements are ammonia (NH3), tributyl phosphate (TBP), arsine (AsH3) or dimethylhydrazine (UDMH). Some of the precursor gases can be generated by using a water bubbler and a carrier gas.

[0118] According to one embodiment, the temperature in the reactor is in the range 900°C to 1065°C, preferably in the range 1000°C to 106.5°C, in particular 1050°C. According to one embodiment, the pressure in the reactor is in the range 50 Torr (about 6.7 kPa) to 200 Torr (about 26.7 kPa), in particular 100 Torr (about 13.3 kPa). According to one embodiment, the flow rate of the precursor of a group III element (e.g. TEGa) is in the range 500 sccm to 2500 sccm, in particular 1155 sccm. According to one embodiment, the flow rate of the precursor of a group V element (e.g. NH3) is in the range 65 sccm to 260 sccm, in particular 130 sccm. According to one embodiment, the ratio of the flow rate of the precursor gas of a group V element injected into the reactor to the flow rate of the precursor gas of a group III element injected into the reactor, known as the V / III ratio, is in the range 5 to 15. The carrier gas can comprise N2and H2. According to one embodiment, the percentage by weight of hydrogen injected into the reactor relative to the total mass of the carrier gas is in the range 3% to 15%, in particular 5%. The growth speed of the wire 34 obtained can be in the range 1 pm / h to 15 pm / h, in particular 5 pm / h.

[0119] A precursor of the dopant can be injected into the reactor. For example, when the dopant is Si, the precursor can be silane (SiH4). The flow rate of the precursor can be chosen to target an average dopant concentration in the range 5*10 18 to 5*10 19 atoms / cm 3 , in particular 10 19 atoms / cm 3 .

[0120] In another embodiment, when semiconductor layer 70 is present, it is grown on each wire by MBE. According to one embodiment, for MBE growth of semiconductor layer 70, the temperature in the reactor is in the range of 800°C to 900°C. According to one embodiment, the pressure in the reactor is in the range of 3*10 -8 Torr (about 4*10 -3 Torr (about 4*10 -5 Torr (about 4*10 18 Torr (about 4*10 19 Torr (about 4*10 3 Torr (about 4*10 19 Torr (about 4*10 3 .

[0121] A precursor of the dopant can be injected into the reactor. For example, when the dopant is Si, the precursor can be silane (SiH4). The flow rate of the precursor can be selected to target an average dopant concentration in the range of 5*10 18 Torr (about 4*10 19 atoms / cm 3 Torr (about 4*10 19 atoms / cm 3 .

[0122] According to one embodiment, each layer of active region 76 is grown by MBE. In one embodiment, the MOCVD and MBE steps are performed in different reactors. In one embodiment, the method can use solid / gas source precursors for the group III and group V elements for MBE. According to one embodiment, a solid source can be used when the group III element is Ga and a gaseous or plasma precursor can be used when the group V element is N. In this source, excited neutral nitrogen molecules are formed in a region without electric field and accelerated towards the substrate by the pressure gradient of the vacuum chamber.

[0123] Forming certain layers of active region 76, particularly quantum well 86, can include injecting solid / gas precursors of additional elements into the reactor. According to one embodiment, a solid source can be used when the additional group III element is In, Ga or Al. The speed at which the additional elements are incorporated into active region 76 depends, among other things, on the lateral dimensions of active region 76, the distance between wires 20, 22, 24 and the height of active region 76 relative to the support having wires 20, 23, 24 extending therefrom.

[0124] The dopant can be injected into the reactor. For example, when the dopant is made of Si, a solid source can be used. According to one embodiment, the temperature of the solid source of the dopant element is in the range of 1000 °C to 1200 °C.

[0125] According to one embodiment, for the MBE growth of each barrier layer 88, the temperature in the reactor is in the range of 570 °C to 640 °C, in particular 620 °C. According to one embodiment, the pressure in the reactor is in the range of 3*10 -8 Torr (about 4*10 -3 mPa) to 5*10 -5 Torr (about 6.7 mPa). According to one embodiment, the plasma is generated with an RF power between 300 W and 600 W, for example 360 W. According to one embodiment, the temperature of the solid source of the group III element (e.g. Ga) is in the range of 850 °C to 950 °C, in particular 895 °C. According to one embodiment, the flow rate of the precursor gas of the group V element (e.g. N2) is in the range of 0.5 sccm to 5 sccm, in particular 1.5 sccm.

[0126] According to one embodiment, for the MBE growth of each quantum well 86, the temperature in the reactor is in the range of 570 °C to 640 °C, in particular 620 °C. According to one embodiment, the pressure in the reactor is in the range of 3*10 -8 Torr (about 4*10 -3 mPa) to 5*10 -5 Torr (about 6.7 mPa). According to one embodiment, the plasma is generated with an RF power between 300 W and 600 W, for example 360 W. According to one embodiment, the temperature of the solid source of the group III element (e.g. Ga) is in the range of 850 °C to 950 °C, in particular 895 °C. According to one embodiment, the temperature of the solid source of the additional element (e.g. In) is in the range of 750 °C to 900 °C, in particular 790 °C. According to one embodiment, the flow rate of the precursor gas of the group V element (e.g. N2) is in the range of 0.5 sccm to 5 sccm, in particular 1.5 sccm.

[0127] According to one embodiment, each layer of the semiconductor stack 78 is grown by MBE. According to one embodiment, the semiconductor layer 80 is grown in a substantially c-plane orientation. According to one embodiment, for the MBE growth of the electron blocking layer 82, the temperature in the reactor is in the range of 700 °C to 900 °C, in particular 800 °C. According to one embodiment, the pressure in the reactor is in the range of 3*10 -8 Torr (about 4*10 -3 mPa) to 5*10 -5Torr (about 6.7 mPa). According to one embodiment, the plasma is generated with an RF power between 300 W and 600 W, for example 360 ​​W. According to one embodiment, the temperature of the solid source of the group III element (for example Ga) is in the range of 850°C to 950°C, in particular 905°C. According to one embodiment, the temperature of the solid source of the additional element (for example Al) is in the range of 1000°C to 1100°C, in particular 1010°C. According to one embodiment, the flow rate of the precursor gas of the group V element (for example N2) is in the range of 0.5 sccm to 5 sccm, in particular 1.5 sccm. The dopant can be injected into the reactor. For example, when the dopant is Mg, a solid source can be used. According to one embodiment, the temperature of the solid source of the dopant element is in the range of 150°C to 350°C, in particular 190°C.

[0128] Figures 7A-7N yes Figure 1 1 , a simplified partial cross-sectional view of a structure obtained at successive steps of another embodiment of a method for manufacturing an optoelectronic device 10 is shown.

[0129] Figure 7A Shown is the structure obtained after the following steps:

[0130] - forming a support 100, which corresponds to the Figure 7A In the process, a substrate 101, at least one nucleation layer (also called a seed layer), and a plurality of layers are stacked from bottom to top. Figure 7A In the example shown are two nucleation films 102 and 103, an electrical insulating layer 104, and an electrical insulating layer 106 on the insulating layer 104, wherein the insulating layer 104 and the insulating layer 106 are made of different materials;

[0131] forming a first opening 108 in the insulating layers 104 and 106 to expose a portion of the nucleation layer 103 at a desired location for the first conductive line 20, the diameter of the first opening 108 substantially corresponding to the diameter of the first conductive line 20, forming a second opening 110 in the insulating layers 104 and 106 to expose a portion of the nucleation layer 103 at a desired location for the second conductive line 22, the diameter of the second opening 110 substantially corresponding to the diameter of the second conductive line 22, and forming a third opening 112 in the insulating layers 104 and 106 to expose a portion of the nucleation layer 103 at a desired location for the third conductive line 24, the diameter of the third opening substantially corresponding to the diameter of the third conductive line 24;

[0132] - simultaneous growth of the conductive lines 20 , 22 , 24 from the nucleation layer 103 in the openings 108 , 110 , 112 by MOCVD;

[0133] - simultaneously growing the heads 26, 28, 30 on the wires 20, 22, 24 by MBE, each head 26, 26, 30 comprising an active region 76 and a semiconductor stack 78.

[0134] As a variant, the insulating layers 104, 106 can be replaced by a single insulating layer.

[0135] The substrate 101 can correspond to the overall structure or can correspond to a layer covering a support made of another material. The substrate 101 is preferably a semiconductor substrate (for example, a substrate made of silicon, germanium, silicon carbide, a III-V compound such as GaN or GaAs), or a ZnO substrate, or an electrically conductive substrate, for example made of a metal or a metal alloy, in particular copper, titanium, molybdenum, nickel-based alloys and steel. Preferably, the substrate 101 is a monocrystalline silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing methods implemented in microelectronics. The substrate 101 can correspond to a multilayer structure of the silicon-on-insulator type, also known as SOI. The substrate 101 can be heavily doped, lightly doped or non-doped.

[0136] The nucleation layers 102, 103 are made of a material that is favorable to the growth of the wires 20, 22, 24. The material forming each nucleation layer 102, 103 can be a metal, a metal oxide, a nitride, a carbide or a boride of a transition metal of column IV, V or VI of the periodic table of the elements, or a combination of these compounds, and is preferably a nitride of a transition metal of column IV, V or VI of the periodic table of the elements or a combination of these compounds. For example, each seed layer 102, 103 can be made of aluminum nitride (AIN), aluminum oxide (AI2O3), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium boride (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), tantalum carbonitride (TaCN), magnesium nitride in the form of magnesium nitride MgxNy y in the form of magnesium nitride MgxNywhere x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride in the form of Mg3N2. The thickness of each nucleation layer 102, 103 is for example in the range 1 nm to 100 nm, preferably in the range 10 nm to 30 nm.

[0137] Each of the insulating layers 104 and 106 is made of a material chosen from the group comprising silicon oxide (SiO2), silicon nitride (Si x N y in the form of magnesium nitride MgxNywhere x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride in the form of Mg3N2. The thickness of each nucleation layer 102, 103 is for example in the range 1 nm to 100 nm, preferably in the range 10 nm to 30 nm. x N yThe insulating layers 104, 106 are made of a material of the group of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2ON2), hafnium oxide (HfO2) or aluminum oxide (Al2O3). According to one embodiment, the insulating layer 104 is made of silicon oxide and the insulating layer 106 is made of silicon nitride. The thickness of each insulating layer 104, 106 is in the range of 10 nm to 100 nm, preferably 20 nm to 60 nm, in particular equal to about 40 nm.

[0138] The growth method of the wires 20, 22, 24 is a MOCVD method as previously described. At the end of the growth step, the height of each wire 20, 22, 24 can be in the range of 250 nm to 15 pm, preferably 500 nm to 5 pm, more preferably 1 pm to 3 pm. The height of the first wire 20 is different from the height of the second wire 22 and from the height of the third wire 24. The height of the wires 20, 22, 24 depends in particular on the wire diameter and on the distance between the wires. According to one embodiment, the height of the first wire 20 is greater than the height of the second wire 22 and the height of the second wire 20 is greater than the height of the third wire 24.

[0139] Each seed layer 102, 103 and each insulating layer 104, 106 can be deposited, for example, by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), CVD, physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0140] Figure 7B A structure obtained after deposition of a dielectric layer 113 on all the wires 20, 22, 24 and on the insulating layer 106 between the wires 20, 22, 24 is shown.

[0141] The dielectric layer 113 can be made of the same material as the insulating layer 106. According to one embodiment, the minimum thickness of the layer 113 is greater than the sum of the height of the smallest wire 20, 22, 24 and the height of the associated head 26, 28, 30. Preferably, the minimum thickness of the layer 113 is greater than the sum of the height of the largest wire 20, 22, 24 and the height of the associated head 26, 28, 30.

[0142] For example, the thickness of the dielectric layer 113 is in the range of 250 nm to 15 pm, preferably 300 nm to 5 pm, for example approximately equal to 2 pm. The insulating layer 113 can be formed by the same method as the method used to form the insulating layers 104, 106.

[0143] Figure 7CThe structure obtained after thinning and planarizing the insulating layer 113 and the portions of the heads 26, 28, 30 to define a planar surface 114 at the level of the insulating layer 106 (for example in the range 150 nm to 10 μιη) is shown. The etching is for example a CMP (Chemical Mechanical Planarization). The presence of the insulating layer 113 between the conductive lines 20, 22, 24 enables the implementation of a CMP type etching method, which would be difficult or even impossible if only the conductive lines were present. After this step, all the conductive head assemblies 20-26, 22-28, 24-30 have the same height. The etching of the insulating layer 113 and of a portion of the conductive lines 20, 22, 24 can be performed in several steps. As a variant, when the conductive head assemblies 20-26, 22-28, 24-30 have substantially the same height, there can be no thinning and planarizing step of the insulating layer 83 and of the portions of the heads 26, 28, 30.

[0144] Figure 7D The structure obtained after complete removal of the dielectric layer 113 to expose the insulating layer 106 and the conductive head assemblies 20-26, 22-28, 24-30 is shown. The insulating layer 106 can then act as an etch stop layer during the etching of the dielectric layer 113. The removal of the dielectric layer 113 can be performed by wet etching. As a variant, the etching of the dielectric layer 113 can be only partial, a residual layer remaining on the insulating layer 106.

[0145] Figure 7E The structure obtained after the following steps is shown:

[0146] - forming an insulating layer 32;

[0147] - forming an insulating layer 34; and

[0148] - etching or thinning the insulating layer 34 through a portion of the thickness of the insulating layer 34 to define a substantially planar surface 116.

[0149] The insulating layer 32 can be formed by conformal deposition (for example by LPCVD). The method of forming the insulating layer 32 is preferably performed at a temperature lower than 700°C to avoid damaging the active area of the light emitting diode. Furthermore, a method of the LPCVD type enables good filling to be obtained between the conductive lines 20, 22, 24. The deposition thickness of the insulating layer 32 can be in the range 100 nm to 1 μιη, for example approximately 500 nm. The insulating layer 34 can be formed for example by conformal deposition (for example by PECVD). The deposition thickness of the insulating layer 34 can be greater than or equal to 2 μιη. The partial etching of the insulating layer 34 can be performed by CMP. The stop of the etching can be performed in the insulating layer 34 (as shown) or in the insulating layer 32, but in any case before the heads 26, 28, 30 are exposed. Figure 7E ​

[0150] Figure 7F The structure obtained after etching the insulating layers 32, 34 to expose the upper surfaces of the heads 26, 28, 30 is shown. The etching is for example an etching of the reactive ion etching type (RIE) or an inductively coupled plasma etching (ICP). Since the heads 26, 28, 30 can have different sizes, some heads 26, 28, 30 can be more exposed than others. The heads 26, 28, 30 are not etched in this step. The etching is preferably an anisotropic etching. The not shown parts of the layer 32 can remain on the sidewalls of the heads 26, 28, 30. The layer located at the top of the heads 26, 28, 30 acts as an etching stop layer. According to one embodiment, an additional layer is added at the top of the heads 26, 28, 30 to act as an etching stop layer when the heads 26, 28, 30 are formed. It can be an AlN layer.

[0151] Figure 7G The structure obtained after the following steps is shown:

[0152] - removal of the etching stop layer when it is present on the heads 26, 28, 30;

[0153] - deposition of a metal layer, for example with a thickness of 0.5 pm, on the structure shown in Figure 7E - for example by cathodic sputtering;

[0154] - etching of the metal layer to define the conductive layers 42, 44, 46, 48.

[0155] When the etching stop layer on the heads 26, 28, 30 is made of AlN, they can be removed by tetramethylammonium hydroxide type (TMAH) etching. Before forming the conductive layers 42, 44, 46, 48, it is possible to form separate metal parts on the whole structure. This can be performed by depositing a metal layer, for example of nickel or platinum, with a thickness of 1 nm and a thermal annealing step, for example at a temperature of 550°C, so as to form separate parts.

[0156] Figure 7H The structure obtained after the following steps is shown:

[0157] - deposition of an insulating layer 50 on the structure shown in Figure 7G - for example by cathodic sputtering; and

[0158] - formation of conductive pads 52, 54, 56, 58, for example made of copper.

[0159] Figure 7IThe structure obtained after the control chip 14 has been bonded to the optoelectronic chip 12 is shown. The bonding of the control chip 14 to the optoelectronic chip 12 can be performed by using an interposer such as a connecting microsphere (not shown). As a variant, the bonding of the control chip 14 to the optoelectronic chip can be performed by direct bonding without using an interposer. The direct bonding can comprise a direct metal-metal bonding of the metal areas of the control chip 14, in particular the conductive pads 62, and the metal areas of the optoelectronic chip 12, in particular the conductive pads 52, 54, 56, 58, and a dielectric-dielectric bonding of the dielectric areas, in particular the insulating layer 50 of the control chip 14, and the dielectric areas of the optoelectronic chip 12, in particular the insulating layer 50. The bonding of the control chip 14 to the optoelectronic chip 12 can be performed by a thermo-compression method, in which the optoelectronic chip 12 is pressed against the control chip 14 by applying pressure and heat.

[0160] Figure 7J The structure obtained after the following steps is shown:

[0161] - removal of the substrate 101 ;

[0162] - removal of the seed layers 102, 103;

[0163] - removal of the insulating layers 104 and 106;

[0164] - partial etching of the insulating layer 32, the insulating layer 34 and the conductive lines 20, 22, 24 to define a substantially planar surface 118.

[0165] The removal of the substrate 101 can be performed by grinding and / or wet etching. The removal of the seed layers 102, 103, the insulating layer 32, the insulating layer 34 and the conductive lines 20, 22, 24 can be performed by wet etching, dry etching or by CMP. The insulating layer 104 or 106 can act as an etch stop layer during the etching of the seed layer 103.

[0166] Figure 7K The structure obtained after forming the conductive layer 18 on the surface 118 is shown, for example by depositing a TCO layer, for example with a thickness of 50 nm, over the entire surface 118 and etching the layer by photolithography techniques to leave only the TCO layer 18.

[0167] Figure 7L The structure obtained after etching an opening 36 in the insulating layer 34 through the entire thickness of the insulating layer 34 to expose the conductive layer 48 is shown. This can be performed by photolithography techniques.

[0168] Figure 7MThe structure obtained after forming the electrically conductive layer 38 in the openings 36 and on the surface 118 in contact with the electrically conductive layer 18 is shown. This can be performed by depositing a stack of electrically conductive layers of the Ti / TiN / AlCu type, for example, on the whole structure on the side of the surface 118 and etching this stack by means of photolithographic techniques to keep only the electrically conductive layer 38.

[0169] Figure 7N The structure obtained after forming the insulating layer 16 delimiting the surface 17 on the electrically conductive layer 18 is shown. It is, for example, a layer of SiON of thickness 1 pm deposited by PECVD.

[0170] An additional step, also called texturing step, can be provided to form a raised area on the surface 17 to increase the extraction of light.

[0171] Reducing the height of the wires on the back face can be performed by a CMP type method (as described previously) or any other dry etching or wet etching method. The height of the wires obtained, in particular the wires made of GaN, can be chosen to increase the extraction of light from the wire feet by optical interaction within the wire itself. Moreover, this height can be chosen to facilitate the optical coupling between the different wires, thus increasing the collective emission of the wire assembly.

[0172] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these different embodiments and variants can be combined and that other variants will occur to the person skilled in the art. In particular, although in the previously described embodiments the optoelectronic device comprises two chips bonded to each other, it is clear that the optoelectronic device can comprise a single chip, the electronic light-emitting diode control circuit being formed in an integrated manner with the light-emitting diode. Finally, the actual implementation of the described embodiments and variants is within the capabilities of the person skilled in the art on the basis of the functional indications given above.

Claims

1. An optoelectronic device (10) comprising a first three-dimensional light-emitting diode, a second three-dimensional light-emitting diode, and a third three-dimensional light-emitting diode having an axial configuration, each light-emitting diode comprising a semiconductor element (20, 22, 24) and an active region (76) located on the semiconductor element, each semiconductor element corresponding to a microwire, a nanowire, a conical element in the nanometer or micrometer range, or a truncated conical element in the nanometer or micrometer range, the first three-dimensional light-emitting diode being configured to emit a first radiation at a first wavelength, the semiconductor element of the first three-dimensional light-emitting diode having a first diameter (D1), the second three-dimensional light-emitting diode being configured to emit a second radiation at a second wavelength, the semiconductor element of the second three-dimensional light-emitting diode having a second diameter (D2), and the third three-dimensional light-emitting diode being configured to emit a third radiation at a third wavelength, the semiconductor element of the third three-dimensional light-emitting diode having a third diameter (D3), the first diameter (D1) being smaller than the second diameter (D2), and the second diameter (D2) being smaller than the third diameter (D3), the first wavelength being greater than the third wavelength, and the second wavelength being greater than the first wavelength.

2. The optoelectronic device according to claim 1, wherein The first diameter (D1) varies between 80 nm and 150 nm.

3. The optoelectronic device according to claim 1, wherein The second diameter (D2) varies between 200 nm and 350 nm.

4. The optoelectronic device according to claim 1, wherein The third diameter (D3) varies between 370 nm and 500 nm.

5. The optoelectronic device according to claim 1, wherein The first wavelength is in the range of 510 nm to 570 nm.

6. The optoelectronic device according to claim 1, wherein The second wavelength is in the range of 600 nm to 720 nm.

7. The optoelectronic device according to claim 1, wherein The third wavelength is in the range of 430 nm to 490 nm.

8. The optoelectronic device (10) of claim 1, comprising a first optoelectronic circuit (12) bonded to a second electronic circuit (14), the second electronic circuit (14) comprising a conductive pad (62), the first optoelectronic circuit comprising pixels and comprising, for each pixel: - a first conductive layer (18); - for each of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third three-dimensional light-emitting diode, the semiconductor element (20, 22, 24) extends perpendicular to the first conductive layer and contacts the first conductive layer, and the active region (76) is located on the end of the semiconductor element opposite the first conductive layer; as well as a second conductive layer (42), a third conductive layer (44), a fourth conductive layer (46), and a fifth conductive layer (48) electrically coupled to the conductive pad (62), the second conductive layer (42) being coupled to the active region (76) of the first three-dimensional light-emitting diode, the third conductive layer (44) being coupled to the active region (76) of the second three-dimensional light-emitting diode, the fourth conductive layer (46) being coupled to the active region (76) of the third three-dimensional light-emitting diode, and the fifth conductive layer (48) being coupled to the first conductive layer.

9. The optoelectronic device according to claim 1, wherein Each active region (76) includes a single quantum well or multiple quantum wells.

10. The optoelectronic device according to claim 1, wherein The semiconductor elements (20, 22, 24) and the active region are made of III-V compounds.

11. The optoelectronic device according to claim 1, wherein The semiconductor elements (20, 22, 24) of the first three-dimensional light emitting diode, the second three-dimensional light emitting diode, and the third three-dimensional light emitting diode are formed by MOCVD.

12. The optoelectronic device according to claim 1, wherein The active regions (76) of the first three-dimensional light emitting diode, the second three-dimensional light emitting diode and the third three-dimensional light emitting diode are formed by MBE.

13. The optoelectronic device according to claim 1, wherein The semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third three-dimensional light-emitting diode are located on a substrate (101) and are in contact with a material suitable for epitaxial growth of the semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third three-dimensional light-emitting diode.

14. The optoelectronic device according to claim 1, wherein The first three-dimensional light emitting diode, the second three-dimensional light emitting diode, and the third three-dimensional light emitting diode form a monolithic structure.

15. A method for manufacturing an optoelectronic device (10) according to claim 1, comprising the following consecutive steps: - forming the semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode and the third three-dimensional light-emitting diode simultaneously; and - simultaneously forming active regions (76) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third three-dimensional light-emitting diode on the semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third three-dimensional light-emitting diode; - the first diameter (D1) varies between 80 nm and 150 nm, the second diameter (D2) varies between 200 nm and 350 nm, and the third diameter (D3) varies between 370 nm and 500 nm; - the first wavelength is in the range of 510 nm to 570 nm, the second wavelength is in the range of 600 nm to 720 nm, and the third wavelength is in the range of 430 nm to 490 nm.

16. The method according to claim 15, wherein The semiconductor elements (20, 22, 24) of the first three-dimensional light emitting diode, the second three-dimensional light emitting diode and the third three-dimensional light emitting diode are formed by MOCVD.

17. The method according to claim 15, wherein: The active regions (76) of the first three-dimensional light emitting diode, the second three-dimensional light emitting diode and the third three-dimensional light emitting diode are formed by MBE.

18. The method according to claim 15, comprising the following consecutive steps: - forming the semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third three-dimensional light-emitting diode simultaneously on the support (100), and forming the active regions (76) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third light-emitting diode on the semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode, and the third light-emitting diode; - forming an electrical insulation layer (32) between the three-dimensional semiconductor elements (20, 22, 24) of the first three-dimensional light-emitting diode, the second three-dimensional light-emitting diode and the third three-dimensional light-emitting diode; and - Removing the support.

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