Reset method, configuration method, electronic device and storage medium of hardware

Abstract

A hardware reset method, a configuration method for hardware reset, an electronic device and a storage medium. The hardware reset method comprises: converting a plurality of reset events for a plurality of hardware abstractions into a plurality of interrupt events; determining, by a micro control unit, a target hardware abstraction corresponding to a target interrupt event in the plurality of interrupt events and a reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event. The hardware reset method can modify the reset timing of the target interrupt event by updating the micro control unit after chip tape-out is completed, thereby improving the reliability and flexibility of hardware reset. Since the control path delay of the micro control unit to other hardware abstractions is small, the real-time performance when controlling complex reset timing is improved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a hardware reset method, a configuration method for hardware reset, an electronic device, and a storage medium. Background Technology

[0002] Network I / O virtualization is a crucial component of server virtualization technology. While computational virtualization (such as CPU and memory virtualization) has matured significantly in the server virtualization field, network I / O virtualization technology has lagged behind. Currently, there are three main network I / O virtualization technologies: software emulation, NIC passthrough, and Single Root I / O Virtualization (SR-IOV). Software emulation uses a virtualization intermediate software layer (hypervisor layer) to simulate a virtual network interface card (NIC), achieving an interface identical to the physical device, but its performance is relatively poor. NIC passthrough allows virtual machines to bypass the hypervisor layer and directly access physical I / O devices, offering high performance; however, at any given time, a physical I / O device can only be exclusively used by one virtual machine. SR-IOV not only inherits the high-performance advantages of NIC passthrough but also supports cross-virtual machine sharing of physical I / O devices, showing promising application prospects. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a hardware reset method, the reset method comprising: converting a plurality of reset events for a plurality of hardware abstractions into a plurality of interrupt events, wherein the plurality of interrupt events correspond to the plurality of hardware abstractions respectively; providing the plurality of interrupt events to a microcontroller unit; the microcontroller unit determining a target hardware abstraction corresponding to a target interrupt event among the plurality of interrupt events and a reset timing sequence of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing sequence of the target interrupt event.

[0004] For example, in a hardware reset method provided in at least one embodiment of this disclosure, providing the plurality of interrupt events to the microcontroller includes: when the number of the plurality of interrupt events is greater than the number of input interfaces of the microcontroller, merging the plurality of interrupt events into a first merged signal and providing the first merged signal to the microcontroller; or, when the number of the plurality of interrupt events is less than or equal to the number of input interfaces of the microcontroller, providing the plurality of interrupt events to the plurality of input interfaces of the microcontroller respectively.

[0005] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the first merged signal includes a sideband signal, the sideband signal includes the target interrupt event, and the microcontroller determines the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event among the plurality of interrupt events, including: the microcontroller reads the interrupt cause register corresponding to the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0006] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the first merged signal includes an in-band signal, the in-band signal containing the target interrupt event and the address information of the target interrupt event, and the microcontroller unit determines the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event among the plurality of interrupt events, including: the microcontroller unit reads the address information of the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0007] For example, in the hardware reset method provided in at least one embodiment of this disclosure, a reset operation corresponding to the target hardware abstraction is triggered based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, including: setting a reset register corresponding to the target hardware abstraction by the microcontroller unit based on the target hardware abstraction corresponding to the target interrupt event; and mapping the reset operation corresponding to the target hardware abstraction by the reset register based on the reset timing of the target interrupt event.

[0008] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the configuration space corresponding to each of the plurality of hardware abstractions includes a start reset bit, and the reset method further includes: setting the start reset bit in the configuration space corresponding to the target hardware abstraction to 1 to obtain a reset event for the target hardware abstraction.

[0009] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the plurality of hardware abstractions include a first hardware abstraction and a plurality of second hardware abstractions. After triggering a reset operation corresponding to the target hardware abstraction, when the target hardware abstraction is the first hardware abstraction, the first hardware abstraction and the plurality of second hardware abstractions are reset; or, when the target hardware abstraction is one of the plurality of second hardware abstractions, only the target hardware abstraction is reset.

[0010] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the reset event includes a functional level reset.

[0011] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the plurality of hardware abstractions include a first hardware abstraction and a plurality of second hardware abstractions, and the reset method further includes: triggering a reset operation corresponding to a second reset event to reset the microcontroller unit, the first hardware abstraction, and the plurality of second hardware abstractions.

[0012] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the second reset event includes a cold reset, a warm reset, or a thermal reset.

[0013] For example, in the hardware reset method provided in at least one embodiment of this disclosure, there is first data to be cleared in the data path corresponding to the target interrupt event. Before triggering the reset operation corresponding to the target hardware abstraction, the reset method further includes: clearing the first data to be cleared; after the first data to be cleared is cleared, modifying the flag bit corresponding to the first data to be cleared to 0; and clearing the flag bit corresponding to the first data to be cleared.

[0014] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the first buffer includes multiple entries, each of the multiple entries having a corresponding tag. Cleaning the first data to be cleaned includes: using the microcontroller to set a cleanup register to determine the target entry corresponding to the target interrupt event among the multiple entries; cleaning the target entry and releasing the target tag corresponding to the target entry; and generating a first response signal based on the released target tag to indicate that the first data to be cleaned has been cleaned.

[0015] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the first data to be cleaned records the return status of multiple first completion packets. Cleaning the first data to be cleaned includes: using the microcontroller to set a time register to determine whether to start the cleanup; if some of the multiple first completion packets have not returned after a first predetermined time, the cleanup is started.

[0016] For example, in the hardware reset method provided in at least one embodiment of this disclosure, cleaning the first data to be cleaned further includes: using the microcontroller to set a discard register to determine whether there is a newly returned first completion packet in the portion of the first completion packet after the cleaning is enabled; and discarding the newly returned first completion packet.

[0017] For example, in the hardware reset method provided in at least one embodiment of this disclosure, the first data to be cleaned further includes a plurality of first requests, and cleaning the first data to be cleaned further includes: using the microcontroller to set a discard register to determine whether there are any new first requests after the cleaning is started; and discarding the new first requests.

[0018] At least one embodiment of this disclosure also provides a configuration method for hardware reset, wherein the hardware is configured to implement multiple hardware abstractions, and the hardware includes a microcontroller unit for reset operations. The configuration method includes: modifying firmware in the microcontroller unit to update an interrupt handler. The firmware runs the interrupt handler during operation, and the interrupt handler performs the following actions in response to interrupt events received by the microcontroller unit: determining a target hardware abstraction corresponding to a target interrupt event among the multiple interrupt events and the reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction and the reset timing of the target interrupt event.

[0019] For example, in the configuration method for hardware reset provided in at least one embodiment of this disclosure, the runtime of the interrupt handler does not exceed a second predetermined time.

[0020] At least one embodiment of this disclosure also provides an electronic device, the electronic device comprising: an electronic device configured to provide a plurality of hardware abstractions during operation, wherein the plurality of hardware abstractions includes a first hardware abstraction and one or more second hardware abstractions, the first hardware abstraction being configured to manage the one or more second hardware abstractions, the electronic device being further configured to convert a plurality of reset events for the plurality of hardware abstractions into a plurality of interrupt events, wherein the plurality of interrupt events correspond to the plurality of hardware abstractions respectively; and a microcontroller unit configured to, when implementing the plurality of hardware abstractions, receive the plurality of interrupt events, determine a target hardware abstraction corresponding to a target interrupt event among the plurality of interrupt events and a reset timing sequence of the target interrupt event, and trigger a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing sequence of the target interrupt event.

[0021] For example, in an electronic device provided in at least one embodiment of this disclosure, the microcontroller is further configured to set a reset register corresponding to each of the plurality of hardware abstractions, and to map the reset operation of the electronic device using the plurality of reset registers.

[0022] At least one embodiment of this disclosure also provides an electronic device, the electronic device comprising: one or more processors; one or more memories storing one or more computer program modules; wherein the one or more computer program modules are stored in the one or more memories and configured to be executed by the one or more processors, the one or more computer program modules being used to implement a hardware reset method or a configuration method for hardware reset provided in any embodiment of this disclosure.

[0023] At least one embodiment of this disclosure also provides a storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement a hardware reset method or a configuration method for hardware reset provided in any embodiment of this disclosure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0025] Figure 1 This is a schematic diagram of multiple hardware abstractions;

[0026] Figure 2 An exemplary flowchart illustrating a hardware reset method provided in at least one embodiment of this disclosure;

[0027] Figure 3 A schematic diagram of an example of a startup reset bit in the configuration space corresponding to a hardware abstraction provided in at least one embodiment of this disclosure;

[0028] Figure 4A A schematic diagram illustrating an example of a hardware reset method provided in at least one embodiment of this disclosure;

[0029] Figure 4B This is a schematic diagram of a hardware reset method;

[0030] Figure 4C This is a schematic diagram of another hardware reset method;

[0031] Figure 5 A schematic diagram illustrating an example of a flag bit corresponding to the first data to be cleaned in the configuration space corresponding to the hardware abstraction provided in at least one embodiment of this disclosure;

[0032] Figure 6 A schematic diagram of another example of a hardware reset method provided in at least one embodiment of this disclosure;

[0033] Figure 7 Another exemplary flowchart of a hardware reset method provided in at least one embodiment of this disclosure;

[0034] Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure;

[0035] Figure 9 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure;

[0036] Figure 10 A schematic block diagram of yet another electronic device provided for at least one embodiment of this disclosure; and

[0037] Figure 11 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0040] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0041] SR-IOV supports virtualizing multiple virtual PCIe devices from a single physical PCIe device, and then directly connecting these virtual PCIe devices to each virtual machine (VM), enabling applications where a single physical PCIe device supports multiple VMs. SR-IOV uses two types of hardware abstraction: Physical Function (PF) and Virtual Function (VF). For example, PF provides a full-featured hardware abstraction in PCIe semantics, while VF is a lightweight hardware abstraction of PF.

[0042] For example, each SR-IOV device can have at least one PF, and each PF can expand into several VFs. The PF contains the SR-IOV functional architecture and is used to manage SR-IOV functions. The PF is a full-featured PCIe function unit, which can be discovered, managed, and processed like other PCIe devices. For instance, when the SR-IOV function is disabled, the PF can be used as a functional unit within a PCIe device. Taking a physical network interface card (NIC) supporting SR-IOV as an example, the hardware is presented as an independent NIC. Each VF has its own independent PCIe configuration space and can share the same physical resources (share the same physical network port) with other VFs associated with the same PF. The PF is responsible for managing all VFs.

[0043] The PCIe protocol includes several reset mechanisms, such as Cold Reset, Warm Reset, and Hot Reset. For example, a cold reset occurs when the device's main power is on and the power cycle is activated; a warm reset can be initiated by changing the system power state without shutting down the main power; and a hot reset is achieved in software by initializing the secondary bus reset bit in the bridge controller configuration register. The PCIe protocol also defines a function-level reset (FLR) function at the functional unit level. FLR is optional if SR-IOV is not implemented, but mandatory if SR-IOV is implemented.

[0044] Figure 1 This is a schematic diagram of multiple hardware abstractions. Figure 1 This illustrates a PCIe device with one power field (PF) and two virtual fairings (VF1 and VF2), but the actual number of PFs and VFs in a PCIe device is not limited to this.

[0045] For example, such as Figure 1As shown, in a PCIe device, each PF and VF has a configuration space for mapping its register set (BAR1...BARn, where n is a positive integer). The PF driver resides in the host operating system (OS), while the VF driver resides in the guest operating system of the virtual machine (VM); the PF or VF driver operates on its register set to enable its functionality. For example, Figure 1 This illustrates a scenario where a VM accesses a VF. In more complex cases, a VM can also access multiple VFs.

[0046] For example, such as Figure 1 As shown, because the capability registers related to VF management (e.g., SR-IOV capability, VF-Resizable-BAR capability, etc.) are located in the PF's configuration space, the PF can be responsible for the management and scheduling of different VFs. Once the SR-IOV function is enabled in the PF, the configuration space of each VF can be accessed through the PF's bus, device, and function number (routing ID). Correspondingly, the PF's FLR can reset the state of all VFs, meaning the reset domain of the PF's FLR is much larger than that of the VF's FLR.

[0047] For example, the FLR reset method allows software to reset only one VF in a multi-functional device without affecting the links shared by all VFs or PFs. For instance, in a virtualized environment, since different VFs time-division multiplex the same hardware, another important function of the VF's FLR is to achieve data isolation between different VFs. For example, when VF1's time slice ends, the PF will schedule a new time slice for VF2 to use the hardware; during the switch from VF1 to VF2, an important step is to clean up residual data in VF1's hardware data path, ensuring that any residual data from VF1 is cleared before VF2 starts running.

[0048] For example, to achieve FLR for a PF or VF, on the one hand, the function registers of the PCIe device can be used to subdivide the reset signals corresponding to the PF and multiple VFs respectively. However, once these reset signals are generated, they are difficult to modify, especially after the chip tapeout is completed. Even if unexpected extreme conditions are encountered, they cannot be modified. On the other hand, reset registers can be set separately for the PF and multiple VFs, and the software on the host can perform fine-grained reset control on each reset register. However, the software can only configure multiple reset registers sequentially and cannot achieve parallel control. Moreover, due to the long delay between the host and the PCIe device (the delay of a two-stage PCIe switch is generally more than 600ns), the time cost is increased, thus making real-time control impossible.

[0049] At least one embodiment of this disclosure provides a hardware reset method, the reset method comprising: converting multiple reset events for multiple hardware abstractions into multiple interrupt events, wherein the multiple interrupt events correspond to the multiple hardware abstractions respectively; providing the multiple interrupt events to a microcontroller unit; the microcontroller unit determining the target hardware abstraction corresponding to the target interrupt event among the multiple interrupt events and the reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0050] At least one embodiment of this disclosure also provides a configuration method for hardware reset, wherein the hardware is configured to implement multiple hardware abstractions, and the hardware includes a microcontroller unit for reset operations. The configuration method includes: modifying firmware in the microcontroller unit to update an interrupt handler. The firmware runs the interrupt handler during operation, and the interrupt handler performs the following actions in response to interrupt events received by the microcontroller unit: determining a target hardware abstraction corresponding to a target interrupt event among multiple interrupt events and the reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction and the reset timing of the target interrupt event.

[0051] At least one embodiment of this disclosure also provides at least one electronic device and a storage medium for implementing the hardware reset method of the above embodiments or the configuration method for hardware reset.

[0052] The reset method, configuration method, electronic device, and storage medium provided in at least one embodiment of this disclosure utilize a microcontroller unit to assist in processing the reset operation of the target hardware abstraction. Even after the chip tape-out is completed, the reset timing of the target interrupt event can still be modified by updating the microcontroller unit, thereby improving the reliability and flexibility of hardware reset. Since the microcontroller unit and the PCIe device are located on the same chip, the control path delay from the microcontroller unit to other hardware abstractions is small, improving the real-time performance when controlling complex reset timings.

[0053] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0054] Figure 2 An exemplary flowchart of a hardware reset method provided for at least one embodiment of this disclosure.

[0055] For example, such as Figure 2 As shown, at least one embodiment of this disclosure provides a hardware reset method, which may include the following steps S110 to S140.

[0056] Step S110: Convert multiple reset events for multiple hardware abstractions into multiple interrupt events;

[0057] Step S120: Provide multiple interrupt events to the microcontroller unit;

[0058] Step S130: The microcontroller unit determines the target hardware abstraction and reset timing of the target interrupt event among multiple interrupt events;

[0059] Step S140: Based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, trigger the reset operation corresponding to the target hardware abstraction.

[0060] For example, in step S110, multiple interrupt events correspond to multiple hardware abstractions. In some examples, the multiple hardware abstractions may include at least one PF and at least one VF. The embodiments of this disclosure do not limit the types of hardware abstractions or the number of PFs or VFs. In some examples, reset events include functional level resets (FLRs); for example, multiple reset events may be FLR events corresponding to different PFs or VFs. Reset events may also be selected from other types as needed, and the embodiments of this disclosure do not limit this selection.

[0061] For example, in step S120, the microcontroller unit can be a lightweight microprocessor (MCU), which is located in the same PCIe device as the hardware abstraction and can be used to assist in the initialization of the control chip, power clock reset, etc. The microcontroller unit can also be selected from other types of processors that can control or process interrupt events according to actual needs, and the embodiments of this disclosure do not limit this.

[0062] For example, in step S130, the reset operations of multiple hardware abstractions are executed sequentially according to a reset sequence, meaning that the reset sequence of each hardware abstraction is different among the multiple hardware abstractions. The target interrupt event corresponds to a specific PF or VF (e.g., Figure 1 Taking the reset event of PF, VF1 or VF2 in the microcontroller as an example, after the microcontroller receives the interrupt event, it first determines which PF or VF the target interrupt event is, and then determines the reset timing of the target interrupt event (i.e. when the reset operation of the target interrupt event is executed).

[0063] For example, in step S140, based on the reset timing of the target hardware abstraction and the target interrupt event determined in step S130, the microcontroller unit can trigger a reset operation corresponding to the target hardware abstraction. In some examples, the specific reset operation can be performed on the hardware. In some examples, the reset operation can be a functional level reset (FLR), or other reset operation types can be selected as needed; the embodiments of this disclosure do not limit this.

[0064] In some examples, the configuration space corresponding to each of the multiple hardware abstractions includes a start-reset bit. The reset method provided in at least one embodiment of this disclosure further includes: setting the start-reset bit in the configuration space corresponding to the target hardware abstraction to 1 to obtain a reset event for the target hardware abstraction.

[0065] Figure 3 This is a schematic diagram illustrating an example of a boot reset bit in the configuration space corresponding to a hardware abstraction provided in at least one embodiment of this disclosure. For example, Figure 3 Examples are used for, such as Figure 2 The hardware reset method shown; in Figure 3 In the example, the reset event is, for example, a functional level reset (FLR).

[0066] For example, such as Figure 3 As shown, the configuration space corresponding to each hardware abstraction includes a device status section and a device control section. The device control section includes an Initiate FLR bit. For example, the Initiate FLR bit can be... Figure 3 The 15th bit of the device control section (i.e., Initiate Function Level Reset). For example, when the host initiates a reset operation on the target hardware abstraction, it sends a "write 1" transaction (CfgWr=1) to the start reset bit in the configuration space corresponding to the target hardware abstraction to set the start reset bit to 1 (i.e., Initiate FLR bit=1), thereby initiating the reset operation of the target hardware abstraction.

[0067] In some examples, Figure 2 Step S120 may include: when the number of multiple interrupt events is greater than the number of input interfaces of the microcontroller, merging the multiple interrupt events into a first merged signal; and providing the first merged signal to the microcontroller. Alternatively, in other examples, Figure 2 Step S120 may include: when the number of multiple interrupt events is less than or equal to the number of input interfaces of the microcontroller, providing the multiple interrupt events to the multiple input interfaces of the microcontroller respectively.

[0068] For example, the first merging signal includes a sideband signal, which contains the target interrupt event. Figure 2 Step S130 may include: the microcontroller unit reading the interrupt cause register corresponding to the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0069] For example, the first merging signal includes in-band signals, which contain the target interrupt event and its address information. Figure 2 Step S130 may include: reading the address information of the target interrupt event by the microcontroller unit to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0070] In some examples, Figure 2 Step S140 may include: setting a reset register corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event by the microcontroller unit; and mapping a reset operation corresponding to the target hardware abstraction by the reset register based on the reset timing of the target interrupt event.

[0071] In some examples, multiple hardware abstractions include a first hardware abstraction and multiple second hardware abstractions, in Figure 2 Following step S140, when the target hardware abstraction is the first hardware abstraction, the first hardware abstraction and the plurality of second hardware abstractions are reset; or, when the target hardware abstraction is one of the plurality of second hardware abstractions, only the target hardware abstraction is reset. In some examples, the first hardware abstraction can be a PF, and the plurality of second hardware abstractions can be a plurality of VFs.

[0072] In some examples, the reset method further includes triggering a reset operation corresponding to a second reset event to reset the microcontroller unit, the first hardware abstraction, and the plurality of second hardware abstractions. For example, the second reset event includes a cold reset, a warm reset, or a hot reset.

[0073] At least one embodiment of this disclosure also provides a configuration method for hardware reset, wherein the hardware is configured to implement multiple hardware abstractions, and the hardware includes a microcontroller unit for reset operations. The configuration method includes modifying the firmware in the microcontroller unit to update an interrupt handler. For example, the firmware runs the interrupt handler during operation, and the interrupt handler is used to perform, for example, actions on interrupt events received by the microcontroller unit. Figure 2 Steps S130 and S140 in the example. In some examples, the interrupt handler runs for no more than a second predetermined time (e.g., the PCIe protocol specifies that the FLR must be completed within 100ms).

[0074] Figure 4A This is a schematic diagram illustrating an example of a hardware reset method provided in at least one embodiment of this disclosure. For example, Figure 4A For example Figure 2 A specific example of a hardware reset method is shown.

[0075] For example, such as Figure 4A As shown, a microcontroller unit (MCU) for reset operations can be configured in a PCIe device. For example, the MCU can access registers of other nodes or individual registers in the hardware abstraction configuration space; the MCU can access the various registers via a bus interface. In some examples, the bus can be a network-on-chip (NOC) based on a certain protocol, such as for memory-mapping I / O (MMIO) transfers. The embodiments of this disclosure do not limit the type of bus.

[0076] For example, in Figure 4A In the example shown, multiple hardware abstractions include a PF and the VF1 and VF2 it controls, and the reset events corresponding to these hardware abstractions are of type Functional Level Reset (FLR). For example, via... Figure 3 The method shown sets the start-reset ratio of PF, VF1, or VF2 to 1, starts the FLR of PF, VF1, or VF2, and then issues the reset signals corresponding to PF, VF1, and VF2 as reset events for PF, VF1, and VF2, respectively; furthermore, based on... Figure 2 The step S110 shown converts multiple reset events into multiple interrupt events (interrupt event 1, interrupt event 2, interrupt event 3) corresponding to PF, VF1, and VF2 respectively.

[0077] For example, such as Figure 4A As shown, based on Figure 2In step S120, multiple interrupt events are aggregated to an interrupt aggregator for further processing. Then, the processed multiple interrupt events are input to an interrupt controller configured on the periphery of the microcontroller. Furthermore, the interrupt controller provides the processed multiple interrupt events to the microcontroller.

[0078] For example, such as Figure 4A As shown, the interrupt aggregator can vary depending on the specific implementation logic of the interrupt controller. On the interrupt aggregator, multiple interrupt events can be processed as follows:

[0079] 1. When the number of multiple interrupt events is less than or equal to the number of input interfaces of the microcontroller, the multiple interrupt events are provided to the multiple input interfaces of the microcontroller respectively; for example, if the total number of PF, VF1 and VF2 is less than the number of input interfaces of the microcontroller, one input interface of the microcontroller can be allocated to each of PF, VF1 and VF2.

[0080] 2. When the number of multiple interrupt events exceeds the number of input interfaces of the microcontroller unit, the multiple interrupt events can be combined into a first combined signal, and then the first combined signal can be provided to the microcontroller unit:

[0081] 2.1 If the number of multiple interrupt events is only slightly greater than the number of input interfaces of the microcontroller, then the multiple interrupt events can be simply merged. In this case, the first merged signal is a sideband signal.

[0082] 2.2 If the number of multiple interrupt events is much greater than the number of input interfaces of the microcontroller,

[0083] In this case, an in-band input interface is required, and the first combined signal is an in-band signal.

[0084] The interrupt controller then translates the in-band signals and provides them to the microcontroller unit.

[0085] For example, a microcontroller has a memory interface (e.g., a ROM port) for loading modifiable firmware, which can run an interrupt service router (ISR) during operation; the interrupt service router is used to perform actions such as... Figure 2 Steps S130 and S140 are described in detail. In particular, since the reset registers, reset timings, etc., corresponding to different hardware abstractions are different, the contents of the interrupt handlers corresponding to different hardware abstractions are also different.

[0086] For example, such as Figure 4AAs shown, based on Figure 2 In step S130, as shown, after the microcontroller receives multiple interrupt events, it first determines which of PF, VF1, and VF2 is the target interrupt event, and then determines the reset timing of the target interrupt event (i.e., when exactly the reset operation of the target interrupt event will be executed):

[0087] (1) When multiple interrupt events are provided to multiple input interfaces of the microcontroller, the microcontroller can directly determine which target interrupt event corresponds to the target interrupt event by distinguishing the input of each interface;

[0088] (2) When the first merging signal is a sideband signal, by running the interrupt handler, the microcontroller polls the interrupt cause register corresponding to each interrupt event via the bus, and then reads the interrupt cause register corresponding to the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event;

[0089] (3) When the first merged signal is an in-band signal, in addition to the interrupt event itself, the in-band signal also includes ancillary information such as interrupt vector information and interrupt cause. The interrupt controller contains a writable memory address space for transmitting the above-mentioned ancillary information. By running the interrupt handler, the microcontroller reads the address information of the target interrupt event attached to the in-band signal (if the interrupt vector information resources are sufficient, it can even be mapped to different interrupt vectors). Thus, the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event can be determined by addressing, without having to poll the interrupt cause register corresponding to each interrupt event through the bus, thereby reducing latency.

[0090] For example, such as Figure 4A As shown, based on Figure 2 In step S140, the microcontroller first sets a reset register corresponding to the target hardware abstraction based on the target interrupt event. Then, based on the reset timing of the target interrupt event, the reset register maps the reset operation corresponding to the target hardware abstraction. That is, the hardware uses multiple hardware abstraction reset registers as interfaces with the microcontroller, which controls when to write to which reset register, thereby sequentially triggering reset operations corresponding to multiple hardware abstractions according to their reset timings.

[0091] For example, specifically, when the target hardware abstraction is PF, the microcontroller sets at least one reset register of PF (PF reset register 1, ..., PF reset register n, where n is a positive integer), and then, based on the reset timing of PF, the reset registers of PF are mapped to the reset operation of PF; when the target hardware abstraction is VF1, the microcontroller sets at least one reset register of VF1 (VF1 reset register 1, ..., VF1 reset register n, where n is a positive integer), and then, based on the reset timing of VF1, the reset registers of VF1 are mapped to the reset operation of VF1; when the target hardware abstraction is VF2, similar operations as described above are performed, and will not be repeated here. It should be noted that the embodiments of this disclosure do not limit the type, number, etc., of the reset registers of the target hardware abstraction.

[0092] For example, such as Figure 4A As shown, the microcontroller unit and different hardware abstractions have different reset domains. For example, the reset domains of individual VFs are independent of each other, while the reset domain of the PF should include the PF itself and all VFs. For example, the microcontroller unit and its interrupt control logic reside in other reset domains independent of the PF or VF reset domains, and the reset domain where the microcontroller unit and its interrupt control logic reside are less likely to be reset (i.e., more "ON" reset domains) compared to the PF or VF reset domains.

[0093] For example, specifically, as shown in Table 1 below, in Figure 2 After step S140, when the target hardware abstraction is PF (i.e., the target reset event is the FLR of PF), PF, VF1, and VF2 are all reset; when the target hardware abstraction is one of VF1 and VF2 (i.e., the target reset event is the FLR of VF1 or VF2), only the target hardware abstraction is reset, and PF is not reset; however, for the microcontroller unit and its interrupt control logic, it can only be reset by the system reset event, and is not affected by the reset events of PF, VF1, or VF2.

[0094] For example, for system reset events such as cold reset, warm reset, or hot reset (referred to as the second reset event), after the second reset event is triggered, the microcontroller unit and its interrupt control logic, power supply (PF), and multiple virtual function units (VFs) can all be reset. Specifically, as shown in Table 1 below, when the second reset event is a cold reset, warm reset 2, or hot reset 2, after the second reset event is triggered, the microcontroller unit and its interrupt control logic, PF, and multiple VFs can all be reset; when the second reset event is a warm reset 1 or hot reset 1, the PF and multiple VFs can all be reset, while the microcontroller unit and its interrupt control logic remain unaffected.

[0095] Table 1 Division of the reset region

[0096]

[0097] It should be noted that the division of the reset domain shown in Table 1 is only an example. The specific method of resetting domain division can be selected according to actual needs, and the embodiments of this disclosure do not limit it.

[0098] It should be noted that the reset event or second reset event provided in at least one embodiment of this disclosure is not limited to the description above, and other reset types can be selected according to actual needs. This disclosure does not limit this.

[0099] In the reset method provided in at least one embodiment of this disclosure, when it is necessary to modify the reset event during or after the reset operation, the interrupt handler can be updated by modifying the firmware in the microcontroller unit. Specifically, even after chip fabrication is complete, the firmware can still be modified through the microcontroller unit's memory interface to modify the contents of the interrupt handlers corresponding to different hardware abstractions, thus eliminating the need for hardware modification.

[0100] Figure 4B This is a schematic diagram of a hardware reset method; Figure 4C This is a schematic diagram of another hardware reset method.

[0101] For example, in such Figure 4B In the example shown, after initiating a function-level reset (FLR) of PF, VF1, or VF2, the function registers of PF, VF1, or VF2 are used to subdivide multiple reset signals corresponding to PF, VF1, and VF2 respectively (PF reset signal 1, ... PF reset signal n, VF1 reset signal 1, ... VF1 reset signal n, VF2 reset signal 1, ... VF2 reset signal n, where n is a positive integer), and then these reset signals are used to trigger the corresponding reset operation.

[0102] However, once these reset signals are generated, they are difficult to modify. In this case, due to the complexity of the reset timing of multiple hardware abstractions, it is difficult to eliminate errors in timing sequence. Therefore, before the chip tapeout is completed, the reset timing and various corner cases need to be fully verified to ensure that the control timing of the hardware logic is correct and can handle various complex extreme cases, which greatly increases the workload. Once the chip tapeout is completed, even if unexpected extreme cases are encountered, they cannot be directly modified, resulting in poor flexibility.

[0103] For example, in such Figure 4CIn the example shown, after initiating a function-level reset (FLR) for PF, VF1, or VF2, reset registers (PF reset register 1, ..., PF reset register n, VF1 reset register 1, ..., VF1 reset register n, VF2 reset register 1, ..., VF2 reset register n, where n is a positive integer) can be set for PF, VF1, and VF2 respectively. Then, the software on the host (e.g., the driver) performs fine-grained reset control on each reset register to trigger the corresponding reset operation.

[0104] However, the software on the host computer can only configure multiple reset registers sequentially, preventing parallel control. Furthermore, the long latency between the host and the PCIe device (typically exceeding 600ns for a two-stage PCIe switch) increases time costs, hindering real-time control. Additionally, this approach requires the host software to have a deep understanding of the PCIe device's underlying hardware. If the reset timing itself is complex, it exposes the hardware's complexity entirely to the host software, significantly complicating implementation. Moreover, besides the reset registers, the reset process requires protecting and cleaning various hardware abstraction data paths, involving complex underlying hardware structures and control timings. These are not suitable for complete exposure to the host software, and the high latency between the host and the PCIe device further exacerbates the control difficulties.

[0105] For example, in Figure 4A In the example, multiple hardware-abstracted resets are treated as multiple independent reset events, which are then converted into multiple interrupt events provided to the microcontroller unit. Different reset operations are run as different interrupt handlers on the firmware of the microcontroller unit. Therefore, when modifications to the reset events are needed, neither hardware updates nor modifications to the host software are required; only the firmware on the control unit needs to be updated.

[0106] For example, compared to Figure 4B The plan, in Figure 4A In this approach, even after the chip tape-out is completed, the reset timing of the target hardware abstraction (PF, VF1, or VF2) can still be updated by updating the firmware on the microcontroller unit. This allows for modifications even in the event of unexpected extreme conditions, thus greatly improving flexibility.

[0107] For example, compared to Figure 4C The plan, in Figure 4AIn this solution, the software only needs to initiate a reset event and reconfigure the data path after the reset, thus greatly reducing the complexity of the software on the host. Furthermore, since the microcontroller unit and the PCIe device are on the same chip, the distance of the control path from the microcontroller unit to other hardware abstractions is very short, thus greatly reducing latency; and, when controlling complex reset timings, the firmware on the microcontroller unit also significantly improves real-time performance with low latency compared to the software on the host.

[0108] Therefore, in the hardware reset method provided in at least one embodiment of this disclosure, the microcontroller unit assists in processing the reset operation of the target hardware abstraction. Even after the chip tape-out is completed, the reset timing of the target interrupt event can still be modified by updating the microcontroller unit, which improves the reliability and flexibility of hardware reset. Since the microcontroller unit and the PCIe device are on the same chip, the control path delay from the microcontroller unit to other hardware abstractions is small, which improves the real-time performance when controlling complex reset timing.

[0109] It should be noted that, Figures 4A to 4C The hardware reset method described herein is merely exemplary. The types and number of hardware abstractions, the division of reset domains, and the implementation form of microcontrollers can be selected according to actual needs, and this disclosure does not impose any limitations on these aspects.

[0110] In some examples, there is a first data to be cleaned in the data path corresponding to the target interrupt event. The first data to be cleaned includes, for example, information left over from the previous hardware abstraction reset, transaction information generated when requesting the target hardware abstraction to reset, etc. Before triggering the reset operation corresponding to the target hardware abstraction, the reset method further includes: cleaning the first data to be cleaned; after the first data to be cleaned is cleaned, modifying the flag bit corresponding to the first data to be cleaned to 0; and cleaning the flag bit corresponding to the first data to be cleaned.

[0111] For example, the hardware logic for cleaning the first data to be cleaned includes a first buffer, which contains multiple entries, each of which has a corresponding tag. Cleaning the first data to be cleaned includes: using a microcontroller to set a cleanup register to determine the target entry corresponding to the target interrupt event among the multiple entries; cleaning the target entry and releasing the target tag corresponding to the target entry; and generating a first response signal based on the released target tag to indicate that the cleaning of the first data to be cleaned is complete.

[0112] For example, the first data to be cleaned records the return status of multiple first completed packets. Cleaning the first data to be cleaned includes: using the microcontroller to set a time register to determine whether to start cleaning; if some of the first completed packets have not returned after a first predetermined time, cleaning is started.

[0113] For example, cleaning the first data to be cleaned also includes: using the microcontroller to set a discard register to determine whether there is a newly returned first complete packet in part of the first complete packet after cleaning is started; and discarding the newly returned first complete packet.

[0114] For example, the first data to be cleaned may also include multiple first requests, such as register access requests; cleaning the first data to be cleaned may also include: using the microcontroller to set a discard register to determine whether there are any new first requests after cleaning is started; and discarding the new first requests.

[0115] Figure 5 This is a schematic diagram of an example of a flag bit corresponding to the first data to be cleaned in the configuration space corresponding to the hardware abstraction provided in at least one embodiment of this disclosure.

[0116] For example, such as Figure 5 As shown, the configuration space corresponding to each hardware abstraction includes a device status section and a device control section. The device status section includes a flag bit (Transaction Pending bit) corresponding to the first piece of data to be cleared. For example, the flag bit corresponding to the first piece of data to be cleared can be... Figure 5 The 6th bit in the device status section (i.e., TransactionsPending).

[0117] For example, the flag corresponding to the first data to be cleaned reflects the basic situation of the data path corresponding to the target interruption event, and records the return status of multiple first completion packets. These first completion packets may include, for example, the access completion status of all non-posted transactions; non-posted transactions may include, for example, read transaction CfgRd, write transaction CfgWr, read memory transaction MemRd, etc. Specifically, the first completion packet may include the initiation operation of a reset event (e.g., Figure 3 The method shown sets the boot reset bit of the target hardware abstraction to 1 (i.e., Initiate FLR bit = 1). For example, if the first completion packet does not return, it may hinder the cleanup of the data path.

[0118] For example, before triggering the reset operation corresponding to the target hardware abstraction, the first data to be cleaned is started; after the first data to be cleaned is cleaned, the flag bit corresponding to the first data to be cleaned is modified to 0 (i.e., TransactionsPending bit = 0); the flag bit corresponding to the first data to be cleaned is then cleared. That is, the hardware eventually clears all the first data to be cleaned along with the flag bit corresponding to the first data to be cleaned.

[0119] In some examples, the interrupt handler's execution time does not exceed a second predetermined time. For instance, within the second predetermined time, the cleanup of the data path cannot begin until these pending transactions have actually returned the first completion packet. Taking a Functional Level Reset (FLR) as an example, according to the PCIe protocol, the interrupt handler must complete the FLR within 100ms; during the FLR, the hardware abstractions are invisible to the host, and the host cannot access the hardware abstractions; and when the FLR completes, the host driver can initialize the FLR to the enabled state through a "write 1" transaction (CfgWr=1).

[0120] In some examples, the FLR cleanup process includes an optional timeout mechanism: even if some first completion packets among multiple first completion packets have not been returned after a first predetermined time (which may differ from the second predetermined time, e.g., tens of milliseconds), cleanup still needs to be initiated. For example, if a new first completion packet is still returned after the second predetermined time, the new returned first completion packet can be considered an unexpected completion, and thus the new returned first completion packet or the newly sent first request can be silently discarded.

[0121] Therefore, the data path cleaning process should at least include:

[0122] (1) After the first predetermined time has elapsed, the cleanup is started, and before the FLR starts, the first data to be cleaned, along with the cleanup flag, is completely cleaned up.

[0123] (2) During FLR, newly sent requests can be silently discarded;

[0124] (3) During FLR, the newly returned first complete packet can also be silently discarded (the corresponding credit needs to be released);

[0125] (4) The FLR itself must be completed within the second scheduled time.

[0126] For example, if the cleanup is for the first piece of data to be cleaned corresponding to the target hardware abstraction, it should not affect the normal processing of transactions in other hardware abstractions, nor should it clean up pending transactions in other hardware abstractions. Therefore, based on the hardware cleanup logic, a cleanup module for multiple hardware abstractions needs to be added to ensure that, while meeting the cleanup requirements described above, the cleanup of the data path of the target hardware abstraction does not affect the normal data transmission of other hardware abstractions.

[0127] Figure 6 A schematic diagram illustrating another example of a hardware reset method provided in at least one embodiment of this disclosure. For example, Figure 6 Examples are used for, such as Figure 4AThe data path is cleared during the reset operation shown.

[0128] For example, such as Figure 6 As shown, the hardware logic used to clean up the first data to be cleaned includes a first buffer, which contains multiple entries (i.e., each row in the table represents one entry). For example, each entry includes a validity flag v, a PF number / VF number, and a request content. Each entry also has a corresponding label (not shown in the figure). For example, the PF number / VF number indicates which hardware abstraction (PF, VF1, or VF2) the entry corresponds to, the request content is a specific request for resetting the hardware abstraction (PF request 1, PF request 2...VF1 request 1, VF1 request 2...VF2 request 1, VF2 request 2...), and the validity flag v indicates the return status of the first completion packet (e.g., v=0 indicates a normal state, v=1 indicates that the cleanup action has been initiated).

[0129] For example, such as Figure 6 As shown, the hardware logic for cleaning up the first data to be cleaned includes a response buffer, a first buffer control module, a cleanup module, and a first response signal generation module. The response buffer can be accessed through the first buffer control module. For example, in a normal cleanup process, the response buffer first collects multiple returned first completion packets, releases the corresponding tags, and then returns the generated response signal to the downstream data path. The branch path where the cleanup module is located only operates during the reset of the hardware abstraction (e.g., functional level reset (FLR)). After cleaning up the first data to be cleaned corresponding to the target hardware abstraction (PF, VF1, or VF2), the first response signal generation module generates a first response signal (dummy response). The first response signal is used to terminate the pending non-reporting transactions corresponding to the target hardware abstraction (PF, VF1, or VF2) for the downstream data path. Furthermore, the data paths of the response signal and the first response signal are arbitrated by an arbitrator to prevent the reset operation of the target hardware abstraction from interfering with the normal data transmission of other hardware abstractions.

[0130] For example, such as Figure 6As shown, firstly, the microcontroller sets cleanup registers (PF cleanup register, VF1 cleanup register, and VF2 cleanup register) to determine the target entry corresponding to the target interrupt event among multiple entries, i.e., determining whether to clean up PF, VF1, or VF2. Secondly, the cleanup module sends a cleanup request for the target entry to the first buffer, then cleans the target entry and releases the target tag corresponding to the target entry. Specifically, the cleanup module can scan all entries in the first buffer one by one and update the corresponding valid flag v. For example, when the target hardware abstraction is VF1, only entries found to be VF1 are cleaned; entries of other hardware abstractions are skipped. However, when the target hardware abstraction is PF, in addition to cleaning up PF entries, it is also necessary to clean up all VF entries managed by PF. Thirdly, based on the released target tag, a first response signal is generated to indicate that the first data to be cleaned has been cleaned up.

[0131] For example, such as Figure 6 As shown, due to the timeout mechanism of functional level reset, multiple time registers (PF time register, VF1 time register, and VF2 time register) can be set on the first buffer control module. The microcontroller unit can select the appropriate time to start the cleanup of the target hardware abstraction (PF, VF1, or VF2) by setting the time registers. For example, when the microcontroller unit receives a target interrupt event, it can still wait for a first predetermined time (e.g., tens of milliseconds) to wait for the return of the first completion packet. If, after the first predetermined time has elapsed, some of the first completion packets have still not returned, the cleanup module's cleanup action also needs to be activated.

[0132] For example, such as Figure 6 As shown, if a previously unreturned first completion packet is still returned after data cleanup is enabled, the request discard submodule silently discards the newly returned first completion packet and processes the corresponding credit. For example, the microcontroller first sets the discard registers (PF discard register, VF1 discard register, and VF2 discard register) to determine the first completion packet corresponding to the target hardware abstraction (PF, VF1, or VF2), thereby determining whether a new first completion packet has been returned after cleanup is enabled. If so, the newly returned first completion packet is silently discarded, and the credit corresponding to the first completion packet (e.g., the credit of PF, VF1, or VF2 during FLR) is released.

[0133] For example, after data cleanup is enabled, first requests may continue to be sent (including requests in both the host path and the DMA / interrupt path). Therefore, when the microcontroller sets the discard register, it is necessary to determine the first request corresponding to the target hardware abstraction (PF, VF1 or VF2) to determine whether there are any new first requests after cleanup is enabled. If so, the new first requests are discarded, thus avoiding the continuous filling of new requests while cleaning the first buffer.

[0134] For example, after the first piece of data to be cleaned is cleaned, the flag bit corresponding to the first piece of data to be cleaned is modified to 0 (i.e., Transactions Pending bit = 0), thereby ending the cleanup. Then, the reset operation of the target hardware abstraction (PF, VF1, or VF2) is initiated (e.g., Figure 2 (Step S140).

[0135] In the reset method provided in at least one embodiment of this disclosure, by setting the registers of the hardware module, on the one hand, the corresponding operation of the target hardware abstraction can be determined in each process, thereby ensuring that the clearing of the data path of the target hardware abstraction does not affect the normal data transmission of other hardware abstractions. On the other hand, it can also avoid the inherent time constraints of hardware logic when controlling complex timing, and provide greater flexibility for the reset timing of hardware abstractions in the reset operation.

[0136] Figure 7 Another exemplary flowchart of a hardware reset method provided for at least one embodiment of this disclosure. For example, Figure 7 For example Figure 2 A specific example of the reset method shown.

[0137] For example, such as Figure 7 As shown, in the entire reset timing of the target hardware abstraction, the software and hardware running on the host, as well as the firmware running on the microcontroller unit, jointly complete the entire reset process of the target hardware abstraction. For example, Figure 7 The left side shows the software's actions on the host machine, mainly used to initiate reset events and reconfigure the data path after a reset. Figure 7 The middle section describes the hardware operation process, completing physical operations such as reset and cleanup. For example, Figure 7 The right side shows the firmware's operation process, which is mainly handled by the microcontroller unit for interrupting reset events and configuring various reset or cleanup registers.

[0138] For example, such as Figure 7As shown, taking a Functional Level Reset (FLR) as an example, firstly, in the software, the host determines to initiate the FLR of the target hardware abstraction. Then, the driver sends a "write 1" transaction (CfgWr = 1) to the start-reset bit in the configuration space corresponding to the target hardware abstraction. Further, the hardware sets the start-reset bit of the target hardware abstraction to 1 (i.e., Initiate FLR bit = 1) and returns the corresponding completion packet. Then, the hardware converts the reset event for the target hardware abstraction into a target interrupt event and provides the target interrupt event to the microcontroller unit (i.e., the execution unit). Figure 2 Steps S110 to S120 in the process are used to enable the microcontroller to initiate an interrupt operation.

[0139] For example, such as Figure 7 As shown, after receiving the target interrupt event, the microcontroller starts the interrupt handler on the firmware to execute... Figure 2 In step S130, the microcontroller sets the time register to determine whether to start cleanup. Once cleanup begins, the microcontroller sets the cleanup register and the discard register to enable the hardware to perform cleanup operations and waits for the flag bit corresponding to the first data to be cleaned to be written to 0. Further, the hardware begins cleanup of the first data to be cleaned and begins discarding newly returned first completion packets and newly sent first requests. After cleanup is complete, the flag bit corresponding to the first data to be cleaned is written to 0 (i.e., Transactions Pending bit = 0) and the microcontroller is notified. The hardware then stops cleanup and continues to discard newly returned first completion packets and newly sent first requests. Further, the microcontroller sets the reset register of the target hardware abstraction, and then the hardware begins to reset (i.e., executes...). Figure 2 (Step S140); After waiting for a period of time, the microcontroller exits the interrupt handler and repeats the above operation before the next reset begins; After the hardware reset is completed, a completion packet is returned to the host to indicate that the reset is complete.

[0140] For example, such as Figure 7As shown, while the microcontroller handles interrupt events and the hardware performs cleanup and reset, the software waits for the "write 1" transaction of the start reset bit to complete (i.e., Initiate FLR bit = 1). The driver then stops the transaction on the functional unit where the target hardware abstraction resides by disabling Bus Master Enable (BME) or Memory Space Enable (MSE), i.e., setting BME / MSE = 0. The driver for the target hardware abstraction is then unloaded from the operating system (OS). The driver is then reloaded, and the OS enumerates target hardware abstractions to further determine the corresponding target hardware abstraction, and then waits for the completion packet to return. Further, after the completion packet returns, the driver begins executing other configurations.

[0141] For example, an intermediate completion packet can be returned before the completion packet is returned. The intermediate completion packet may include a configuration request retry status (CRS) to respond to an early non-reportable transaction (e.g., CfgWr / CfgRd operation).

[0142] It should be noted that the microcontroller writes many hardware registers in the firmware interrupt handler for target hardware abstraction (HAI) reset actions or for data path protection and cleanup actions. Once the target HAI has completed its reset, which is the end of the interrupt handler, the microcontroller needs to unregister these registers, restoring the hardware to its normal initialized state. Specifically, the entire interrupt handler should not exceed a second predetermined time limit (e.g., 100ms).

[0143] In the hardware reset method provided in at least one embodiment of this disclosure, the microcontroller unit assists in processing the reset operation of the target hardware abstraction. Even after the chip tape-out is completed, the reset timing of the target interrupt event can still be modified by updating the microcontroller unit, which improves the reliability and flexibility of hardware reset. Since the microcontroller unit and the PCIe device are on the same chip, the control path delay from the microcontroller unit to other hardware abstractions is small, which improves the real-time performance when controlling complex reset timing.

[0144] Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0145] For example, such as Figure 8 As shown, the electronic device 200 includes an electronic device 210 and a microcontroller unit 220.

[0146] For example, electronic device 210 is configured to provide multiple hardware abstractions during operation, wherein the multiple hardware abstractions include a first hardware abstraction and one or more second hardware abstractions, the first hardware abstraction being configured to manage one or more second hardware abstractions; additionally, electronic device 210 is also configured to convert multiple reset events for the multiple hardware abstractions into multiple interrupt events, wherein the multiple interrupt events correspond to the multiple hardware abstractions respectively; in some examples, electronic device 210 is also configured to provide the multiple interrupt events to microcontroller unit 220; that is, electronic device 210 can be configured to perform, for example Figure 2 The steps S110 to S120 are shown. For example, in some examples, the reset event includes a functional level reset (FLR).

[0147] For example, the microcontroller unit 220 is configured to, when implementing multiple hardware abstractions, receive multiple interrupt events, determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, and, based on the target hardware abstraction and the reset timing of the target interrupt event, trigger a reset operation corresponding to the target hardware abstraction. That is, the microcontroller unit 220 can be configured to perform, for example... Figure 2 The steps S130 to S140 are shown.

[0148] For example, in some examples, the microcontroller unit 220 is also configured to set a reset register corresponding to each of a plurality of hardware abstractions, thereby mapping the reset operation of the electronic device using the plurality of reset registers.

[0149] For example, in some examples, the electronic device 210 is further configured to, when the number of multiple interrupt events is greater than the number of input interfaces of the microcontroller, combine the multiple interrupt events into a first combined signal and provide the first combined signal to the microcontroller; or, when the number of multiple interrupt events is less than or equal to the number of input interfaces of the microcontroller, provide the multiple interrupt events to the multiple input interfaces of the microcontroller respectively.

[0150] For example, in some examples, the first merge signal includes a sideband signal containing the target interrupt event; the microcontroller unit 220 is also configured to read the interrupt cause register corresponding to the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0151] For example, in some examples, the first merge signal includes an in-band signal containing the target interrupt event and the address information of the target interrupt event; the microcontroller unit 220 is also configured to read the address information of the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

[0152] For example, in some examples, the microcontroller 220 is also configured to set a reset register corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event; and to map a reset operation corresponding to the target hardware abstraction based on the reset timing of the target interrupt event.

[0153] For example, in some examples, the configuration space corresponding to each of the multiple hardware abstractions includes a start-reset bit; the electronic device 210 is also configured to set the start-reset bit in the configuration space corresponding to the target hardware abstraction to 1 to obtain a reset event for the target hardware abstraction.

[0154] For example, in some examples, multiple hardware abstractions include a first hardware abstraction and multiple second hardware abstractions. For instance, after triggering a reset operation corresponding to a target hardware abstraction, if the target hardware abstraction is the first hardware abstraction, the first hardware abstraction and multiple second hardware abstractions are reset; or, if the target hardware abstraction is one of the multiple second hardware abstractions, only the target hardware abstraction is reset.

[0155] For example, in some examples, electronic device 210 is further configured to trigger a reset operation corresponding to a second reset event, so as to reset the microcontroller unit, the first hardware abstraction, and the plurality of second hardware abstractions. In some examples, the second reset event includes a cold reset, a warm reset, or a thermal reset.

[0156] For example, in some examples, there is first data to be cleared in the data path corresponding to the target interrupt event; before triggering the reset operation corresponding to the target hardware abstraction, the electronic device 210 is also configured to clear the first data to be cleared; after the first data to be cleared is cleared, the flag bit corresponding to the first data to be cleared is modified to 0; and the flag bit corresponding to the first data to be cleared is cleared.

[0157] For example, in some examples, the first buffer includes multiple entries, each of which has a corresponding tag; the electronic device 210 is also configured to use the microcontroller to set a cleanup register to determine the target entry corresponding to the target interruption event among the multiple entries; clean up the target entry and release the target tag corresponding to the target entry; and generate a first response signal based on the released target tag to indicate that the first data to be cleaned has been cleaned up.

[0158] For example, in some examples, the hardware is configured to implement multiple hardware abstractions, and the hardware includes a microcontroller unit for reset operations; the electronic device 210 is also configured to modify the firmware in the microcontroller unit to update the interrupt handler. For example, the firmware runs the interrupt handler during operation, which performs the following actions in response to interrupt events received by the microcontroller unit: determining the target hardware abstraction corresponding to a target interrupt event among multiple interrupt events and the reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction and the reset timing of the target interrupt event. For example, the execution time of the interrupt handler does not exceed a second predetermined time.

[0159] Due to the above description, for example Figure 2 The details of the operation of the aforementioned electronic device 200 have already been described in the hardware reset method illustrated above. Therefore, for the sake of brevity, they will not be repeated here. For relevant details, please refer to the above description. Figures 2-7 The description.

[0160] It should be noted that, Figure 8 The electronic device 210 and microcontroller unit 220 in the illustrated electronic device 200 can be configured, respectively, as software, hardware, firmware, or any combination thereof to perform a specific function. For example, the electronic device 210 and microcontroller unit 220 may correspond to a dedicated integrated circuit, pure software code, or a module combining software and hardware. As an example, see... Figure 8 The described electronic device may be a PC computer, tablet device, personal digital assistant, smartphone, web application or other device capable of executing program instructions, but is not limited thereto.

[0161] At least one embodiment of this disclosure also provides another electronic device, which includes one or more processors and one or more memories; the one or more memories store one or more computer program modules; the one or more computer program modules are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more computer program modules include a reset method for implementing the hardware provided in the embodiments of this disclosure described above or a configuration method for hardware reset. For example, the processor may be a single-core processor or a multi-core processor.

[0162] Figure 9 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0163] For example, such as Figure 9As shown, the electronic device 300 includes one or more processors 310 and one or more memories 320. For example, the one or more memories 320 are used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The one or more processors 310 are used to execute the non-transitory computer-readable instructions, which, when executed by the one or more processors 310, can perform one or more steps of the hardware reset method or the configuration method for hardware reset as described above. The one or more memories 320 and the one or more processors 310 can be interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0164] For example, one or more processors 310 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a digital signal processor (DSP), or other processing units with hardware reset capability and / or program execution capability, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) may be an x86, RISC-V, or ARM architecture. One or more processors 310 may be general-purpose processors or special-purpose processors, capable of controlling other components in the electronic device 300 to perform desired functions.

[0165] For example, one or more memories 320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable optical disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and one or more processors 310 may run one or more computer program modules to implement various functions of the electronic device 300. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0166] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 300 can be referred to the description above of the hardware reset method or the configuration method for hardware reset provided in at least one embodiment of this disclosure, and will not be repeated here.

[0167] Figure 10 This is a schematic block diagram of yet another electronic device provided for at least one embodiment of the present disclosure.

[0168] For example, such as Figure 10 As shown, the electronic device 400 is, for example, suitable for implementing the hardware reset method or the configuration method for hardware reset provided in the embodiments of this disclosure. It should be noted that... Figure 10 The illustrated electronic device 400 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0169] For example, such as Figure 10 As shown, electronic device 400 may include a processing unit (e.g., central processing unit, graphics processor, etc.) 41, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 42 or a program loaded from storage device 48 into random access memory (RAM) 43. RAM 43 also stores various programs and data required for the operation of electronic device 400. Processing unit 41, ROM 42, and RAM 43 are interconnected via bus 44. Input / output (I / O) interface 45 is also connected to bus 44. Typically, the following devices can be connected to I / O interface 45: input devices 46 including, for example, touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 47 including, for example, liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 48 including, for example, magnetic tape, hard disk, etc.; and communication devices 49. Communication device 49 allows electronic device 400 to communicate wirelessly or wiredly with other electronic devices to exchange data.

[0170] Although Figure 10 An electronic device 400 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 400 may alternatively implement or have more or fewer devices.

[0171] For detailed information and technical effects regarding electronic device 400, please refer to the above description of the hardware reset method; it will not be repeated here.

[0172] Figure 11 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure.

[0173] For example, such as Figure 11 As shown, storage medium 500 stores non-transitory computer-readable instructions 510. For example, when the non-transitory computer-readable instructions 510 are executed by a computer, one or more steps of a hardware reset method or a configuration method for hardware reset as described above are performed.

[0174] For example, this storage medium 500 can be applied to Figure 9In the illustrated electronic device 300, for example, storage medium 500 can be one of one or more memories 320 in the electronic device 300. For example, a description of storage medium 500 can be found here. Figure 9 The corresponding descriptions of one or more memories 320 in the illustrated electronic device 300 are not repeated here.

[0175] The following points need to be clarified regarding this disclosure:

[0176] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0177] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0178] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A hardware reset method, comprising: Multiple reset events for multiple hardware abstractions are converted into multiple interrupt events, wherein each of the multiple interrupt events corresponds to one of the multiple hardware abstractions; The multiple interrupt events are provided to the microcontroller unit; The microcontroller unit determines the target hardware abstraction corresponding to the target interrupt event among the plurality of interrupt events and the reset timing of the target interrupt event; Based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, a reset operation corresponding to the target hardware abstraction is triggered.

2. The hardware reset method according to claim 1, wherein, Providing the plurality of interrupt events to the microcontroller includes: When the number of interrupt events exceeds the number of input interfaces of the microcontroller, the multiple interrupt events are combined into a first combined signal. The first merged signal is provided to the microcontroller unit; or, When the number of interrupt events is less than or equal to the number of input interfaces of the microcontroller, the interrupt events are respectively provided to the multiple input interfaces of the microcontroller.

3. The hardware reset method according to claim 2, wherein, The first merged signal includes a sideband signal, and the sideband signal contains the target interrupt event. The microcontroller unit determines the target hardware abstraction corresponding to the target interrupt event among the plurality of interrupt events and the reset timing of the target interrupt event, including: The microcontroller reads the interrupt cause register corresponding to the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

4. The hardware reset method according to claim 2, wherein, The first merged signal includes an in-band signal, which contains the target interrupt event and its address information. The microcontroller unit determines the target hardware abstraction corresponding to the target interrupt event among the plurality of interrupt events and the reset timing of the target interrupt event, including: The microcontroller reads the address information of the target interrupt event to determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

5. The hardware reset method according to claim 1, wherein, Based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, a reset operation corresponding to the target hardware abstraction is triggered, including: Based on the target hardware abstraction corresponding to the target interrupt event, the microcontroller sets a reset register corresponding to the target hardware abstraction; Based on the reset timing of the target interrupt event, the reset register maps to the reset operation corresponding to the target hardware abstraction.

6. The hardware reset method according to claim 1, wherein, The configuration space corresponding to each of the plurality of hardware abstractions includes startup and reset bits. The reset method further includes: Set the startup reset ratio in the configuration space corresponding to the target hardware abstraction to 1 to obtain the reset event for the target hardware abstraction.

7. The hardware reset method according to claim 1, wherein, The plurality of hardware abstractions includes a first hardware abstraction and a plurality of second hardware abstractions. After the reset operation corresponding to the target hardware abstraction is triggered When the target hardware abstraction is the first hardware abstraction, the first hardware abstraction and the plurality of second hardware abstractions are reset. or, When the target hardware abstraction is one of the plurality of second hardware abstractions, only the target hardware abstraction is reset.

8. The hardware reset method according to claim 7, wherein, The reset events include functional-level resets.

9. The hardware reset method according to claim 1, wherein, The plurality of hardware abstractions includes a first hardware abstraction and a plurality of second hardware abstractions. The reset method further includes: A reset operation corresponding to the second reset event is triggered to reset the microcontroller unit, the first hardware abstraction, and the plurality of second hardware abstractions.

10. The hardware reset method according to claim 9, wherein, The second reset event includes cold reset, warm reset, or hot reset.

11. The hardware reset method according to claim 1, wherein, The data path corresponding to the target interruption event contains a first set of data to be cleaned. Prior to triggering the reset operation corresponding to the target hardware abstraction, the reset method further includes: Clean up the first set of data to be cleaned; After the first data to be cleaned is cleaned, the flag bit corresponding to the first data to be cleaned is modified to 0; Clear the flag bit corresponding to the first data to be cleared.

12. The hardware reset method according to claim 11, wherein, The first buffer contains multiple entries, each of which has a corresponding label. Cleaning the first data to be cleaned includes: The microcontroller is used to set a cleanup register to determine the target entry corresponding to the target interrupt event among the plurality of entries; Clean up the target entries and release the target tags corresponding to the target entries; Based on the released target tag, a first response signal is generated to indicate that the first data to be cleaned has been cleaned.

13. The hardware reset method according to claim 11, wherein, The first data to be cleaned records the return status of multiple first completion packets. Cleaning the first data to be cleaned includes: The time register is set using the microcontroller unit to determine whether to enable the cleanup; If some of the first completed packages among the plurality of first completed packages have not returned after the first predetermined time has elapsed, the cleanup process is initiated.

14. The hardware reset method according to claim 13, wherein, Cleaning the first data to be cleaned also includes: The microcontroller is used to set a drop register to determine whether there is a new first completion packet returned in the first completion packet after the cleanup is started; Discard the newly returned first completion package.

15. The hardware reset method according to claim 13, wherein, The first data to be cleaned also includes multiple first requests. Cleaning the first data to be cleaned also includes: The microcontroller unit is used to set a discard register to determine whether a new first request has been sent after the cleanup is initiated. Discard the newly sent first request.

16. A configuration method for hardware reset, wherein, The hardware is configured to implement multiple hardware abstractions, and the hardware includes a microcontroller unit for reset operations. The configuration method includes: Modify the firmware in the microcontroller to update the interrupt handler. The firmware runs the interrupt handler during operation, and the interrupt handler is used to execute interrupt events received by the microcontroller unit. Determine the target hardware abstraction corresponding to the target interrupt event among the plurality of interrupt events and the reset timing of the target interrupt event; Based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, a reset operation corresponding to the target hardware abstraction is triggered.

17. The configuration method for hardware reset according to claim 16, wherein, The interrupt handler runs for no more than a second predetermined time.

18. An electronic device comprising: An electronic device is configured to provide multiple hardware abstractions during operation, wherein the multiple hardware abstractions include a first hardware abstraction and one or more second hardware abstractions, the first hardware abstraction being configured to manage the one or more second hardware abstractions. The electronic device is further configured to convert multiple reset events for multiple hardware abstractions into multiple interrupt events, wherein the multiple interrupt events correspond to the multiple hardware abstractions respectively; The microcontroller unit is configured to, when implementing the plurality of hardware abstractions, receive the plurality of interrupt events, determine the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event, and trigger a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event.

19. The electronic device according to claim 18, wherein, The microcontroller unit is further configured to set a reset register corresponding to each of the plurality of hardware abstractions, and to map the reset operation of the electronic device using the plurality of reset registers.

20. An electronic device, comprising: One or more processors; One or more memory stores one or more computer program modules; The one or more computer program modules are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more computer program modules are used to implement the hardware reset method according to any one of claims 1-15 or the hardware reset configuration method according to any one of claims 16-17.

21. A storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement the hardware reset method of any one of claims 1-15 or the hardware reset configuration method of any one of claims 16-17.

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